r600_pipe.h revision e2809849ecac69615ece294a55ee355afaac33d3
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30 31#include "pipe/p_state.h" 32#include "pipe/p_screen.h" 33#include "pipe/p_context.h" 34#include "util/u_math.h" 35#include "util/u_slab.h" 36#include "util/u_vbuf.h" 37#include "r600.h" 38#include "r600_public.h" 39#include "r600_shader.h" 40#include "r600_resource.h" 41 42#define R600_MAX_CONST_BUFFERS 2 43#define R600_MAX_CONST_BUFFER_SIZE 4096 44 45#ifdef PIPE_ARCH_BIG_ENDIAN 46#define R600_BIG_ENDIAN 1 47#else 48#define R600_BIG_ENDIAN 0 49#endif 50 51enum r600_atom_flags { 52 /* When set, atoms are added at the beginning of the dirty list 53 * instead of the end. */ 54 EMIT_EARLY = (1 << 0) 55}; 56 57/* This encapsulates a state or an operation which can emitted into the GPU 58 * command stream. It's not limited to states only, it can be used for anything 59 * that wants to write commands into the CS (e.g. cache flushes). */ 60struct r600_atom { 61 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 62 63 unsigned num_dw; 64 enum r600_atom_flags flags; 65 bool dirty; 66 67 struct list_head head; 68}; 69 70/* This is an atom containing GPU commands that never change. 71 * This is supposed to be copied directly into the CS. */ 72struct r600_command_buffer { 73 struct r600_atom atom; 74 uint32_t *buf; 75 unsigned max_num_dw; 76}; 77 78struct r600_atom_surface_sync { 79 struct r600_atom atom; 80 unsigned flush_flags; /* CP_COHER_CNTL */ 81}; 82 83struct r600_atom_db_misc_state { 84 struct r600_atom atom; 85 bool occlusion_query_enabled; 86 bool flush_depthstencil_enabled; 87}; 88 89enum r600_pipe_state_id { 90 R600_PIPE_STATE_BLEND = 0, 91 R600_PIPE_STATE_BLEND_COLOR, 92 R600_PIPE_STATE_CONFIG, 93 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 94 R600_PIPE_STATE_CLIP, 95 R600_PIPE_STATE_SCISSOR, 96 R600_PIPE_STATE_VIEWPORT, 97 R600_PIPE_STATE_RASTERIZER, 98 R600_PIPE_STATE_VGT, 99 R600_PIPE_STATE_FRAMEBUFFER, 100 R600_PIPE_STATE_DSA, 101 R600_PIPE_STATE_STENCIL_REF, 102 R600_PIPE_STATE_PS_SHADER, 103 R600_PIPE_STATE_VS_SHADER, 104 R600_PIPE_STATE_CONSTANT, 105 R600_PIPE_STATE_SAMPLER, 106 R600_PIPE_STATE_RESOURCE, 107 R600_PIPE_STATE_POLYGON_OFFSET, 108 R600_PIPE_STATE_FETCH_SHADER, 109 R600_PIPE_NSTATES 110}; 111 112struct r600_pipe_fences { 113 struct r600_resource *bo; 114 unsigned *data; 115 unsigned next_index; 116 /* linked list of preallocated blocks */ 117 struct list_head blocks; 118 /* linked list of freed fences */ 119 struct list_head pool; 120 pipe_mutex mutex; 121}; 122 123struct r600_screen { 124 struct pipe_screen screen; 125 struct radeon_winsys *ws; 126 unsigned family; 127 enum chip_class chip_class; 128 struct radeon_info info; 129 struct r600_tiling_info tiling_info; 130 struct util_slab_mempool pool_buffers; 131 struct r600_pipe_fences fences; 132 133 unsigned num_contexts; 134 unsigned use_surface; 135 136 /* for thread-safe write accessing to num_contexts */ 137 pipe_mutex mutex_num_contexts; 138}; 139 140struct r600_pipe_sampler_view { 141 struct pipe_sampler_view base; 142 struct r600_pipe_resource_state state; 143}; 144 145struct r600_pipe_rasterizer { 146 struct r600_pipe_state rstate; 147 boolean flatshade; 148 boolean two_side; 149 unsigned sprite_coord_enable; 150 unsigned clip_plane_enable; 151 unsigned pa_sc_line_stipple; 152 unsigned pa_cl_clip_cntl; 153 float offset_units; 154 float offset_scale; 155}; 156 157struct r600_pipe_blend { 158 struct r600_pipe_state rstate; 159 unsigned cb_target_mask; 160 unsigned cb_color_control; 161}; 162 163struct r600_pipe_dsa { 164 struct r600_pipe_state rstate; 165 unsigned alpha_ref; 166 ubyte valuemask[2]; 167 ubyte writemask[2]; 168 bool is_flush; 169}; 170 171struct r600_vertex_element 172{ 173 unsigned count; 174 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 175 struct u_vbuf_elements *vmgr_elements; 176 struct r600_resource *fetch_shader; 177 unsigned fs_size; 178 struct r600_pipe_state rstate; 179 /* if offset is to big for fetch instructio we need to alterate 180 * offset of vertex buffer, record here the offset need to add 181 */ 182 unsigned vbuffer_need_offset; 183 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; 184}; 185 186struct r600_pipe_shader { 187 struct r600_shader shader; 188 struct r600_pipe_state rstate; 189 struct r600_resource *bo; 190 struct r600_resource *bo_fetch; 191 struct r600_vertex_element vertex_elements; 192 struct tgsi_token *tokens; 193 unsigned sprite_coord_enable; 194 unsigned flatshade; 195 unsigned pa_cl_vs_out_cntl; 196 struct pipe_stream_output_info so; 197}; 198 199struct r600_pipe_sampler_state { 200 struct r600_pipe_state rstate; 201 boolean seamless_cube_map; 202}; 203 204/* needed for blitter save */ 205#define NUM_TEX_UNITS 16 206 207struct r600_textures_info { 208 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 209 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 210 unsigned n_views; 211 unsigned n_samplers; 212 bool samplers_dirty; 213 bool is_array_sampler[NUM_TEX_UNITS]; 214}; 215 216struct r600_fence { 217 struct pipe_reference reference; 218 unsigned index; /* in the shared bo */ 219 struct r600_resource *sleep_bo; 220 struct list_head head; 221}; 222 223#define FENCE_BLOCK_SIZE 16 224 225struct r600_fence_block { 226 struct r600_fence fences[FENCE_BLOCK_SIZE]; 227 struct list_head head; 228}; 229 230#define R600_CONSTANT_ARRAY_SIZE 256 231#define R600_RESOURCE_ARRAY_SIZE 160 232 233struct r600_stencil_ref 234{ 235 ubyte ref_value[2]; 236 ubyte valuemask[2]; 237 ubyte writemask[2]; 238}; 239 240struct r600_context { 241 struct pipe_context context; 242 struct blitter_context *blitter; 243 enum radeon_family family; 244 enum chip_class chip_class; 245 unsigned r6xx_num_clause_temp_gprs; 246 void *custom_dsa_flush; 247 struct r600_screen *screen; 248 struct radeon_winsys *ws; 249 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 250 struct r600_vertex_element *vertex_elements; 251 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; 252 struct pipe_framebuffer_state framebuffer; 253 unsigned cb_target_mask; 254 unsigned cb_color_control; 255 unsigned pa_sc_line_stipple; 256 unsigned pa_cl_clip_cntl; 257 /* for saving when using blitter */ 258 struct pipe_stencil_ref stencil_ref; 259 struct pipe_viewport_state viewport; 260 struct pipe_clip_state clip; 261 struct r600_pipe_shader *ps_shader; 262 struct r600_pipe_shader *vs_shader; 263 struct r600_pipe_state vs_const_buffer; 264 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 265 struct r600_pipe_state ps_const_buffer; 266 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 267 struct r600_pipe_rasterizer *rasterizer; 268 struct r600_pipe_state vgt; 269 struct r600_pipe_state spi; 270 struct pipe_query *current_render_cond; 271 unsigned current_render_cond_mode; 272 struct pipe_query *saved_render_cond; 273 unsigned saved_render_cond_mode; 274 /* shader information */ 275 boolean two_side; 276 unsigned sprite_coord_enable; 277 boolean export_16bpc; 278 unsigned alpha_ref; 279 boolean alpha_ref_dirty; 280 unsigned nr_cbufs; 281 struct r600_textures_info vs_samplers; 282 struct r600_textures_info ps_samplers; 283 284 struct u_vbuf *vbuf_mgr; 285 struct util_slab_mempool pool_transfers; 286 boolean have_depth_texture, have_depth_fb; 287 288 unsigned default_ps_gprs, default_vs_gprs; 289 290 /* States based on r600_state. */ 291 struct list_head dirty_states; 292 struct r600_command_buffer atom_start_cs; /* invariant state mostly */ 293 struct r600_atom_surface_sync atom_surface_sync; 294 struct r600_atom atom_r6xx_flush_and_inv; 295 struct r600_atom_db_misc_state atom_db_misc_state; 296 297 /* Below are variables from the old r600_context. 298 */ 299 struct radeon_winsys_cs *cs; 300 301 struct r600_range *range; 302 unsigned nblocks; 303 struct r600_block **blocks; 304 struct list_head dirty; 305 struct list_head resource_dirty; 306 struct list_head enable_list; 307 unsigned pm4_dirty_cdwords; 308 unsigned ctx_pm4_ndwords; 309 310 /* The list of active queries. Only one query of each type can be active. */ 311 int num_occlusion_queries; 312 struct list_head active_query_list; 313 unsigned num_cs_dw_queries_suspend; 314 unsigned num_cs_dw_streamout_end; 315 316 unsigned backend_mask; 317 unsigned max_db; /* for OQ */ 318 unsigned flags; 319 boolean predicate_drawing; 320 struct r600_range ps_resources; 321 struct r600_range vs_resources; 322 struct r600_range fs_resources; 323 int num_ps_resources, num_vs_resources, num_fs_resources; 324 325 unsigned num_so_targets; 326 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 327 boolean streamout_start; 328 unsigned streamout_append_bitmask; 329}; 330 331static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 332{ 333 atom->emit(rctx, atom); 334 atom->dirty = false; 335 if (atom->head.next && atom->head.prev) 336 LIST_DELINIT(&atom->head); 337} 338 339static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 340{ 341 if (!state->dirty) { 342 if (state->flags & EMIT_EARLY) { 343 LIST_ADD(&state->head, &rctx->dirty_states); 344 } else { 345 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 346 } 347 state->dirty = true; 348 } 349} 350 351/* evergreen_state.c */ 352void evergreen_init_state_functions(struct r600_context *rctx); 353void evergreen_init_atom_start_cs(struct r600_context *rctx); 354void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 355void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 356void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 357void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 358void evergreen_polygon_offset_update(struct r600_context *rctx); 359void evergreen_pipe_init_buffer_resource(struct r600_context *rctx, 360 struct r600_pipe_resource_state *rstate); 361void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, 362 struct r600_pipe_resource_state *rstate, 363 struct r600_resource *rbuffer, 364 unsigned offset, unsigned stride, 365 enum radeon_bo_usage usage); 366boolean evergreen_is_format_supported(struct pipe_screen *screen, 367 enum pipe_format format, 368 enum pipe_texture_target target, 369 unsigned sample_count, 370 unsigned usage); 371 372/* r600_blit.c */ 373void r600_init_blit_functions(struct r600_context *rctx); 374void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 375void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 376void r600_flush_depth_textures(struct r600_context *rctx); 377 378/* r600_buffer.c */ 379bool r600_init_resource(struct r600_screen *rscreen, 380 struct r600_resource *res, 381 unsigned size, unsigned alignment, 382 unsigned bind, unsigned usage); 383struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 384 const struct pipe_resource *templ); 385struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 386 void *ptr, unsigned bytes, 387 unsigned bind); 388void r600_upload_index_buffer(struct r600_context *rctx, 389 struct pipe_index_buffer *ib, unsigned count); 390 391 392/* r600_pipe.c */ 393void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 394 unsigned flags); 395 396/* r600_query.c */ 397void r600_init_query_functions(struct r600_context *rctx); 398 399/* r600_resource.c */ 400void r600_init_context_resource_functions(struct r600_context *r600); 401 402/* r600_shader.c */ 403int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 404void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 405int r600_find_vs_semantic_index(struct r600_shader *vs, 406 struct r600_shader *ps, int id); 407 408/* r600_state.c */ 409void r600_update_sampler_states(struct r600_context *rctx); 410void r600_init_state_functions(struct r600_context *rctx); 411void r600_init_atom_start_cs(struct r600_context *rctx); 412void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 413void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 414void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 415void *r600_create_db_flush_dsa(struct r600_context *rctx); 416void r600_polygon_offset_update(struct r600_context *rctx); 417void r600_pipe_init_buffer_resource(struct r600_context *rctx, 418 struct r600_pipe_resource_state *rstate); 419void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 420 struct r600_resource *rbuffer, 421 unsigned offset, unsigned stride, 422 enum radeon_bo_usage usage); 423void r600_adjust_gprs(struct r600_context *rctx); 424boolean r600_is_format_supported(struct pipe_screen *screen, 425 enum pipe_format format, 426 enum pipe_texture_target target, 427 unsigned sample_count, 428 unsigned usage); 429 430/* r600_texture.c */ 431void r600_init_screen_texture_functions(struct pipe_screen *screen); 432void r600_init_surface_functions(struct r600_context *r600); 433uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 434 const unsigned char *swizzle_view, 435 uint32_t *word4_p, uint32_t *yuv_format_p); 436unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 437 unsigned level, unsigned layer); 438 439/* r600_translate.c */ 440void r600_translate_index_buffer(struct r600_context *r600, 441 struct pipe_index_buffer *ib, 442 unsigned count); 443 444/* r600_state_common.c */ 445void r600_init_atom(struct r600_atom *atom, 446 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 447 unsigned num_dw, enum r600_atom_flags flags); 448void r600_init_common_atoms(struct r600_context *rctx); 449unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 450void r600_texture_barrier(struct pipe_context *ctx); 451void r600_set_index_buffer(struct pipe_context *ctx, 452 const struct pipe_index_buffer *ib); 453void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 454 const struct pipe_vertex_buffer *buffers); 455void *r600_create_vertex_elements(struct pipe_context *ctx, 456 unsigned count, 457 const struct pipe_vertex_element *elements); 458void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 459void r600_bind_blend_state(struct pipe_context *ctx, void *state); 460void r600_set_blend_color(struct pipe_context *ctx, 461 const struct pipe_blend_color *state); 462void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 463void r600_bind_rs_state(struct pipe_context *ctx, void *state); 464void r600_delete_rs_state(struct pipe_context *ctx, void *state); 465void r600_sampler_view_destroy(struct pipe_context *ctx, 466 struct pipe_sampler_view *state); 467void r600_delete_state(struct pipe_context *ctx, void *state); 468void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 469void *r600_create_shader_state(struct pipe_context *ctx, 470 const struct pipe_shader_state *state); 471void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 472void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 473void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 474void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 475void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 476 struct pipe_resource *buffer); 477struct pipe_stream_output_target * 478r600_create_so_target(struct pipe_context *ctx, 479 struct pipe_resource *buffer, 480 unsigned buffer_offset, 481 unsigned buffer_size); 482void r600_so_target_destroy(struct pipe_context *ctx, 483 struct pipe_stream_output_target *target); 484void r600_set_so_targets(struct pipe_context *ctx, 485 unsigned num_targets, 486 struct pipe_stream_output_target **targets, 487 unsigned append_bitmask); 488void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 489 const struct pipe_stencil_ref *state); 490void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 491uint32_t r600_translate_stencil_op(int s_op); 492uint32_t r600_translate_fill(uint32_t func); 493unsigned r600_tex_wrap(unsigned wrap); 494unsigned r600_tex_filter(unsigned filter); 495unsigned r600_tex_mipfilter(unsigned filter); 496unsigned r600_tex_compare(unsigned compare); 497 498/* 499 * Helpers for building command buffers 500 */ 501 502#define PKT3_SET_CONFIG_REG 0x68 503#define PKT3_SET_CONTEXT_REG 0x69 504#define PKT3_SET_CTL_CONST 0x6F 505 506#define R600_CONFIG_REG_OFFSET 0x08000 507#define R600_CONTEXT_REG_OFFSET 0x28000 508#define R600_CTL_CONST_OFFSET 0x3CFF0 509 510#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 511#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 512#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 513#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 514#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 515 516static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 517{ 518 cb->buf[cb->atom.num_dw++] = value; 519} 520 521static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 522{ 523 assert(reg < R600_CONTEXT_REG_OFFSET); 524 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 525 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 526 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 527} 528 529static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 530{ 531 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 532 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 533 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 534 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 535} 536 537static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 538{ 539 assert(reg >= R600_CTL_CONST_OFFSET); 540 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 541 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 542 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 543} 544 545static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 546{ 547 r600_store_config_reg_seq(cb, reg, 1); 548 r600_store_value(cb, value); 549} 550 551static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 552{ 553 r600_store_context_reg_seq(cb, reg, 1); 554 r600_store_value(cb, value); 555} 556 557static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 558{ 559 r600_store_ctl_const_seq(cb, reg, 1); 560 r600_store_value(cb, value); 561} 562 563void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 564void r600_release_command_buffer(struct r600_command_buffer *cb); 565 566/* 567 * Helpers for emitting state into a command stream directly. 568 */ 569 570static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 571{ 572 cs->buf[cs->cdw++] = value; 573} 574 575static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 576{ 577 assert(reg < R600_CONTEXT_REG_OFFSET); 578 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 579 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 580 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 581} 582 583static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 584{ 585 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 586 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 587 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 588 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 589} 590 591static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 592{ 593 assert(reg >= R600_CTL_CONST_OFFSET); 594 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 595 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 596 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 597} 598 599static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 600{ 601 r600_write_config_reg_seq(cs, reg, 1); 602 r600_write_value(cs, value); 603} 604 605static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 606{ 607 r600_write_context_reg_seq(cs, reg, 1); 608 r600_write_value(cs, value); 609} 610 611static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 612{ 613 r600_write_ctl_const_seq(cs, reg, 1); 614 r600_write_value(cs, value); 615} 616 617/* 618 * common helpers 619 */ 620static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 621{ 622 return value * (1 << frac_bits); 623} 624#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 625 626static inline unsigned r600_tex_aniso_filter(unsigned filter) 627{ 628 if (filter <= 1) return 0; 629 if (filter <= 2) return 1; 630 if (filter <= 4) return 2; 631 if (filter <= 8) return 3; 632 /* else */ return 4; 633} 634 635/* 12.4 fixed-point */ 636static INLINE unsigned r600_pack_float_12p4(float x) 637{ 638 return x <= 0 ? 0 : 639 x >= 4096 ? 0xffff : x * 16; 640} 641 642#endif 643