brw_fs_visitor.cpp revision 01fa9addf447120e994415ad8fc8246ac234ec27
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "../glsl/glsl_types.h" 50#include "../glsl/ir_optimization.h" 51#include "../glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || 146 (this->result.file == GRF && 147 this->result.reg != 0)); 148 this->result.reg_offset += index->value.i[0] * element_size; 149 } else { 150 assert(!"FINISHME: non-constant array element"); 151 } 152} 153 154/* Instruction selection: Produce a MOV.sat instead of 155 * MIN(MAX(val, 0), 1) when possible. 156 */ 157bool 158fs_visitor::try_emit_saturate(ir_expression *ir) 159{ 160 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 161 162 if (!sat_val) 163 return false; 164 165 this->result = reg_undef; 166 sat_val->accept(this); 167 fs_reg src = this->result; 168 169 this->result = fs_reg(this, ir->type); 170 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 171 inst->saturate = true; 172 173 return true; 174} 175 176void 177fs_visitor::visit(ir_expression *ir) 178{ 179 unsigned int operand; 180 fs_reg op[2], temp; 181 fs_inst *inst; 182 183 assert(ir->get_num_operands() <= 2); 184 185 if (try_emit_saturate(ir)) 186 return; 187 188 /* This is where our caller would like us to put the result, if possible. */ 189 fs_reg saved_result_storage = this->result; 190 191 for (operand = 0; operand < ir->get_num_operands(); operand++) { 192 this->result = reg_undef; 193 ir->operands[operand]->accept(this); 194 if (this->result.file == BAD_FILE) { 195 ir_print_visitor v; 196 fail("Failed to get tree for expression operand:\n"); 197 ir->operands[operand]->accept(&v); 198 } 199 op[operand] = this->result; 200 201 /* Matrix expression operands should have been broken down to vector 202 * operations already. 203 */ 204 assert(!ir->operands[operand]->type->is_matrix()); 205 /* And then those vector operands should have been broken down to scalar. 206 */ 207 assert(!ir->operands[operand]->type->is_vector()); 208 } 209 210 /* Inherit storage from our parent if possible, and otherwise we 211 * alloc a temporary. 212 */ 213 if (saved_result_storage.file == BAD_FILE) { 214 this->result = fs_reg(this, ir->type); 215 } else { 216 this->result = saved_result_storage; 217 } 218 219 switch (ir->operation) { 220 case ir_unop_logic_not: 221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 222 * ones complement of the whole register, not just bit 0. 223 */ 224 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 225 break; 226 case ir_unop_neg: 227 op[0].negate = !op[0].negate; 228 this->result = op[0]; 229 break; 230 case ir_unop_abs: 231 op[0].abs = true; 232 op[0].negate = false; 233 this->result = op[0]; 234 break; 235 case ir_unop_sign: 236 temp = fs_reg(this, ir->type); 237 238 /* Unalias the destination. (imagine a = sign(a)) */ 239 this->result = fs_reg(this, ir->type); 240 241 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 242 243 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 244 inst->conditional_mod = BRW_CONDITIONAL_G; 245 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 246 inst->predicated = true; 247 248 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 249 inst->conditional_mod = BRW_CONDITIONAL_L; 250 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 251 inst->predicated = true; 252 253 break; 254 case ir_unop_rcp: 255 emit_math(FS_OPCODE_RCP, this->result, op[0]); 256 break; 257 258 case ir_unop_exp2: 259 emit_math(FS_OPCODE_EXP2, this->result, op[0]); 260 break; 261 case ir_unop_log2: 262 emit_math(FS_OPCODE_LOG2, this->result, op[0]); 263 break; 264 case ir_unop_exp: 265 case ir_unop_log: 266 assert(!"not reached: should be handled by ir_explog_to_explog2"); 267 break; 268 case ir_unop_sin: 269 case ir_unop_sin_reduced: 270 emit_math(FS_OPCODE_SIN, this->result, op[0]); 271 break; 272 case ir_unop_cos: 273 case ir_unop_cos_reduced: 274 emit_math(FS_OPCODE_COS, this->result, op[0]); 275 break; 276 277 case ir_unop_dFdx: 278 emit(FS_OPCODE_DDX, this->result, op[0]); 279 break; 280 case ir_unop_dFdy: 281 emit(FS_OPCODE_DDY, this->result, op[0]); 282 break; 283 284 case ir_binop_add: 285 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 286 break; 287 case ir_binop_sub: 288 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 289 break; 290 291 case ir_binop_mul: 292 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 293 break; 294 case ir_binop_div: 295 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 296 break; 297 case ir_binop_mod: 298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 299 break; 300 301 case ir_binop_less: 302 case ir_binop_greater: 303 case ir_binop_lequal: 304 case ir_binop_gequal: 305 case ir_binop_equal: 306 case ir_binop_all_equal: 307 case ir_binop_nequal: 308 case ir_binop_any_nequal: 309 temp = this->result; 310 /* original gen4 does implicit conversion before comparison. */ 311 if (intel->gen < 5) 312 temp.type = op[0].type; 313 314 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 315 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 316 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 317 break; 318 319 case ir_binop_logic_xor: 320 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 321 break; 322 323 case ir_binop_logic_or: 324 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 325 break; 326 327 case ir_binop_logic_and: 328 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 329 break; 330 331 case ir_binop_dot: 332 case ir_unop_any: 333 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 334 break; 335 336 case ir_unop_noise: 337 assert(!"not reached: should be handled by lower_noise"); 338 break; 339 340 case ir_quadop_vector: 341 assert(!"not reached: should be handled by lower_quadop_vector"); 342 break; 343 344 case ir_unop_sqrt: 345 emit_math(FS_OPCODE_SQRT, this->result, op[0]); 346 break; 347 348 case ir_unop_rsq: 349 emit_math(FS_OPCODE_RSQ, this->result, op[0]); 350 break; 351 352 case ir_unop_i2f: 353 case ir_unop_b2f: 354 case ir_unop_b2i: 355 case ir_unop_f2i: 356 emit(BRW_OPCODE_MOV, this->result, op[0]); 357 break; 358 case ir_unop_f2b: 359 case ir_unop_i2b: 360 temp = this->result; 361 /* original gen4 does implicit conversion before comparison. */ 362 if (intel->gen < 5) 363 temp.type = op[0].type; 364 365 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 366 inst->conditional_mod = BRW_CONDITIONAL_NZ; 367 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 368 break; 369 370 case ir_unop_trunc: 371 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 372 break; 373 case ir_unop_ceil: 374 op[0].negate = !op[0].negate; 375 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 376 this->result.negate = true; 377 break; 378 case ir_unop_floor: 379 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 380 break; 381 case ir_unop_fract: 382 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 383 break; 384 case ir_unop_round_even: 385 emit(BRW_OPCODE_RNDE, this->result, op[0]); 386 break; 387 388 case ir_binop_min: 389 if (intel->gen >= 6) { 390 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 391 inst->conditional_mod = BRW_CONDITIONAL_L; 392 } else { 393 /* Unalias the destination */ 394 this->result = fs_reg(this, ir->type); 395 396 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 397 inst->conditional_mod = BRW_CONDITIONAL_L; 398 399 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 400 inst->predicated = true; 401 } 402 break; 403 case ir_binop_max: 404 if (intel->gen >= 6) { 405 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 406 inst->conditional_mod = BRW_CONDITIONAL_GE; 407 } else { 408 /* Unalias the destination */ 409 this->result = fs_reg(this, ir->type); 410 411 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 412 inst->conditional_mod = BRW_CONDITIONAL_G; 413 414 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 415 inst->predicated = true; 416 } 417 break; 418 419 case ir_binop_pow: 420 emit_math(FS_OPCODE_POW, this->result, op[0], op[1]); 421 break; 422 423 case ir_unop_bit_not: 424 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 425 break; 426 case ir_binop_bit_and: 427 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 428 break; 429 case ir_binop_bit_xor: 430 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 431 break; 432 case ir_binop_bit_or: 433 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 434 break; 435 436 case ir_unop_u2f: 437 case ir_binop_lshift: 438 case ir_binop_rshift: 439 assert(!"GLSL 1.30 features unsupported"); 440 break; 441 } 442} 443 444void 445fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 446 const glsl_type *type, bool predicated) 447{ 448 switch (type->base_type) { 449 case GLSL_TYPE_FLOAT: 450 case GLSL_TYPE_UINT: 451 case GLSL_TYPE_INT: 452 case GLSL_TYPE_BOOL: 453 for (unsigned int i = 0; i < type->components(); i++) { 454 l.type = brw_type_for_base_type(type); 455 r.type = brw_type_for_base_type(type); 456 457 if (predicated || !l.equals(&r)) { 458 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 459 inst->predicated = predicated; 460 } 461 462 l.reg_offset++; 463 r.reg_offset++; 464 } 465 break; 466 case GLSL_TYPE_ARRAY: 467 for (unsigned int i = 0; i < type->length; i++) { 468 emit_assignment_writes(l, r, type->fields.array, predicated); 469 } 470 break; 471 472 case GLSL_TYPE_STRUCT: 473 for (unsigned int i = 0; i < type->length; i++) { 474 emit_assignment_writes(l, r, type->fields.structure[i].type, 475 predicated); 476 } 477 break; 478 479 case GLSL_TYPE_SAMPLER: 480 break; 481 482 default: 483 assert(!"not reached"); 484 break; 485 } 486} 487 488void 489fs_visitor::visit(ir_assignment *ir) 490{ 491 struct fs_reg l, r; 492 fs_inst *inst; 493 494 /* FINISHME: arrays on the lhs */ 495 this->result = reg_undef; 496 ir->lhs->accept(this); 497 l = this->result; 498 499 /* If we're doing a direct assignment, an RHS expression could 500 * drop its result right into our destination. Otherwise, tell it 501 * not to. 502 */ 503 if (ir->condition || 504 !(ir->lhs->type->is_scalar() || 505 (ir->lhs->type->is_vector() && 506 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) { 507 this->result = reg_undef; 508 } 509 510 ir->rhs->accept(this); 511 r = this->result; 512 513 assert(l.file != BAD_FILE); 514 assert(r.file != BAD_FILE); 515 516 if (ir->condition) { 517 emit_bool_to_cond_code(ir->condition); 518 } 519 520 if (ir->lhs->type->is_scalar() || 521 ir->lhs->type->is_vector()) { 522 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 523 if (ir->write_mask & (1 << i)) { 524 if (ir->condition) { 525 inst = emit(BRW_OPCODE_MOV, l, r); 526 inst->predicated = true; 527 } else if (!l.equals(&r)) { 528 inst = emit(BRW_OPCODE_MOV, l, r); 529 } 530 531 r.reg_offset++; 532 } 533 l.reg_offset++; 534 } 535 } else { 536 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 537 } 538} 539 540fs_inst * 541fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 542 int sampler) 543{ 544 int mlen; 545 int base_mrf = 1; 546 bool simd16 = false; 547 fs_reg orig_dst; 548 549 /* g0 header. */ 550 mlen = 1; 551 552 if (ir->shadow_comparitor) { 553 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 554 fs_inst *inst = emit(BRW_OPCODE_MOV, 555 fs_reg(MRF, base_mrf + mlen + i), coordinate); 556 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 557 inst->saturate = true; 558 559 coordinate.reg_offset++; 560 } 561 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 562 mlen += 3; 563 564 if (ir->op == ir_tex) { 565 /* There's no plain shadow compare message, so we use shadow 566 * compare with a bias of 0.0. 567 */ 568 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 569 mlen++; 570 } else if (ir->op == ir_txb) { 571 this->result = reg_undef; 572 ir->lod_info.bias->accept(this); 573 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 574 mlen++; 575 } else { 576 assert(ir->op == ir_txl); 577 this->result = reg_undef; 578 ir->lod_info.lod->accept(this); 579 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 580 mlen++; 581 } 582 583 this->result = reg_undef; 584 ir->shadow_comparitor->accept(this); 585 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 586 mlen++; 587 } else if (ir->op == ir_tex) { 588 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 589 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 590 coordinate); 591 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 592 inst->saturate = true; 593 coordinate.reg_offset++; 594 } 595 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 596 mlen += 3; 597 } else if (ir->op == ir_txd) { 598 ir->lod_info.grad.dPdx->accept(this); 599 fs_reg dPdx = this->result; 600 601 ir->lod_info.grad.dPdy->accept(this); 602 fs_reg dPdy = this->result; 603 604 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 605 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 606 coordinate.reg_offset++; 607 } 608 /* the slots for u and v are always present, but r is optional */ 609 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 610 611 /* P = u, v, r 612 * dPdx = dudx, dvdx, drdx 613 * dPdy = dudy, dvdy, drdy 614 * 615 * 2-arg: dudx dvdx dudy dvdy 616 * dPdx.x dPdx.y dPdy.x dPdy.y 617 * m4 m5 m6 m7 618 * 619 * 3-arg: dudx dvdx drdx dudy dvdy drdy 620 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 621 * m5 m6 m7 m8 m9 m10 622 */ 623 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 624 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 625 dPdx.reg_offset++; 626 mlen++; 627 } 628 629 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 630 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 631 dPdy.reg_offset++; 632 mlen++; 633 } 634 } else { 635 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 636 * instructions. We'll need to do SIMD16 here. 637 */ 638 assert(ir->op == ir_txb || ir->op == ir_txl); 639 640 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 641 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 642 base_mrf + mlen + i * 2), 643 coordinate); 644 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 645 inst->saturate = true; 646 coordinate.reg_offset++; 647 } 648 649 /* lod/bias appears after u/v/r. */ 650 mlen += 6; 651 652 if (ir->op == ir_txb) { 653 this->result = reg_undef; 654 ir->lod_info.bias->accept(this); 655 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 656 mlen++; 657 } else { 658 this->result = reg_undef; 659 ir->lod_info.lod->accept(this); 660 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 661 mlen++; 662 } 663 664 /* The unused upper half. */ 665 mlen++; 666 667 /* Now, since we're doing simd16, the return is 2 interleaved 668 * vec4s where the odd-indexed ones are junk. We'll need to move 669 * this weirdness around to the expected layout. 670 */ 671 simd16 = true; 672 orig_dst = dst; 673 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 674 2)); 675 dst.type = BRW_REGISTER_TYPE_F; 676 } 677 678 fs_inst *inst = NULL; 679 switch (ir->op) { 680 case ir_tex: 681 inst = emit(FS_OPCODE_TEX, dst); 682 break; 683 case ir_txb: 684 inst = emit(FS_OPCODE_TXB, dst); 685 break; 686 case ir_txl: 687 inst = emit(FS_OPCODE_TXL, dst); 688 break; 689 case ir_txd: 690 inst = emit(FS_OPCODE_TXD, dst); 691 break; 692 case ir_txf: 693 assert(!"GLSL 1.30 features unsupported"); 694 break; 695 } 696 inst->base_mrf = base_mrf; 697 inst->mlen = mlen; 698 inst->header_present = true; 699 700 if (simd16) { 701 for (int i = 0; i < 4; i++) { 702 emit(BRW_OPCODE_MOV, orig_dst, dst); 703 orig_dst.reg_offset++; 704 dst.reg_offset += 2; 705 } 706 } 707 708 return inst; 709} 710 711/* gen5's sampler has slots for u, v, r, array index, then optional 712 * parameters like shadow comparitor or LOD bias. If optional 713 * parameters aren't present, those base slots are optional and don't 714 * need to be included in the message. 715 * 716 * We don't fill in the unnecessary slots regardless, which may look 717 * surprising in the disassembly. 718 */ 719fs_inst * 720fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 721 int sampler) 722{ 723 int mlen = 0; 724 int base_mrf = 2; 725 int reg_width = c->dispatch_width / 8; 726 bool header_present = false; 727 728 if (ir->offset) { 729 /* The offsets set up by the ir_texture visitor are in the 730 * m1 header, so we can't go headerless. 731 */ 732 header_present = true; 733 mlen++; 734 base_mrf--; 735 } 736 737 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 738 fs_inst *inst = emit(BRW_OPCODE_MOV, 739 fs_reg(MRF, base_mrf + mlen + i * reg_width), 740 coordinate); 741 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 742 inst->saturate = true; 743 coordinate.reg_offset++; 744 } 745 mlen += ir->coordinate->type->vector_elements * reg_width; 746 747 if (ir->shadow_comparitor) { 748 mlen = MAX2(mlen, header_present + 4 * reg_width); 749 750 this->result = reg_undef; 751 ir->shadow_comparitor->accept(this); 752 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 753 mlen += reg_width; 754 } 755 756 fs_inst *inst = NULL; 757 switch (ir->op) { 758 case ir_tex: 759 inst = emit(FS_OPCODE_TEX, dst); 760 break; 761 case ir_txb: 762 this->result = reg_undef; 763 ir->lod_info.bias->accept(this); 764 mlen = MAX2(mlen, header_present + 4 * reg_width); 765 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 766 mlen += reg_width; 767 768 inst = emit(FS_OPCODE_TXB, dst); 769 770 break; 771 case ir_txl: 772 this->result = reg_undef; 773 ir->lod_info.lod->accept(this); 774 mlen = MAX2(mlen, header_present + 4 * reg_width); 775 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 776 mlen += reg_width; 777 778 inst = emit(FS_OPCODE_TXL, dst); 779 break; 780 case ir_txd: { 781 ir->lod_info.grad.dPdx->accept(this); 782 fs_reg dPdx = this->result; 783 784 ir->lod_info.grad.dPdy->accept(this); 785 fs_reg dPdy = this->result; 786 787 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 788 789 /** 790 * P = u, v, r 791 * dPdx = dudx, dvdx, drdx 792 * dPdy = dudy, dvdy, drdy 793 * 794 * Load up these values: 795 * - dudx dudy dvdx dvdy drdx drdy 796 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 797 */ 798 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 799 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 800 dPdx.reg_offset++; 801 mlen += reg_width; 802 803 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 804 dPdy.reg_offset++; 805 mlen += reg_width; 806 } 807 808 inst = emit(FS_OPCODE_TXD, dst); 809 break; 810 } 811 case ir_txf: 812 assert(!"GLSL 1.30 features unsupported"); 813 break; 814 } 815 inst->base_mrf = base_mrf; 816 inst->mlen = mlen; 817 inst->header_present = header_present; 818 819 if (mlen > 11) { 820 fail("Message length >11 disallowed by hardware\n"); 821 } 822 823 return inst; 824} 825 826fs_inst * 827fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 828 int sampler) 829{ 830 int mlen = 0; 831 int base_mrf = 2; 832 int reg_width = c->dispatch_width / 8; 833 bool header_present = false; 834 835 if (ir->offset) { 836 /* The offsets set up by the ir_texture visitor are in the 837 * m1 header, so we can't go headerless. 838 */ 839 header_present = true; 840 mlen++; 841 base_mrf--; 842 } 843 844 if (ir->shadow_comparitor) { 845 ir->shadow_comparitor->accept(this); 846 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 847 mlen += reg_width; 848 } 849 850 /* Set up the LOD info */ 851 switch (ir->op) { 852 case ir_tex: 853 break; 854 case ir_txb: 855 ir->lod_info.bias->accept(this); 856 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 857 mlen += reg_width; 858 break; 859 case ir_txl: 860 ir->lod_info.lod->accept(this); 861 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 862 mlen += reg_width; 863 break; 864 case ir_txd: { 865 if (c->dispatch_width == 16) 866 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 867 868 ir->lod_info.grad.dPdx->accept(this); 869 fs_reg dPdx = this->result; 870 871 ir->lod_info.grad.dPdy->accept(this); 872 fs_reg dPdy = this->result; 873 874 /* Load dPdx and the coordinate together: 875 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 876 */ 877 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 878 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 879 coordinate); 880 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 881 inst->saturate = true; 882 coordinate.reg_offset++; 883 mlen += reg_width; 884 885 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 886 dPdx.reg_offset++; 887 mlen += reg_width; 888 889 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 890 dPdy.reg_offset++; 891 mlen += reg_width; 892 } 893 break; 894 } 895 case ir_txf: 896 assert(!"GLSL 1.30 features unsupported"); 897 break; 898 } 899 900 /* Set up the coordinate (except for TXD where it was done earlier) */ 901 if (ir->op != ir_txd) { 902 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 903 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 904 coordinate); 905 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 906 inst->saturate = true; 907 coordinate.reg_offset++; 908 mlen += reg_width; 909 } 910 } 911 912 /* Generate the SEND */ 913 fs_inst *inst = NULL; 914 switch (ir->op) { 915 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 916 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 917 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 918 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 919 case ir_txf: assert(!"TXF unsupported."); 920 } 921 inst->base_mrf = base_mrf; 922 inst->mlen = mlen; 923 inst->header_present = header_present; 924 925 if (mlen > 11) { 926 fail("Message length >11 disallowed by hardware\n"); 927 } 928 929 return inst; 930} 931 932void 933fs_visitor::visit(ir_texture *ir) 934{ 935 fs_inst *inst = NULL; 936 937 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 938 sampler = fp->Base.SamplerUnits[sampler]; 939 940 this->result = reg_undef; 941 ir->coordinate->accept(this); 942 fs_reg coordinate = this->result; 943 944 if (ir->offset != NULL) { 945 ir_constant *offset = ir->offset->as_constant(); 946 assert(offset != NULL); 947 948 signed char offsets[3]; 949 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 950 offsets[i] = (signed char) offset->value.i[i]; 951 952 /* Combine all three offsets into a single unsigned dword: 953 * 954 * bits 11:8 - U Offset (X component) 955 * bits 7:4 - V Offset (Y component) 956 * bits 3:0 - R Offset (Z component) 957 */ 958 unsigned offset_bits = 0; 959 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 960 const unsigned shift = 4 * (2 - i); 961 offset_bits |= (offsets[i] << shift) & (0xF << shift); 962 } 963 964 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 965 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 966 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 967 968 /* Then set the offset bits in DWord 2 of the message header. */ 969 emit(BRW_OPCODE_MOV, 970 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 971 BRW_REGISTER_TYPE_UD)), 972 fs_reg(brw_imm_uw(offset_bits))); 973 } 974 975 /* Should be lowered by do_lower_texture_projection */ 976 assert(!ir->projector); 977 978 /* The 965 requires the EU to do the normalization of GL rectangle 979 * texture coordinates. We use the program parameter state 980 * tracking to get the scaling factor. 981 */ 982 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 983 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 984 int tokens[STATE_LENGTH] = { 985 STATE_INTERNAL, 986 STATE_TEXRECT_SCALE, 987 sampler, 988 0, 989 0 990 }; 991 992 if (c->dispatch_width == 16) { 993 fail("rectangle scale uniform setup not supported on 16-wide\n"); 994 this->result = fs_reg(this, ir->type); 995 return; 996 } 997 998 c->prog_data.param_convert[c->prog_data.nr_params] = 999 PARAM_NO_CONVERT; 1000 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1001 PARAM_NO_CONVERT; 1002 1003 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1004 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1005 GLuint index = _mesa_add_state_reference(params, 1006 (gl_state_index *)tokens); 1007 1008 this->param_index[c->prog_data.nr_params] = index; 1009 this->param_offset[c->prog_data.nr_params] = 0; 1010 c->prog_data.nr_params++; 1011 this->param_index[c->prog_data.nr_params] = index; 1012 this->param_offset[c->prog_data.nr_params] = 1; 1013 c->prog_data.nr_params++; 1014 1015 fs_reg dst = fs_reg(this, ir->coordinate->type); 1016 fs_reg src = coordinate; 1017 coordinate = dst; 1018 1019 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1020 dst.reg_offset++; 1021 src.reg_offset++; 1022 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1023 } 1024 1025 /* Writemasking doesn't eliminate channels on SIMD8 texture 1026 * samples, so don't worry about them. 1027 */ 1028 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 1029 1030 if (intel->gen >= 7) { 1031 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1032 } else if (intel->gen >= 5) { 1033 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1034 } else { 1035 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1036 } 1037 1038 /* If there's an offset, we already set up m1. To avoid the implied move, 1039 * use the null register. Otherwise, we want an implied move from g0. 1040 */ 1041 if (ir->offset != NULL || !inst->header_present) 1042 inst->src[0] = reg_undef; 1043 else 1044 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1045 1046 inst->sampler = sampler; 1047 1048 if (ir->shadow_comparitor) 1049 inst->shadow_compare = true; 1050 1051 swizzle_result(ir, dst, sampler); 1052} 1053 1054/** 1055 * Swizzle the result of a texture result. This is necessary for 1056 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1057 */ 1058void 1059fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1060{ 1061 this->result = orig_val; 1062 1063 if (ir->type == glsl_type::float_type) { 1064 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1065 assert(ir->sampler->type->sampler_shadow); 1066 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1067 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1068 1069 for (int i = 0; i < 4; i++) { 1070 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1071 fs_reg l = swizzled_result; 1072 l.reg_offset += i; 1073 1074 if (swiz == SWIZZLE_ZERO) { 1075 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1076 } else if (swiz == SWIZZLE_ONE) { 1077 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1078 } else { 1079 fs_reg r = orig_val; 1080 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1081 emit(BRW_OPCODE_MOV, l, r); 1082 } 1083 } 1084 this->result = swizzled_result; 1085 } 1086} 1087 1088void 1089fs_visitor::visit(ir_swizzle *ir) 1090{ 1091 this->result = reg_undef; 1092 ir->val->accept(this); 1093 fs_reg val = this->result; 1094 1095 if (ir->type->vector_elements == 1) { 1096 this->result.reg_offset += ir->mask.x; 1097 return; 1098 } 1099 1100 fs_reg result = fs_reg(this, ir->type); 1101 this->result = result; 1102 1103 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1104 fs_reg channel = val; 1105 int swiz = 0; 1106 1107 switch (i) { 1108 case 0: 1109 swiz = ir->mask.x; 1110 break; 1111 case 1: 1112 swiz = ir->mask.y; 1113 break; 1114 case 2: 1115 swiz = ir->mask.z; 1116 break; 1117 case 3: 1118 swiz = ir->mask.w; 1119 break; 1120 } 1121 1122 channel.reg_offset += swiz; 1123 emit(BRW_OPCODE_MOV, result, channel); 1124 result.reg_offset++; 1125 } 1126} 1127 1128void 1129fs_visitor::visit(ir_discard *ir) 1130{ 1131 assert(ir->condition == NULL); /* FINISHME */ 1132 1133 emit(FS_OPCODE_DISCARD); 1134 kill_emitted = true; 1135} 1136 1137void 1138fs_visitor::visit(ir_constant *ir) 1139{ 1140 /* Set this->result to reg at the bottom of the function because some code 1141 * paths will cause this visitor to be applied to other fields. This will 1142 * cause the value stored in this->result to be modified. 1143 * 1144 * Make reg constant so that it doesn't get accidentally modified along the 1145 * way. Yes, I actually had this problem. :( 1146 */ 1147 const fs_reg reg(this, ir->type); 1148 fs_reg dst_reg = reg; 1149 1150 if (ir->type->is_array()) { 1151 const unsigned size = type_size(ir->type->fields.array); 1152 1153 for (unsigned i = 0; i < ir->type->length; i++) { 1154 this->result = reg_undef; 1155 ir->array_elements[i]->accept(this); 1156 fs_reg src_reg = this->result; 1157 1158 dst_reg.type = src_reg.type; 1159 for (unsigned j = 0; j < size; j++) { 1160 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1161 src_reg.reg_offset++; 1162 dst_reg.reg_offset++; 1163 } 1164 } 1165 } else if (ir->type->is_record()) { 1166 foreach_list(node, &ir->components) { 1167 ir_instruction *const field = (ir_instruction *) node; 1168 const unsigned size = type_size(field->type); 1169 1170 this->result = reg_undef; 1171 field->accept(this); 1172 fs_reg src_reg = this->result; 1173 1174 dst_reg.type = src_reg.type; 1175 for (unsigned j = 0; j < size; j++) { 1176 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1177 src_reg.reg_offset++; 1178 dst_reg.reg_offset++; 1179 } 1180 } 1181 } else { 1182 const unsigned size = type_size(ir->type); 1183 1184 for (unsigned i = 0; i < size; i++) { 1185 switch (ir->type->base_type) { 1186 case GLSL_TYPE_FLOAT: 1187 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1188 break; 1189 case GLSL_TYPE_UINT: 1190 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1191 break; 1192 case GLSL_TYPE_INT: 1193 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1194 break; 1195 case GLSL_TYPE_BOOL: 1196 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1197 break; 1198 default: 1199 assert(!"Non-float/uint/int/bool constant"); 1200 } 1201 dst_reg.reg_offset++; 1202 } 1203 } 1204 1205 this->result = reg; 1206} 1207 1208void 1209fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1210{ 1211 ir_expression *expr = ir->as_expression(); 1212 1213 if (expr) { 1214 fs_reg op[2]; 1215 fs_inst *inst; 1216 1217 assert(expr->get_num_operands() <= 2); 1218 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1219 assert(expr->operands[i]->type->is_scalar()); 1220 1221 this->result = reg_undef; 1222 expr->operands[i]->accept(this); 1223 op[i] = this->result; 1224 } 1225 1226 switch (expr->operation) { 1227 case ir_unop_logic_not: 1228 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1229 inst->conditional_mod = BRW_CONDITIONAL_Z; 1230 break; 1231 1232 case ir_binop_logic_xor: 1233 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1234 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1235 break; 1236 1237 case ir_binop_logic_or: 1238 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1239 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1240 break; 1241 1242 case ir_binop_logic_and: 1243 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1244 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1245 break; 1246 1247 case ir_unop_f2b: 1248 if (intel->gen >= 6) { 1249 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1250 } else { 1251 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1252 } 1253 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1254 break; 1255 1256 case ir_unop_i2b: 1257 if (intel->gen >= 6) { 1258 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1259 } else { 1260 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1261 } 1262 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1263 break; 1264 1265 case ir_binop_greater: 1266 case ir_binop_gequal: 1267 case ir_binop_less: 1268 case ir_binop_lequal: 1269 case ir_binop_equal: 1270 case ir_binop_all_equal: 1271 case ir_binop_nequal: 1272 case ir_binop_any_nequal: 1273 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1274 inst->conditional_mod = 1275 brw_conditional_for_comparison(expr->operation); 1276 break; 1277 1278 default: 1279 assert(!"not reached"); 1280 fail("bad cond code\n"); 1281 break; 1282 } 1283 return; 1284 } 1285 1286 this->result = reg_undef; 1287 ir->accept(this); 1288 1289 if (intel->gen >= 6) { 1290 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1291 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1292 } else { 1293 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1294 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1295 } 1296} 1297 1298/** 1299 * Emit a gen6 IF statement with the comparison folded into the IF 1300 * instruction. 1301 */ 1302void 1303fs_visitor::emit_if_gen6(ir_if *ir) 1304{ 1305 ir_expression *expr = ir->condition->as_expression(); 1306 1307 if (expr) { 1308 fs_reg op[2]; 1309 fs_inst *inst; 1310 fs_reg temp; 1311 1312 assert(expr->get_num_operands() <= 2); 1313 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1314 assert(expr->operands[i]->type->is_scalar()); 1315 1316 this->result = reg_undef; 1317 expr->operands[i]->accept(this); 1318 op[i] = this->result; 1319 } 1320 1321 switch (expr->operation) { 1322 case ir_unop_logic_not: 1323 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1324 inst->conditional_mod = BRW_CONDITIONAL_Z; 1325 return; 1326 1327 case ir_binop_logic_xor: 1328 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1329 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1330 return; 1331 1332 case ir_binop_logic_or: 1333 temp = fs_reg(this, glsl_type::bool_type); 1334 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1335 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1336 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1337 return; 1338 1339 case ir_binop_logic_and: 1340 temp = fs_reg(this, glsl_type::bool_type); 1341 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1342 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1343 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1344 return; 1345 1346 case ir_unop_f2b: 1347 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1348 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1349 return; 1350 1351 case ir_unop_i2b: 1352 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1353 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1354 return; 1355 1356 case ir_binop_greater: 1357 case ir_binop_gequal: 1358 case ir_binop_less: 1359 case ir_binop_lequal: 1360 case ir_binop_equal: 1361 case ir_binop_all_equal: 1362 case ir_binop_nequal: 1363 case ir_binop_any_nequal: 1364 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1365 inst->conditional_mod = 1366 brw_conditional_for_comparison(expr->operation); 1367 return; 1368 default: 1369 assert(!"not reached"); 1370 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1371 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1372 fail("bad condition\n"); 1373 return; 1374 } 1375 return; 1376 } 1377 1378 this->result = reg_undef; 1379 ir->condition->accept(this); 1380 1381 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1382 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1383} 1384 1385void 1386fs_visitor::visit(ir_if *ir) 1387{ 1388 fs_inst *inst; 1389 1390 if (intel->gen != 6 && c->dispatch_width == 16) { 1391 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1392 } 1393 1394 /* Don't point the annotation at the if statement, because then it plus 1395 * the then and else blocks get printed. 1396 */ 1397 this->base_ir = ir->condition; 1398 1399 if (intel->gen == 6) { 1400 emit_if_gen6(ir); 1401 } else { 1402 emit_bool_to_cond_code(ir->condition); 1403 1404 inst = emit(BRW_OPCODE_IF); 1405 inst->predicated = true; 1406 } 1407 1408 foreach_iter(exec_list_iterator, iter, ir->then_instructions) { 1409 ir_instruction *ir = (ir_instruction *)iter.get(); 1410 this->base_ir = ir; 1411 this->result = reg_undef; 1412 ir->accept(this); 1413 } 1414 1415 if (!ir->else_instructions.is_empty()) { 1416 emit(BRW_OPCODE_ELSE); 1417 1418 foreach_iter(exec_list_iterator, iter, ir->else_instructions) { 1419 ir_instruction *ir = (ir_instruction *)iter.get(); 1420 this->base_ir = ir; 1421 this->result = reg_undef; 1422 ir->accept(this); 1423 } 1424 } 1425 1426 emit(BRW_OPCODE_ENDIF); 1427} 1428 1429void 1430fs_visitor::visit(ir_loop *ir) 1431{ 1432 fs_reg counter = reg_undef; 1433 1434 if (c->dispatch_width == 16) { 1435 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1436 } 1437 1438 if (ir->counter) { 1439 this->base_ir = ir->counter; 1440 ir->counter->accept(this); 1441 counter = *(variable_storage(ir->counter)); 1442 1443 if (ir->from) { 1444 this->result = counter; 1445 1446 this->base_ir = ir->from; 1447 this->result = counter; 1448 ir->from->accept(this); 1449 1450 if (!this->result.equals(&counter)) 1451 emit(BRW_OPCODE_MOV, counter, this->result); 1452 } 1453 } 1454 1455 emit(BRW_OPCODE_DO); 1456 1457 if (ir->to) { 1458 this->base_ir = ir->to; 1459 this->result = reg_undef; 1460 ir->to->accept(this); 1461 1462 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1463 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1464 1465 inst = emit(BRW_OPCODE_BREAK); 1466 inst->predicated = true; 1467 } 1468 1469 foreach_iter(exec_list_iterator, iter, ir->body_instructions) { 1470 ir_instruction *ir = (ir_instruction *)iter.get(); 1471 1472 this->base_ir = ir; 1473 this->result = reg_undef; 1474 ir->accept(this); 1475 } 1476 1477 if (ir->increment) { 1478 this->base_ir = ir->increment; 1479 this->result = reg_undef; 1480 ir->increment->accept(this); 1481 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1482 } 1483 1484 emit(BRW_OPCODE_WHILE); 1485} 1486 1487void 1488fs_visitor::visit(ir_loop_jump *ir) 1489{ 1490 switch (ir->mode) { 1491 case ir_loop_jump::jump_break: 1492 emit(BRW_OPCODE_BREAK); 1493 break; 1494 case ir_loop_jump::jump_continue: 1495 emit(BRW_OPCODE_CONTINUE); 1496 break; 1497 } 1498} 1499 1500void 1501fs_visitor::visit(ir_call *ir) 1502{ 1503 assert(!"FINISHME"); 1504} 1505 1506void 1507fs_visitor::visit(ir_return *ir) 1508{ 1509 assert(!"FINISHME"); 1510} 1511 1512void 1513fs_visitor::visit(ir_function *ir) 1514{ 1515 /* Ignore function bodies other than main() -- we shouldn't see calls to 1516 * them since they should all be inlined before we get to ir_to_mesa. 1517 */ 1518 if (strcmp(ir->name, "main") == 0) { 1519 const ir_function_signature *sig; 1520 exec_list empty; 1521 1522 sig = ir->matching_signature(&empty); 1523 1524 assert(sig); 1525 1526 foreach_iter(exec_list_iterator, iter, sig->body) { 1527 ir_instruction *ir = (ir_instruction *)iter.get(); 1528 this->base_ir = ir; 1529 this->result = reg_undef; 1530 ir->accept(this); 1531 } 1532 } 1533} 1534 1535void 1536fs_visitor::visit(ir_function_signature *ir) 1537{ 1538 assert(!"not reached"); 1539 (void)ir; 1540} 1541 1542fs_inst * 1543fs_visitor::emit(fs_inst inst) 1544{ 1545 fs_inst *list_inst = new(mem_ctx) fs_inst; 1546 *list_inst = inst; 1547 1548 if (force_uncompressed_stack > 0) 1549 list_inst->force_uncompressed = true; 1550 else if (force_sechalf_stack > 0) 1551 list_inst->force_sechalf = true; 1552 1553 list_inst->annotation = this->current_annotation; 1554 list_inst->ir = this->base_ir; 1555 1556 this->instructions.push_tail(list_inst); 1557 1558 return list_inst; 1559} 1560 1561/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1562void 1563fs_visitor::emit_dummy_fs() 1564{ 1565 /* Everyone's favorite color. */ 1566 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1567 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1568 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1569 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1570 1571 fs_inst *write; 1572 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1573 write->base_mrf = 0; 1574} 1575 1576/* The register location here is relative to the start of the URB 1577 * data. It will get adjusted to be a real location before 1578 * generate_code() time. 1579 */ 1580struct brw_reg 1581fs_visitor::interp_reg(int location, int channel) 1582{ 1583 int regnr = urb_setup[location] * 2 + channel / 2; 1584 int stride = (channel & 1) * 4; 1585 1586 assert(urb_setup[location] != -1); 1587 1588 return brw_vec1_grf(regnr, stride); 1589} 1590 1591/** Emits the interpolation for the varying inputs. */ 1592void 1593fs_visitor::emit_interpolation_setup_gen4() 1594{ 1595 this->current_annotation = "compute pixel centers"; 1596 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1597 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1598 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1599 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1600 1601 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1602 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1603 1604 this->current_annotation = "compute pixel deltas from v0"; 1605 if (brw->has_pln) { 1606 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1607 this->delta_y = this->delta_x; 1608 this->delta_y.reg_offset++; 1609 } else { 1610 this->delta_x = fs_reg(this, glsl_type::float_type); 1611 this->delta_y = fs_reg(this, glsl_type::float_type); 1612 } 1613 emit(BRW_OPCODE_ADD, this->delta_x, 1614 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1615 emit(BRW_OPCODE_ADD, this->delta_y, 1616 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1617 1618 this->current_annotation = "compute pos.w and 1/pos.w"; 1619 /* Compute wpos.w. It's always in our setup, since it's needed to 1620 * interpolate the other attributes. 1621 */ 1622 this->wpos_w = fs_reg(this, glsl_type::float_type); 1623 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1624 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1625 /* Compute the pixel 1/W value from wpos.w. */ 1626 this->pixel_w = fs_reg(this, glsl_type::float_type); 1627 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w); 1628 this->current_annotation = NULL; 1629} 1630 1631/** Emits the interpolation for the varying inputs. */ 1632void 1633fs_visitor::emit_interpolation_setup_gen6() 1634{ 1635 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1636 1637 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1638 this->current_annotation = "compute pixel centers"; 1639 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1640 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1641 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1642 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1643 emit(BRW_OPCODE_ADD, 1644 int_pixel_x, 1645 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1646 fs_reg(brw_imm_v(0x10101010))); 1647 emit(BRW_OPCODE_ADD, 1648 int_pixel_y, 1649 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1650 fs_reg(brw_imm_v(0x11001100))); 1651 1652 /* As of gen6, we can no longer mix float and int sources. We have 1653 * to turn the integer pixel centers into floats for their actual 1654 * use. 1655 */ 1656 this->pixel_x = fs_reg(this, glsl_type::float_type); 1657 this->pixel_y = fs_reg(this, glsl_type::float_type); 1658 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1659 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1660 1661 this->current_annotation = "compute pos.w"; 1662 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1663 this->wpos_w = fs_reg(this, glsl_type::float_type); 1664 emit_math(FS_OPCODE_RCP, this->wpos_w, this->pixel_w); 1665 1666 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1667 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1668 1669 this->current_annotation = NULL; 1670} 1671 1672void 1673fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1674{ 1675 int reg_width = c->dispatch_width / 8; 1676 1677 if (c->dispatch_width == 8 || intel->gen == 6) { 1678 /* SIMD8 write looks like: 1679 * m + 0: r0 1680 * m + 1: r1 1681 * m + 2: g0 1682 * m + 3: g1 1683 * 1684 * gen6 SIMD16 DP write looks like: 1685 * m + 0: r0 1686 * m + 1: r1 1687 * m + 2: g0 1688 * m + 3: g1 1689 * m + 4: b0 1690 * m + 5: b1 1691 * m + 6: a0 1692 * m + 7: a1 1693 */ 1694 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index * reg_width), 1695 color); 1696 } else { 1697 /* pre-gen6 SIMD16 single source DP write looks like: 1698 * m + 0: r0 1699 * m + 1: g0 1700 * m + 2: b0 1701 * m + 3: a0 1702 * m + 4: r1 1703 * m + 5: g1 1704 * m + 6: b1 1705 * m + 7: a1 1706 */ 1707 if (brw->has_compr4) { 1708 /* By setting the high bit of the MRF register number, we 1709 * indicate that we want COMPR4 mode - instead of doing the 1710 * usual destination + 1 for the second half we get 1711 * destination + 4. 1712 */ 1713 emit(BRW_OPCODE_MOV, 1714 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), color); 1715 } else { 1716 push_force_uncompressed(); 1717 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), color); 1718 pop_force_uncompressed(); 1719 1720 push_force_sechalf(); 1721 color.sechalf = true; 1722 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), color); 1723 pop_force_sechalf(); 1724 color.sechalf = false; 1725 } 1726 } 1727} 1728 1729void 1730fs_visitor::emit_fb_writes() 1731{ 1732 this->current_annotation = "FB write header"; 1733 GLboolean header_present = GL_TRUE; 1734 int nr = 0; 1735 int reg_width = c->dispatch_width / 8; 1736 1737 if (intel->gen >= 6 && 1738 !this->kill_emitted && 1739 c->key.nr_color_regions == 1) { 1740 header_present = false; 1741 } 1742 1743 if (header_present) { 1744 /* m0, m1 header */ 1745 nr += 2; 1746 } 1747 1748 if (c->aa_dest_stencil_reg) { 1749 push_force_uncompressed(); 1750 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1751 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1752 pop_force_uncompressed(); 1753 } 1754 1755 /* Reserve space for color. It'll be filled in per MRT below. */ 1756 int color_mrf = nr; 1757 nr += 4 * reg_width; 1758 1759 if (c->source_depth_to_render_target) { 1760 if (intel->gen == 6 && c->dispatch_width == 16) { 1761 /* For outputting oDepth on gen6, SIMD8 writes have to be 1762 * used. This would require 8-wide moves of each half to 1763 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1764 * Just bail on doing so for now. 1765 */ 1766 fail("Missing support for simd16 depth writes on gen6\n"); 1767 } 1768 1769 if (c->computes_depth) { 1770 /* Hand over gl_FragDepth. */ 1771 assert(this->frag_depth); 1772 fs_reg depth = *(variable_storage(this->frag_depth)); 1773 1774 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1775 } else { 1776 /* Pass through the payload depth. */ 1777 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1778 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1779 } 1780 nr += reg_width; 1781 } 1782 1783 if (c->dest_depth_reg) { 1784 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1785 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1786 nr += reg_width; 1787 } 1788 1789 fs_reg color = reg_undef; 1790 if (this->frag_color) 1791 color = *(variable_storage(this->frag_color)); 1792 else if (this->frag_data) { 1793 color = *(variable_storage(this->frag_data)); 1794 color.type = BRW_REGISTER_TYPE_F; 1795 } 1796 1797 for (int target = 0; target < c->key.nr_color_regions; target++) { 1798 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1799 "FB write target %d", 1800 target); 1801 if (this->frag_color || this->frag_data) { 1802 for (int i = 0; i < 4; i++) { 1803 emit_color_write(i, color_mrf, color); 1804 color.reg_offset++; 1805 } 1806 } 1807 1808 if (this->frag_color) 1809 color.reg_offset -= 4; 1810 1811 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1812 inst->target = target; 1813 inst->base_mrf = 0; 1814 inst->mlen = nr; 1815 if (target == c->key.nr_color_regions - 1) 1816 inst->eot = true; 1817 inst->header_present = header_present; 1818 } 1819 1820 if (c->key.nr_color_regions == 0) { 1821 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1822 /* If the alpha test is enabled but there's no color buffer, 1823 * we still need to send alpha out the pipeline to our null 1824 * renderbuffer. 1825 */ 1826 color.reg_offset += 3; 1827 emit_color_write(3, color_mrf, color); 1828 } 1829 1830 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1831 inst->base_mrf = 0; 1832 inst->mlen = nr; 1833 inst->eot = true; 1834 inst->header_present = header_present; 1835 } 1836 1837 this->current_annotation = NULL; 1838} 1839