brw_fs_visitor.cpp revision 0edf5d63d60100cc2b7467da78ce811c4824b760
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || this->result.file == GRF); 146 this->result.reg_offset += index->value.i[0] * element_size; 147 } else { 148 assert(!"FINISHME: non-constant array element"); 149 } 150} 151 152/* Instruction selection: Produce a MOV.sat instead of 153 * MIN(MAX(val, 0), 1) when possible. 154 */ 155bool 156fs_visitor::try_emit_saturate(ir_expression *ir) 157{ 158 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 159 160 if (!sat_val) 161 return false; 162 163 sat_val->accept(this); 164 fs_reg src = this->result; 165 166 this->result = fs_reg(this, ir->type); 167 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 168 inst->saturate = true; 169 170 return true; 171} 172 173void 174fs_visitor::visit(ir_expression *ir) 175{ 176 unsigned int operand; 177 fs_reg op[2], temp; 178 fs_inst *inst; 179 180 assert(ir->get_num_operands() <= 2); 181 182 if (try_emit_saturate(ir)) 183 return; 184 185 for (operand = 0; operand < ir->get_num_operands(); operand++) { 186 ir->operands[operand]->accept(this); 187 if (this->result.file == BAD_FILE) { 188 ir_print_visitor v; 189 fail("Failed to get tree for expression operand:\n"); 190 ir->operands[operand]->accept(&v); 191 } 192 op[operand] = this->result; 193 194 /* Matrix expression operands should have been broken down to vector 195 * operations already. 196 */ 197 assert(!ir->operands[operand]->type->is_matrix()); 198 /* And then those vector operands should have been broken down to scalar. 199 */ 200 assert(!ir->operands[operand]->type->is_vector()); 201 } 202 203 /* Storage for our result. If our result goes into an assignment, it will 204 * just get copy-propagated out, so no worries. 205 */ 206 this->result = fs_reg(this, ir->type); 207 208 switch (ir->operation) { 209 case ir_unop_logic_not: 210 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 211 * ones complement of the whole register, not just bit 0. 212 */ 213 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 214 break; 215 case ir_unop_neg: 216 op[0].negate = !op[0].negate; 217 this->result = op[0]; 218 break; 219 case ir_unop_abs: 220 op[0].abs = true; 221 op[0].negate = false; 222 this->result = op[0]; 223 break; 224 case ir_unop_sign: 225 temp = fs_reg(this, ir->type); 226 227 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 228 229 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 230 inst->conditional_mod = BRW_CONDITIONAL_G; 231 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 232 inst->predicated = true; 233 234 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 235 inst->conditional_mod = BRW_CONDITIONAL_L; 236 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 237 inst->predicated = true; 238 239 break; 240 case ir_unop_rcp: 241 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 242 break; 243 244 case ir_unop_exp2: 245 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 246 break; 247 case ir_unop_log2: 248 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 249 break; 250 case ir_unop_exp: 251 case ir_unop_log: 252 assert(!"not reached: should be handled by ir_explog_to_explog2"); 253 break; 254 case ir_unop_sin: 255 case ir_unop_sin_reduced: 256 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 257 break; 258 case ir_unop_cos: 259 case ir_unop_cos_reduced: 260 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 261 break; 262 263 case ir_unop_dFdx: 264 emit(FS_OPCODE_DDX, this->result, op[0]); 265 break; 266 case ir_unop_dFdy: 267 emit(FS_OPCODE_DDY, this->result, op[0]); 268 break; 269 270 case ir_binop_add: 271 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 272 break; 273 case ir_binop_sub: 274 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 275 break; 276 277 case ir_binop_mul: 278 if (ir->type->is_integer()) { 279 /* For integer multiplication, the MUL uses the low 16 bits 280 * of one of the operands (src0 on gen6, src1 on gen7). The 281 * MACH accumulates in the contribution of the upper 16 bits 282 * of that operand. 283 * 284 * FINISHME: Emit just the MUL if we know an operand is small 285 * enough. 286 */ 287 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 288 289 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 290 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 291 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 292 } else { 293 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 294 } 295 break; 296 case ir_binop_div: 297 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 298 break; 299 case ir_binop_mod: 300 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 301 break; 302 303 case ir_binop_less: 304 case ir_binop_greater: 305 case ir_binop_lequal: 306 case ir_binop_gequal: 307 case ir_binop_equal: 308 case ir_binop_all_equal: 309 case ir_binop_nequal: 310 case ir_binop_any_nequal: 311 temp = this->result; 312 /* original gen4 does implicit conversion before comparison. */ 313 if (intel->gen < 5) 314 temp.type = op[0].type; 315 316 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 317 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 318 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 319 break; 320 321 case ir_binop_logic_xor: 322 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 323 break; 324 325 case ir_binop_logic_or: 326 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 327 break; 328 329 case ir_binop_logic_and: 330 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 331 break; 332 333 case ir_binop_dot: 334 case ir_unop_any: 335 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 336 break; 337 338 case ir_unop_noise: 339 assert(!"not reached: should be handled by lower_noise"); 340 break; 341 342 case ir_quadop_vector: 343 assert(!"not reached: should be handled by lower_quadop_vector"); 344 break; 345 346 case ir_unop_sqrt: 347 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 348 break; 349 350 case ir_unop_rsq: 351 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 352 break; 353 354 case ir_unop_i2u: 355 op[0].type = BRW_REGISTER_TYPE_UD; 356 this->result = op[0]; 357 break; 358 case ir_unop_u2i: 359 op[0].type = BRW_REGISTER_TYPE_D; 360 this->result = op[0]; 361 break; 362 case ir_unop_i2f: 363 case ir_unop_u2f: 364 case ir_unop_b2f: 365 case ir_unop_b2i: 366 case ir_unop_f2i: 367 emit(BRW_OPCODE_MOV, this->result, op[0]); 368 break; 369 case ir_unop_f2b: 370 case ir_unop_i2b: 371 temp = this->result; 372 /* original gen4 does implicit conversion before comparison. */ 373 if (intel->gen < 5) 374 temp.type = op[0].type; 375 376 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 377 inst->conditional_mod = BRW_CONDITIONAL_NZ; 378 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 379 break; 380 381 case ir_unop_trunc: 382 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 383 break; 384 case ir_unop_ceil: 385 op[0].negate = !op[0].negate; 386 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 387 this->result.negate = true; 388 break; 389 case ir_unop_floor: 390 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 391 break; 392 case ir_unop_fract: 393 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 394 break; 395 case ir_unop_round_even: 396 emit(BRW_OPCODE_RNDE, this->result, op[0]); 397 break; 398 399 case ir_binop_min: 400 if (intel->gen >= 6) { 401 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 402 inst->conditional_mod = BRW_CONDITIONAL_L; 403 } else { 404 /* Unalias the destination */ 405 this->result = fs_reg(this, ir->type); 406 407 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 408 inst->conditional_mod = BRW_CONDITIONAL_L; 409 410 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 411 inst->predicated = true; 412 } 413 break; 414 case ir_binop_max: 415 if (intel->gen >= 6) { 416 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 417 inst->conditional_mod = BRW_CONDITIONAL_GE; 418 } else { 419 /* Unalias the destination */ 420 this->result = fs_reg(this, ir->type); 421 422 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 423 inst->conditional_mod = BRW_CONDITIONAL_G; 424 425 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 426 inst->predicated = true; 427 } 428 break; 429 430 case ir_binop_pow: 431 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 432 break; 433 434 case ir_unop_bit_not: 435 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 436 break; 437 case ir_binop_bit_and: 438 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 439 break; 440 case ir_binop_bit_xor: 441 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 442 break; 443 case ir_binop_bit_or: 444 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 445 break; 446 447 case ir_binop_lshift: 448 case ir_binop_rshift: 449 assert(!"GLSL 1.30 features unsupported"); 450 break; 451 } 452} 453 454void 455fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 456 const glsl_type *type, bool predicated) 457{ 458 switch (type->base_type) { 459 case GLSL_TYPE_FLOAT: 460 case GLSL_TYPE_UINT: 461 case GLSL_TYPE_INT: 462 case GLSL_TYPE_BOOL: 463 for (unsigned int i = 0; i < type->components(); i++) { 464 l.type = brw_type_for_base_type(type); 465 r.type = brw_type_for_base_type(type); 466 467 if (predicated || !l.equals(&r)) { 468 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 469 inst->predicated = predicated; 470 } 471 472 l.reg_offset++; 473 r.reg_offset++; 474 } 475 break; 476 case GLSL_TYPE_ARRAY: 477 for (unsigned int i = 0; i < type->length; i++) { 478 emit_assignment_writes(l, r, type->fields.array, predicated); 479 } 480 break; 481 482 case GLSL_TYPE_STRUCT: 483 for (unsigned int i = 0; i < type->length; i++) { 484 emit_assignment_writes(l, r, type->fields.structure[i].type, 485 predicated); 486 } 487 break; 488 489 case GLSL_TYPE_SAMPLER: 490 break; 491 492 default: 493 assert(!"not reached"); 494 break; 495 } 496} 497 498/* If the RHS processing resulted in an instruction generating a 499 * temporary value, and it would be easy to rewrite the instruction to 500 * generate its result right into the LHS instead, do so. This ends 501 * up reliably removing instructions where it can be tricky to do so 502 * later without real UD chain information. 503 */ 504bool 505fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 506 fs_reg dst, 507 fs_reg src, 508 fs_inst *pre_rhs_inst, 509 fs_inst *last_rhs_inst) 510{ 511 if (pre_rhs_inst == last_rhs_inst) 512 return false; /* No instructions generated to work with. */ 513 514 /* Only attempt if we're doing a direct assignment. */ 515 if (ir->condition || 516 !(ir->lhs->type->is_scalar() || 517 (ir->lhs->type->is_vector() && 518 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 519 return false; 520 521 /* Make sure the last instruction generated our source reg. */ 522 if (last_rhs_inst->predicated || 523 last_rhs_inst->force_uncompressed || 524 last_rhs_inst->force_sechalf || 525 !src.equals(&last_rhs_inst->dst)) 526 return false; 527 528 /* Success! Rewrite the instruction. */ 529 last_rhs_inst->dst = dst; 530 531 return true; 532} 533 534void 535fs_visitor::visit(ir_assignment *ir) 536{ 537 fs_reg l, r; 538 fs_inst *inst; 539 540 /* FINISHME: arrays on the lhs */ 541 ir->lhs->accept(this); 542 l = this->result; 543 544 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 545 546 ir->rhs->accept(this); 547 r = this->result; 548 549 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 550 551 assert(l.file != BAD_FILE); 552 assert(r.file != BAD_FILE); 553 554 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 555 return; 556 557 if (ir->condition) { 558 emit_bool_to_cond_code(ir->condition); 559 } 560 561 if (ir->lhs->type->is_scalar() || 562 ir->lhs->type->is_vector()) { 563 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 564 if (ir->write_mask & (1 << i)) { 565 inst = emit(BRW_OPCODE_MOV, l, r); 566 if (ir->condition) 567 inst->predicated = true; 568 r.reg_offset++; 569 } 570 l.reg_offset++; 571 } 572 } else { 573 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 574 } 575} 576 577fs_inst * 578fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 579 int sampler) 580{ 581 int mlen; 582 int base_mrf = 1; 583 bool simd16 = false; 584 fs_reg orig_dst; 585 586 /* g0 header. */ 587 mlen = 1; 588 589 if (ir->shadow_comparitor && ir->op != ir_txd) { 590 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 591 fs_inst *inst = emit(BRW_OPCODE_MOV, 592 fs_reg(MRF, base_mrf + mlen + i), coordinate); 593 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 594 inst->saturate = true; 595 596 coordinate.reg_offset++; 597 } 598 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 599 mlen += 3; 600 601 if (ir->op == ir_tex) { 602 /* There's no plain shadow compare message, so we use shadow 603 * compare with a bias of 0.0. 604 */ 605 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 606 mlen++; 607 } else if (ir->op == ir_txb) { 608 ir->lod_info.bias->accept(this); 609 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 610 mlen++; 611 } else { 612 assert(ir->op == ir_txl); 613 ir->lod_info.lod->accept(this); 614 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 615 mlen++; 616 } 617 618 ir->shadow_comparitor->accept(this); 619 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 620 mlen++; 621 } else if (ir->op == ir_tex) { 622 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 623 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 624 coordinate); 625 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 626 inst->saturate = true; 627 coordinate.reg_offset++; 628 } 629 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 630 mlen += 3; 631 } else if (ir->op == ir_txd) { 632 ir->lod_info.grad.dPdx->accept(this); 633 fs_reg dPdx = this->result; 634 635 ir->lod_info.grad.dPdy->accept(this); 636 fs_reg dPdy = this->result; 637 638 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 639 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 640 coordinate.reg_offset++; 641 } 642 /* the slots for u and v are always present, but r is optional */ 643 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 644 645 /* P = u, v, r 646 * dPdx = dudx, dvdx, drdx 647 * dPdy = dudy, dvdy, drdy 648 * 649 * 1-arg: Does not exist. 650 * 651 * 2-arg: dudx dvdx dudy dvdy 652 * dPdx.x dPdx.y dPdy.x dPdy.y 653 * m4 m5 m6 m7 654 * 655 * 3-arg: dudx dvdx drdx dudy dvdy drdy 656 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 657 * m5 m6 m7 m8 m9 m10 658 */ 659 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 660 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 661 dPdx.reg_offset++; 662 } 663 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 664 665 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 666 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 667 dPdy.reg_offset++; 668 } 669 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 670 } else if (ir->op == ir_txs) { 671 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 672 simd16 = true; 673 ir->lod_info.lod->accept(this); 674 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 675 mlen += 2; 676 } else { 677 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 678 * instructions. We'll need to do SIMD16 here. 679 */ 680 simd16 = true; 681 assert(ir->op == ir_txb || ir->op == ir_txl); 682 683 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 684 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 685 base_mrf + mlen + i * 2), 686 coordinate); 687 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 688 inst->saturate = true; 689 coordinate.reg_offset++; 690 } 691 692 /* lod/bias appears after u/v/r. */ 693 mlen += 6; 694 695 if (ir->op == ir_txb) { 696 ir->lod_info.bias->accept(this); 697 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 698 mlen++; 699 } else { 700 ir->lod_info.lod->accept(this); 701 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 702 mlen++; 703 } 704 705 /* The unused upper half. */ 706 mlen++; 707 } 708 709 if (simd16) { 710 /* Now, since we're doing simd16, the return is 2 interleaved 711 * vec4s where the odd-indexed ones are junk. We'll need to move 712 * this weirdness around to the expected layout. 713 */ 714 orig_dst = dst; 715 const glsl_type *vec_type = 716 glsl_type::get_instance(ir->type->base_type, 4, 1); 717 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 718 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 719 : BRW_REGISTER_TYPE_F; 720 } 721 722 fs_inst *inst = NULL; 723 switch (ir->op) { 724 case ir_tex: 725 inst = emit(FS_OPCODE_TEX, dst); 726 break; 727 case ir_txb: 728 inst = emit(FS_OPCODE_TXB, dst); 729 break; 730 case ir_txl: 731 inst = emit(FS_OPCODE_TXL, dst); 732 break; 733 case ir_txd: 734 inst = emit(FS_OPCODE_TXD, dst); 735 break; 736 case ir_txs: 737 inst = emit(FS_OPCODE_TXS, dst); 738 break; 739 case ir_txf: 740 assert(!"GLSL 1.30 features unsupported"); 741 break; 742 } 743 inst->base_mrf = base_mrf; 744 inst->mlen = mlen; 745 inst->header_present = true; 746 747 if (simd16) { 748 for (int i = 0; i < 4; i++) { 749 emit(BRW_OPCODE_MOV, orig_dst, dst); 750 orig_dst.reg_offset++; 751 dst.reg_offset += 2; 752 } 753 } 754 755 return inst; 756} 757 758/* gen5's sampler has slots for u, v, r, array index, then optional 759 * parameters like shadow comparitor or LOD bias. If optional 760 * parameters aren't present, those base slots are optional and don't 761 * need to be included in the message. 762 * 763 * We don't fill in the unnecessary slots regardless, which may look 764 * surprising in the disassembly. 765 */ 766fs_inst * 767fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 768 int sampler) 769{ 770 int mlen = 0; 771 int base_mrf = 2; 772 int reg_width = c->dispatch_width / 8; 773 bool header_present = false; 774 const int vector_elements = 775 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 776 777 if (ir->offset) { 778 /* The offsets set up by the ir_texture visitor are in the 779 * m1 header, so we can't go headerless. 780 */ 781 header_present = true; 782 mlen++; 783 base_mrf--; 784 } 785 786 for (int i = 0; i < vector_elements; i++) { 787 fs_inst *inst = emit(BRW_OPCODE_MOV, 788 fs_reg(MRF, base_mrf + mlen + i * reg_width, 789 coordinate.type), 790 coordinate); 791 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 792 inst->saturate = true; 793 coordinate.reg_offset++; 794 } 795 mlen += vector_elements * reg_width; 796 797 if (ir->shadow_comparitor && ir->op != ir_txd) { 798 mlen = MAX2(mlen, header_present + 4 * reg_width); 799 800 ir->shadow_comparitor->accept(this); 801 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 802 mlen += reg_width; 803 } 804 805 fs_inst *inst = NULL; 806 switch (ir->op) { 807 case ir_tex: 808 inst = emit(FS_OPCODE_TEX, dst); 809 break; 810 case ir_txb: 811 ir->lod_info.bias->accept(this); 812 mlen = MAX2(mlen, header_present + 4 * reg_width); 813 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 814 mlen += reg_width; 815 816 inst = emit(FS_OPCODE_TXB, dst); 817 818 break; 819 case ir_txl: 820 ir->lod_info.lod->accept(this); 821 mlen = MAX2(mlen, header_present + 4 * reg_width); 822 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 823 mlen += reg_width; 824 825 inst = emit(FS_OPCODE_TXL, dst); 826 break; 827 case ir_txd: { 828 ir->lod_info.grad.dPdx->accept(this); 829 fs_reg dPdx = this->result; 830 831 ir->lod_info.grad.dPdy->accept(this); 832 fs_reg dPdy = this->result; 833 834 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 835 836 /** 837 * P = u, v, r 838 * dPdx = dudx, dvdx, drdx 839 * dPdy = dudy, dvdy, drdy 840 * 841 * Load up these values: 842 * - dudx dudy dvdx dvdy drdx drdy 843 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 844 */ 845 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 846 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 847 dPdx.reg_offset++; 848 mlen += reg_width; 849 850 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 851 dPdy.reg_offset++; 852 mlen += reg_width; 853 } 854 855 inst = emit(FS_OPCODE_TXD, dst); 856 break; 857 } 858 case ir_txs: 859 ir->lod_info.lod->accept(this); 860 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 861 mlen += reg_width; 862 inst = emit(FS_OPCODE_TXS, dst); 863 break; 864 case ir_txf: 865 mlen = header_present + 4 * reg_width; 866 867 ir->lod_info.lod->accept(this); 868 emit(BRW_OPCODE_MOV, 869 fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 870 this->result); 871 inst = emit(FS_OPCODE_TXF, dst); 872 break; 873 } 874 inst->base_mrf = base_mrf; 875 inst->mlen = mlen; 876 inst->header_present = header_present; 877 878 if (mlen > 11) { 879 fail("Message length >11 disallowed by hardware\n"); 880 } 881 882 return inst; 883} 884 885fs_inst * 886fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 887 int sampler) 888{ 889 int mlen = 0; 890 int base_mrf = 2; 891 int reg_width = c->dispatch_width / 8; 892 bool header_present = false; 893 894 if (ir->offset) { 895 /* The offsets set up by the ir_texture visitor are in the 896 * m1 header, so we can't go headerless. 897 */ 898 header_present = true; 899 mlen++; 900 base_mrf--; 901 } 902 903 if (ir->shadow_comparitor && ir->op != ir_txd) { 904 ir->shadow_comparitor->accept(this); 905 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 906 mlen += reg_width; 907 } 908 909 /* Set up the LOD info */ 910 switch (ir->op) { 911 case ir_tex: 912 break; 913 case ir_txb: 914 ir->lod_info.bias->accept(this); 915 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 916 mlen += reg_width; 917 break; 918 case ir_txl: 919 ir->lod_info.lod->accept(this); 920 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 921 mlen += reg_width; 922 break; 923 case ir_txd: { 924 if (c->dispatch_width == 16) 925 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 926 927 ir->lod_info.grad.dPdx->accept(this); 928 fs_reg dPdx = this->result; 929 930 ir->lod_info.grad.dPdy->accept(this); 931 fs_reg dPdy = this->result; 932 933 /* Load dPdx and the coordinate together: 934 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 935 */ 936 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 937 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 938 coordinate); 939 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 940 inst->saturate = true; 941 coordinate.reg_offset++; 942 mlen += reg_width; 943 944 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 945 dPdx.reg_offset++; 946 mlen += reg_width; 947 948 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 949 dPdy.reg_offset++; 950 mlen += reg_width; 951 } 952 break; 953 } 954 case ir_txs: 955 ir->lod_info.lod->accept(this); 956 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 957 mlen += reg_width; 958 break; 959 case ir_txf: 960 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */ 961 fs_inst *inst = emit(BRW_OPCODE_MOV, 962 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), 963 coordinate); 964 coordinate.reg_offset++; 965 mlen += reg_width; 966 967 ir->lod_info.lod->accept(this); 968 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result); 969 mlen += reg_width; 970 971 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { 972 fs_inst *inst = emit(BRW_OPCODE_MOV, 973 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), 974 coordinate); 975 coordinate.reg_offset++; 976 mlen += reg_width; 977 } 978 break; 979 } 980 981 /* Set up the coordinate (except for cases where it was done above) */ 982 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { 983 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 984 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 985 coordinate); 986 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 987 inst->saturate = true; 988 coordinate.reg_offset++; 989 mlen += reg_width; 990 } 991 } 992 993 /* Generate the SEND */ 994 fs_inst *inst = NULL; 995 switch (ir->op) { 996 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 997 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 998 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 999 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 1000 case ir_txf: inst = emit(FS_OPCODE_TXF, dst); break; 1001 case ir_txs: inst = emit(FS_OPCODE_TXS, dst); break; 1002 } 1003 inst->base_mrf = base_mrf; 1004 inst->mlen = mlen; 1005 inst->header_present = header_present; 1006 1007 if (mlen > 11) { 1008 fail("Message length >11 disallowed by hardware\n"); 1009 } 1010 1011 return inst; 1012} 1013 1014void 1015fs_visitor::visit(ir_texture *ir) 1016{ 1017 fs_inst *inst = NULL; 1018 1019 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1020 sampler = fp->Base.SamplerUnits[sampler]; 1021 1022 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1023 * for textureGrad/TXD need to be emulated with instructions. 1024 */ 1025 bool hw_compare_supported = ir->op != ir_txd; 1026 if (ir->shadow_comparitor && !hw_compare_supported) { 1027 assert(c->key.compare_funcs[sampler] != GL_NONE); 1028 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1029 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 1030 return swizzle_result(ir, fs_reg(1.0f), sampler); 1031 else if (c->key.compare_funcs[sampler] == GL_NEVER) 1032 return swizzle_result(ir, fs_reg(0.0f), sampler); 1033 } 1034 1035 if (ir->coordinate) 1036 ir->coordinate->accept(this); 1037 fs_reg coordinate = this->result; 1038 1039 if (ir->offset != NULL) { 1040 ir_constant *offset = ir->offset->as_constant(); 1041 assert(offset != NULL); 1042 1043 signed char offsets[3]; 1044 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 1045 offsets[i] = (signed char) offset->value.i[i]; 1046 1047 /* Combine all three offsets into a single unsigned dword: 1048 * 1049 * bits 11:8 - U Offset (X component) 1050 * bits 7:4 - V Offset (Y component) 1051 * bits 3:0 - R Offset (Z component) 1052 */ 1053 unsigned offset_bits = 0; 1054 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1055 const unsigned shift = 4 * (2 - i); 1056 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1057 } 1058 1059 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1060 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1061 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 1062 1063 /* Then set the offset bits in DWord 2 of the message header. */ 1064 emit(BRW_OPCODE_MOV, 1065 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1066 BRW_REGISTER_TYPE_UD)), 1067 fs_reg(brw_imm_uw(offset_bits))); 1068 } 1069 1070 /* Should be lowered by do_lower_texture_projection */ 1071 assert(!ir->projector); 1072 1073 /* The 965 requires the EU to do the normalization of GL rectangle 1074 * texture coordinates. We use the program parameter state 1075 * tracking to get the scaling factor. 1076 */ 1077 if (intel->gen < 6 && 1078 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1079 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1080 int tokens[STATE_LENGTH] = { 1081 STATE_INTERNAL, 1082 STATE_TEXRECT_SCALE, 1083 sampler, 1084 0, 1085 0 1086 }; 1087 1088 if (c->dispatch_width == 16) { 1089 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1090 this->result = fs_reg(this, ir->type); 1091 return; 1092 } 1093 1094 c->prog_data.param_convert[c->prog_data.nr_params] = 1095 PARAM_NO_CONVERT; 1096 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1097 PARAM_NO_CONVERT; 1098 1099 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1100 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1101 GLuint index = _mesa_add_state_reference(params, 1102 (gl_state_index *)tokens); 1103 1104 this->param_index[c->prog_data.nr_params] = index; 1105 this->param_offset[c->prog_data.nr_params] = 0; 1106 c->prog_data.nr_params++; 1107 this->param_index[c->prog_data.nr_params] = index; 1108 this->param_offset[c->prog_data.nr_params] = 1; 1109 c->prog_data.nr_params++; 1110 1111 fs_reg dst = fs_reg(this, ir->coordinate->type); 1112 fs_reg src = coordinate; 1113 coordinate = dst; 1114 1115 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1116 dst.reg_offset++; 1117 src.reg_offset++; 1118 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1119 } 1120 1121 /* Writemasking doesn't eliminate channels on SIMD8 texture 1122 * samples, so don't worry about them. 1123 */ 1124 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1125 1126 if (intel->gen >= 7) { 1127 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1128 } else if (intel->gen >= 5) { 1129 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1130 } else { 1131 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1132 } 1133 1134 /* If there's an offset, we already set up m1. To avoid the implied move, 1135 * use the null register. Otherwise, we want an implied move from g0. 1136 */ 1137 if (ir->offset != NULL || !inst->header_present) 1138 inst->src[0] = reg_undef; 1139 else 1140 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1141 1142 inst->sampler = sampler; 1143 1144 if (ir->shadow_comparitor) { 1145 if (hw_compare_supported) { 1146 inst->shadow_compare = true; 1147 } else { 1148 ir->shadow_comparitor->accept(this); 1149 fs_reg ref = this->result; 1150 1151 fs_reg value = dst; 1152 dst = fs_reg(this, glsl_type::vec4_type); 1153 1154 /* FINISHME: This needs to be done pre-filtering. */ 1155 1156 uint32_t conditional = 0; 1157 switch (c->key.compare_funcs[sampler]) { 1158 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1159 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1160 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1161 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1162 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1163 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1164 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1165 default: assert(!"Should not get here: bad shadow compare function"); 1166 } 1167 1168 /* Use conditional moves to load 0 or 1 as the result */ 1169 this->current_annotation = "manual shadow comparison"; 1170 for (int i = 0; i < 4; i++) { 1171 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1172 1173 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1174 inst->conditional_mod = conditional; 1175 1176 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1177 inst->predicated = true; 1178 1179 dst.reg_offset++; 1180 value.reg_offset++; 1181 } 1182 dst.reg_offset = 0; 1183 } 1184 } 1185 1186 swizzle_result(ir, dst, sampler); 1187} 1188 1189/** 1190 * Swizzle the result of a texture result. This is necessary for 1191 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1192 */ 1193void 1194fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1195{ 1196 this->result = orig_val; 1197 1198 if (ir->type == glsl_type::float_type) { 1199 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1200 assert(ir->sampler->type->sampler_shadow); 1201 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1202 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1203 1204 for (int i = 0; i < 4; i++) { 1205 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1206 fs_reg l = swizzled_result; 1207 l.reg_offset += i; 1208 1209 if (swiz == SWIZZLE_ZERO) { 1210 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1211 } else if (swiz == SWIZZLE_ONE) { 1212 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1213 } else { 1214 fs_reg r = orig_val; 1215 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1216 emit(BRW_OPCODE_MOV, l, r); 1217 } 1218 } 1219 this->result = swizzled_result; 1220 } 1221} 1222 1223void 1224fs_visitor::visit(ir_swizzle *ir) 1225{ 1226 ir->val->accept(this); 1227 fs_reg val = this->result; 1228 1229 if (ir->type->vector_elements == 1) { 1230 this->result.reg_offset += ir->mask.x; 1231 return; 1232 } 1233 1234 fs_reg result = fs_reg(this, ir->type); 1235 this->result = result; 1236 1237 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1238 fs_reg channel = val; 1239 int swiz = 0; 1240 1241 switch (i) { 1242 case 0: 1243 swiz = ir->mask.x; 1244 break; 1245 case 1: 1246 swiz = ir->mask.y; 1247 break; 1248 case 2: 1249 swiz = ir->mask.z; 1250 break; 1251 case 3: 1252 swiz = ir->mask.w; 1253 break; 1254 } 1255 1256 channel.reg_offset += swiz; 1257 emit(BRW_OPCODE_MOV, result, channel); 1258 result.reg_offset++; 1259 } 1260} 1261 1262void 1263fs_visitor::visit(ir_discard *ir) 1264{ 1265 assert(ir->condition == NULL); /* FINISHME */ 1266 1267 emit(FS_OPCODE_DISCARD); 1268 kill_emitted = true; 1269} 1270 1271void 1272fs_visitor::visit(ir_constant *ir) 1273{ 1274 /* Set this->result to reg at the bottom of the function because some code 1275 * paths will cause this visitor to be applied to other fields. This will 1276 * cause the value stored in this->result to be modified. 1277 * 1278 * Make reg constant so that it doesn't get accidentally modified along the 1279 * way. Yes, I actually had this problem. :( 1280 */ 1281 const fs_reg reg(this, ir->type); 1282 fs_reg dst_reg = reg; 1283 1284 if (ir->type->is_array()) { 1285 const unsigned size = type_size(ir->type->fields.array); 1286 1287 for (unsigned i = 0; i < ir->type->length; i++) { 1288 ir->array_elements[i]->accept(this); 1289 fs_reg src_reg = this->result; 1290 1291 dst_reg.type = src_reg.type; 1292 for (unsigned j = 0; j < size; j++) { 1293 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1294 src_reg.reg_offset++; 1295 dst_reg.reg_offset++; 1296 } 1297 } 1298 } else if (ir->type->is_record()) { 1299 foreach_list(node, &ir->components) { 1300 ir_instruction *const field = (ir_instruction *) node; 1301 const unsigned size = type_size(field->type); 1302 1303 field->accept(this); 1304 fs_reg src_reg = this->result; 1305 1306 dst_reg.type = src_reg.type; 1307 for (unsigned j = 0; j < size; j++) { 1308 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1309 src_reg.reg_offset++; 1310 dst_reg.reg_offset++; 1311 } 1312 } 1313 } else { 1314 const unsigned size = type_size(ir->type); 1315 1316 for (unsigned i = 0; i < size; i++) { 1317 switch (ir->type->base_type) { 1318 case GLSL_TYPE_FLOAT: 1319 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1320 break; 1321 case GLSL_TYPE_UINT: 1322 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1323 break; 1324 case GLSL_TYPE_INT: 1325 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1326 break; 1327 case GLSL_TYPE_BOOL: 1328 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1329 break; 1330 default: 1331 assert(!"Non-float/uint/int/bool constant"); 1332 } 1333 dst_reg.reg_offset++; 1334 } 1335 } 1336 1337 this->result = reg; 1338} 1339 1340void 1341fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1342{ 1343 ir_expression *expr = ir->as_expression(); 1344 1345 if (expr) { 1346 fs_reg op[2]; 1347 fs_inst *inst; 1348 1349 assert(expr->get_num_operands() <= 2); 1350 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1351 assert(expr->operands[i]->type->is_scalar()); 1352 1353 expr->operands[i]->accept(this); 1354 op[i] = this->result; 1355 } 1356 1357 switch (expr->operation) { 1358 case ir_unop_logic_not: 1359 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1360 inst->conditional_mod = BRW_CONDITIONAL_Z; 1361 break; 1362 1363 case ir_binop_logic_xor: 1364 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1365 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1366 break; 1367 1368 case ir_binop_logic_or: 1369 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1370 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1371 break; 1372 1373 case ir_binop_logic_and: 1374 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1375 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1376 break; 1377 1378 case ir_unop_f2b: 1379 if (intel->gen >= 6) { 1380 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1381 } else { 1382 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1383 } 1384 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1385 break; 1386 1387 case ir_unop_i2b: 1388 if (intel->gen >= 6) { 1389 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1390 } else { 1391 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1392 } 1393 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1394 break; 1395 1396 case ir_binop_greater: 1397 case ir_binop_gequal: 1398 case ir_binop_less: 1399 case ir_binop_lequal: 1400 case ir_binop_equal: 1401 case ir_binop_all_equal: 1402 case ir_binop_nequal: 1403 case ir_binop_any_nequal: 1404 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1405 inst->conditional_mod = 1406 brw_conditional_for_comparison(expr->operation); 1407 break; 1408 1409 default: 1410 assert(!"not reached"); 1411 fail("bad cond code\n"); 1412 break; 1413 } 1414 return; 1415 } 1416 1417 ir->accept(this); 1418 1419 if (intel->gen >= 6) { 1420 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1421 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1422 } else { 1423 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1424 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1425 } 1426} 1427 1428/** 1429 * Emit a gen6 IF statement with the comparison folded into the IF 1430 * instruction. 1431 */ 1432void 1433fs_visitor::emit_if_gen6(ir_if *ir) 1434{ 1435 ir_expression *expr = ir->condition->as_expression(); 1436 1437 if (expr) { 1438 fs_reg op[2]; 1439 fs_inst *inst; 1440 fs_reg temp; 1441 1442 assert(expr->get_num_operands() <= 2); 1443 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1444 assert(expr->operands[i]->type->is_scalar()); 1445 1446 expr->operands[i]->accept(this); 1447 op[i] = this->result; 1448 } 1449 1450 switch (expr->operation) { 1451 case ir_unop_logic_not: 1452 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1453 inst->conditional_mod = BRW_CONDITIONAL_Z; 1454 return; 1455 1456 case ir_binop_logic_xor: 1457 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1458 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1459 return; 1460 1461 case ir_binop_logic_or: 1462 temp = fs_reg(this, glsl_type::bool_type); 1463 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1464 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1465 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1466 return; 1467 1468 case ir_binop_logic_and: 1469 temp = fs_reg(this, glsl_type::bool_type); 1470 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1471 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1472 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1473 return; 1474 1475 case ir_unop_f2b: 1476 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1477 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1478 return; 1479 1480 case ir_unop_i2b: 1481 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1482 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1483 return; 1484 1485 case ir_binop_greater: 1486 case ir_binop_gequal: 1487 case ir_binop_less: 1488 case ir_binop_lequal: 1489 case ir_binop_equal: 1490 case ir_binop_all_equal: 1491 case ir_binop_nequal: 1492 case ir_binop_any_nequal: 1493 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1494 inst->conditional_mod = 1495 brw_conditional_for_comparison(expr->operation); 1496 return; 1497 default: 1498 assert(!"not reached"); 1499 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1500 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1501 fail("bad condition\n"); 1502 return; 1503 } 1504 return; 1505 } 1506 1507 ir->condition->accept(this); 1508 1509 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1510 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1511} 1512 1513void 1514fs_visitor::visit(ir_if *ir) 1515{ 1516 fs_inst *inst; 1517 1518 if (intel->gen != 6 && c->dispatch_width == 16) { 1519 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1520 } 1521 1522 /* Don't point the annotation at the if statement, because then it plus 1523 * the then and else blocks get printed. 1524 */ 1525 this->base_ir = ir->condition; 1526 1527 if (intel->gen == 6) { 1528 emit_if_gen6(ir); 1529 } else { 1530 emit_bool_to_cond_code(ir->condition); 1531 1532 inst = emit(BRW_OPCODE_IF); 1533 inst->predicated = true; 1534 } 1535 1536 foreach_list(node, &ir->then_instructions) { 1537 ir_instruction *ir = (ir_instruction *)node; 1538 this->base_ir = ir; 1539 1540 ir->accept(this); 1541 } 1542 1543 if (!ir->else_instructions.is_empty()) { 1544 emit(BRW_OPCODE_ELSE); 1545 1546 foreach_list(node, &ir->else_instructions) { 1547 ir_instruction *ir = (ir_instruction *)node; 1548 this->base_ir = ir; 1549 1550 ir->accept(this); 1551 } 1552 } 1553 1554 emit(BRW_OPCODE_ENDIF); 1555} 1556 1557void 1558fs_visitor::visit(ir_loop *ir) 1559{ 1560 fs_reg counter = reg_undef; 1561 1562 if (c->dispatch_width == 16) { 1563 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1564 } 1565 1566 if (ir->counter) { 1567 this->base_ir = ir->counter; 1568 ir->counter->accept(this); 1569 counter = *(variable_storage(ir->counter)); 1570 1571 if (ir->from) { 1572 this->base_ir = ir->from; 1573 ir->from->accept(this); 1574 1575 emit(BRW_OPCODE_MOV, counter, this->result); 1576 } 1577 } 1578 1579 emit(BRW_OPCODE_DO); 1580 1581 if (ir->to) { 1582 this->base_ir = ir->to; 1583 ir->to->accept(this); 1584 1585 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1586 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1587 1588 inst = emit(BRW_OPCODE_BREAK); 1589 inst->predicated = true; 1590 } 1591 1592 foreach_list(node, &ir->body_instructions) { 1593 ir_instruction *ir = (ir_instruction *)node; 1594 1595 this->base_ir = ir; 1596 ir->accept(this); 1597 } 1598 1599 if (ir->increment) { 1600 this->base_ir = ir->increment; 1601 ir->increment->accept(this); 1602 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1603 } 1604 1605 emit(BRW_OPCODE_WHILE); 1606} 1607 1608void 1609fs_visitor::visit(ir_loop_jump *ir) 1610{ 1611 switch (ir->mode) { 1612 case ir_loop_jump::jump_break: 1613 emit(BRW_OPCODE_BREAK); 1614 break; 1615 case ir_loop_jump::jump_continue: 1616 emit(BRW_OPCODE_CONTINUE); 1617 break; 1618 } 1619} 1620 1621void 1622fs_visitor::visit(ir_call *ir) 1623{ 1624 assert(!"FINISHME"); 1625} 1626 1627void 1628fs_visitor::visit(ir_return *ir) 1629{ 1630 assert(!"FINISHME"); 1631} 1632 1633void 1634fs_visitor::visit(ir_function *ir) 1635{ 1636 /* Ignore function bodies other than main() -- we shouldn't see calls to 1637 * them since they should all be inlined before we get to ir_to_mesa. 1638 */ 1639 if (strcmp(ir->name, "main") == 0) { 1640 const ir_function_signature *sig; 1641 exec_list empty; 1642 1643 sig = ir->matching_signature(&empty); 1644 1645 assert(sig); 1646 1647 foreach_list(node, &sig->body) { 1648 ir_instruction *ir = (ir_instruction *)node; 1649 this->base_ir = ir; 1650 1651 ir->accept(this); 1652 } 1653 } 1654} 1655 1656void 1657fs_visitor::visit(ir_function_signature *ir) 1658{ 1659 assert(!"not reached"); 1660 (void)ir; 1661} 1662 1663fs_inst * 1664fs_visitor::emit(fs_inst inst) 1665{ 1666 fs_inst *list_inst = new(mem_ctx) fs_inst; 1667 *list_inst = inst; 1668 1669 if (force_uncompressed_stack > 0) 1670 list_inst->force_uncompressed = true; 1671 else if (force_sechalf_stack > 0) 1672 list_inst->force_sechalf = true; 1673 1674 list_inst->annotation = this->current_annotation; 1675 list_inst->ir = this->base_ir; 1676 1677 this->instructions.push_tail(list_inst); 1678 1679 return list_inst; 1680} 1681 1682/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1683void 1684fs_visitor::emit_dummy_fs() 1685{ 1686 /* Everyone's favorite color. */ 1687 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1688 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1689 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1690 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1691 1692 fs_inst *write; 1693 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1694 write->base_mrf = 2; 1695} 1696 1697/* The register location here is relative to the start of the URB 1698 * data. It will get adjusted to be a real location before 1699 * generate_code() time. 1700 */ 1701struct brw_reg 1702fs_visitor::interp_reg(int location, int channel) 1703{ 1704 int regnr = urb_setup[location] * 2 + channel / 2; 1705 int stride = (channel & 1) * 4; 1706 1707 assert(urb_setup[location] != -1); 1708 1709 return brw_vec1_grf(regnr, stride); 1710} 1711 1712/** Emits the interpolation for the varying inputs. */ 1713void 1714fs_visitor::emit_interpolation_setup_gen4() 1715{ 1716 this->current_annotation = "compute pixel centers"; 1717 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1718 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1719 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1720 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1721 1722 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1723 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1724 1725 this->current_annotation = "compute pixel deltas from v0"; 1726 if (brw->has_pln) { 1727 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1728 this->delta_y = this->delta_x; 1729 this->delta_y.reg_offset++; 1730 } else { 1731 this->delta_x = fs_reg(this, glsl_type::float_type); 1732 this->delta_y = fs_reg(this, glsl_type::float_type); 1733 } 1734 emit(BRW_OPCODE_ADD, this->delta_x, 1735 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1736 emit(BRW_OPCODE_ADD, this->delta_y, 1737 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1738 1739 this->current_annotation = "compute pos.w and 1/pos.w"; 1740 /* Compute wpos.w. It's always in our setup, since it's needed to 1741 * interpolate the other attributes. 1742 */ 1743 this->wpos_w = fs_reg(this, glsl_type::float_type); 1744 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1745 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1746 /* Compute the pixel 1/W value from wpos.w. */ 1747 this->pixel_w = fs_reg(this, glsl_type::float_type); 1748 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1749 this->current_annotation = NULL; 1750} 1751 1752/** Emits the interpolation for the varying inputs. */ 1753void 1754fs_visitor::emit_interpolation_setup_gen6() 1755{ 1756 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1757 1758 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1759 this->current_annotation = "compute pixel centers"; 1760 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1761 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1762 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1763 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1764 emit(BRW_OPCODE_ADD, 1765 int_pixel_x, 1766 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1767 fs_reg(brw_imm_v(0x10101010))); 1768 emit(BRW_OPCODE_ADD, 1769 int_pixel_y, 1770 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1771 fs_reg(brw_imm_v(0x11001100))); 1772 1773 /* As of gen6, we can no longer mix float and int sources. We have 1774 * to turn the integer pixel centers into floats for their actual 1775 * use. 1776 */ 1777 this->pixel_x = fs_reg(this, glsl_type::float_type); 1778 this->pixel_y = fs_reg(this, glsl_type::float_type); 1779 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1780 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1781 1782 this->current_annotation = "compute pos.w"; 1783 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1784 this->wpos_w = fs_reg(this, glsl_type::float_type); 1785 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1786 1787 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1788 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1789 1790 this->current_annotation = NULL; 1791} 1792 1793void 1794fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1795{ 1796 int reg_width = c->dispatch_width / 8; 1797 fs_inst *inst; 1798 1799 if (c->dispatch_width == 8 || intel->gen == 6) { 1800 /* SIMD8 write looks like: 1801 * m + 0: r0 1802 * m + 1: r1 1803 * m + 2: g0 1804 * m + 3: g1 1805 * 1806 * gen6 SIMD16 DP write looks like: 1807 * m + 0: r0 1808 * m + 1: r1 1809 * m + 2: g0 1810 * m + 3: g1 1811 * m + 4: b0 1812 * m + 5: b1 1813 * m + 6: a0 1814 * m + 7: a1 1815 */ 1816 inst = emit(BRW_OPCODE_MOV, 1817 fs_reg(MRF, first_color_mrf + index * reg_width), 1818 color); 1819 inst->saturate = c->key.clamp_fragment_color; 1820 } else { 1821 /* pre-gen6 SIMD16 single source DP write looks like: 1822 * m + 0: r0 1823 * m + 1: g0 1824 * m + 2: b0 1825 * m + 3: a0 1826 * m + 4: r1 1827 * m + 5: g1 1828 * m + 6: b1 1829 * m + 7: a1 1830 */ 1831 if (brw->has_compr4) { 1832 /* By setting the high bit of the MRF register number, we 1833 * indicate that we want COMPR4 mode - instead of doing the 1834 * usual destination + 1 for the second half we get 1835 * destination + 4. 1836 */ 1837 inst = emit(BRW_OPCODE_MOV, 1838 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1839 color); 1840 inst->saturate = c->key.clamp_fragment_color; 1841 } else { 1842 push_force_uncompressed(); 1843 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1844 color); 1845 inst->saturate = c->key.clamp_fragment_color; 1846 pop_force_uncompressed(); 1847 1848 push_force_sechalf(); 1849 color.sechalf = true; 1850 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1851 color); 1852 inst->saturate = c->key.clamp_fragment_color; 1853 pop_force_sechalf(); 1854 color.sechalf = false; 1855 } 1856 } 1857} 1858 1859void 1860fs_visitor::emit_fb_writes() 1861{ 1862 this->current_annotation = "FB write header"; 1863 GLboolean header_present = GL_TRUE; 1864 int base_mrf = 2; 1865 int nr = base_mrf; 1866 int reg_width = c->dispatch_width / 8; 1867 1868 if (intel->gen >= 6 && 1869 !this->kill_emitted && 1870 c->key.nr_color_regions == 1) { 1871 header_present = false; 1872 } 1873 1874 if (header_present) { 1875 /* m2, m3 header */ 1876 nr += 2; 1877 } 1878 1879 if (c->aa_dest_stencil_reg) { 1880 push_force_uncompressed(); 1881 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1882 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1883 pop_force_uncompressed(); 1884 } 1885 1886 /* Reserve space for color. It'll be filled in per MRT below. */ 1887 int color_mrf = nr; 1888 nr += 4 * reg_width; 1889 1890 if (c->source_depth_to_render_target) { 1891 if (intel->gen == 6 && c->dispatch_width == 16) { 1892 /* For outputting oDepth on gen6, SIMD8 writes have to be 1893 * used. This would require 8-wide moves of each half to 1894 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1895 * Just bail on doing so for now. 1896 */ 1897 fail("Missing support for simd16 depth writes on gen6\n"); 1898 } 1899 1900 if (c->computes_depth) { 1901 /* Hand over gl_FragDepth. */ 1902 assert(this->frag_depth); 1903 fs_reg depth = *(variable_storage(this->frag_depth)); 1904 1905 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1906 } else { 1907 /* Pass through the payload depth. */ 1908 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1909 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1910 } 1911 nr += reg_width; 1912 } 1913 1914 if (c->dest_depth_reg) { 1915 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1916 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1917 nr += reg_width; 1918 } 1919 1920 fs_reg color = reg_undef; 1921 if (this->frag_color) 1922 color = *(variable_storage(this->frag_color)); 1923 else if (this->frag_data) { 1924 color = *(variable_storage(this->frag_data)); 1925 color.type = BRW_REGISTER_TYPE_F; 1926 } 1927 1928 for (int target = 0; target < c->key.nr_color_regions; target++) { 1929 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1930 "FB write target %d", 1931 target); 1932 if (this->frag_color || this->frag_data) { 1933 for (int i = 0; i < 4; i++) { 1934 emit_color_write(i, color_mrf, color); 1935 color.reg_offset++; 1936 } 1937 } 1938 1939 if (this->frag_color) 1940 color.reg_offset -= 4; 1941 1942 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1943 inst->target = target; 1944 inst->base_mrf = base_mrf; 1945 inst->mlen = nr - base_mrf; 1946 if (target == c->key.nr_color_regions - 1) 1947 inst->eot = true; 1948 inst->header_present = header_present; 1949 } 1950 1951 if (c->key.nr_color_regions == 0) { 1952 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1953 /* If the alpha test is enabled but there's no color buffer, 1954 * we still need to send alpha out the pipeline to our null 1955 * renderbuffer. 1956 */ 1957 color.reg_offset += 3; 1958 emit_color_write(3, color_mrf, color); 1959 } 1960 1961 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1962 inst->base_mrf = base_mrf; 1963 inst->mlen = nr - base_mrf; 1964 inst->eot = true; 1965 inst->header_present = header_present; 1966 } 1967 1968 this->current_annotation = NULL; 1969} 1970