brw_fs_visitor.cpp revision 29362875f2613ad87abe7725ce3c56c36d16cf9b
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (ir->mode == ir_var_in) { 62 if (!strcmp(ir->name, "gl_FragCoord")) { 63 reg = emit_fragcoord_interpolation(ir); 64 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 65 reg = emit_frontfacing_interpolation(ir); 66 } else { 67 reg = emit_general_interpolation(ir); 68 } 69 assert(reg); 70 hash_table_insert(this->variable_ht, reg, ir); 71 return; 72 } else if (ir->mode == ir_var_out) { 73 reg = new(this->mem_ctx) fs_reg(this, ir->type); 74 75 if (ir->index > 0) { 76 assert(ir->location == FRAG_RESULT_DATA0); 77 assert(ir->index == 1); 78 this->dual_src_output = *reg; 79 } else if (ir->location == FRAG_RESULT_COLOR) { 80 /* Writing gl_FragColor outputs to all color regions. */ 81 for (unsigned int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) { 82 this->outputs[i] = *reg; 83 } 84 } else if (ir->location == FRAG_RESULT_DEPTH) { 85 this->frag_depth = ir; 86 } else { 87 /* gl_FragData or a user-defined FS output */ 88 assert(ir->location >= FRAG_RESULT_DATA0 && 89 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS); 90 91 /* General color output. */ 92 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) { 93 int output = ir->location - FRAG_RESULT_DATA0 + i; 94 this->outputs[output] = *reg; 95 this->outputs[output].reg_offset += 4 * i; 96 } 97 } 98 } else if (ir->mode == ir_var_uniform) { 99 int param_index = c->prog_data.nr_params; 100 101 if (c->dispatch_width == 16) { 102 if (!variable_storage(ir)) { 103 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 104 } 105 return; 106 } 107 108 if (!strncmp(ir->name, "gl_", 3)) { 109 setup_builtin_uniform_values(ir); 110 } else { 111 setup_uniform_values(ir->location, ir->type); 112 } 113 114 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 115 reg->type = brw_type_for_base_type(ir->type); 116 } 117 118 if (!reg) 119 reg = new(this->mem_ctx) fs_reg(this, ir->type); 120 121 hash_table_insert(this->variable_ht, reg, ir); 122} 123 124void 125fs_visitor::visit(ir_dereference_variable *ir) 126{ 127 fs_reg *reg = variable_storage(ir->var); 128 this->result = *reg; 129} 130 131void 132fs_visitor::visit(ir_dereference_record *ir) 133{ 134 const glsl_type *struct_type = ir->record->type; 135 136 ir->record->accept(this); 137 138 unsigned int offset = 0; 139 for (unsigned int i = 0; i < struct_type->length; i++) { 140 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 141 break; 142 offset += type_size(struct_type->fields.structure[i].type); 143 } 144 this->result.reg_offset += offset; 145 this->result.type = brw_type_for_base_type(ir->type); 146} 147 148void 149fs_visitor::visit(ir_dereference_array *ir) 150{ 151 ir_constant *index; 152 int element_size; 153 154 ir->array->accept(this); 155 index = ir->array_index->as_constant(); 156 157 element_size = type_size(ir->type); 158 this->result.type = brw_type_for_base_type(ir->type); 159 160 if (index) { 161 assert(this->result.file == UNIFORM || this->result.file == GRF); 162 this->result.reg_offset += index->value.i[0] * element_size; 163 } else { 164 assert(!"FINISHME: non-constant array element"); 165 } 166} 167 168/* Instruction selection: Produce a MOV.sat instead of 169 * MIN(MAX(val, 0), 1) when possible. 170 */ 171bool 172fs_visitor::try_emit_saturate(ir_expression *ir) 173{ 174 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 175 176 if (!sat_val) 177 return false; 178 179 fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail(); 180 181 sat_val->accept(this); 182 fs_reg src = this->result; 183 184 fs_inst *last_inst = (fs_inst *) this->instructions.get_tail(); 185 186 /* If the last instruction from our accept() didn't generate our 187 * src, generate a saturated MOV 188 */ 189 fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src); 190 if (!modify || modify->regs_written() != 1) { 191 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 192 inst->saturate = true; 193 } else { 194 modify->saturate = true; 195 this->result = src; 196 } 197 198 199 return true; 200} 201 202bool 203fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg) 204{ 205 /* 3-src instructions were introduced in gen6. */ 206 if (intel->gen < 6) 207 return false; 208 209 /* MAD can only handle floating-point data. */ 210 if (ir->type != glsl_type::float_type) 211 return false; 212 213 ir_rvalue *nonmul = ir->operands[1 - mul_arg]; 214 ir_expression *mul = ir->operands[mul_arg]->as_expression(); 215 216 if (!mul || mul->operation != ir_binop_mul) 217 return false; 218 219 if (nonmul->as_constant() || 220 mul->operands[0]->as_constant() || 221 mul->operands[1]->as_constant()) 222 return false; 223 224 nonmul->accept(this); 225 fs_reg src0 = this->result; 226 227 mul->operands[0]->accept(this); 228 fs_reg src1 = this->result; 229 230 mul->operands[1]->accept(this); 231 fs_reg src2 = this->result; 232 233 this->result = fs_reg(this, ir->type); 234 emit(BRW_OPCODE_MAD, this->result, src0, src1, src2); 235 236 return true; 237} 238 239void 240fs_visitor::visit(ir_expression *ir) 241{ 242 unsigned int operand; 243 fs_reg op[2], temp; 244 fs_inst *inst; 245 246 assert(ir->get_num_operands() <= 2); 247 248 if (try_emit_saturate(ir)) 249 return; 250 if (ir->operation == ir_binop_add) { 251 if (try_emit_mad(ir, 0) || try_emit_mad(ir, 1)) 252 return; 253 } 254 255 for (operand = 0; operand < ir->get_num_operands(); operand++) { 256 ir->operands[operand]->accept(this); 257 if (this->result.file == BAD_FILE) { 258 ir_print_visitor v; 259 fail("Failed to get tree for expression operand:\n"); 260 ir->operands[operand]->accept(&v); 261 } 262 op[operand] = this->result; 263 264 /* Matrix expression operands should have been broken down to vector 265 * operations already. 266 */ 267 assert(!ir->operands[operand]->type->is_matrix()); 268 /* And then those vector operands should have been broken down to scalar. 269 */ 270 assert(!ir->operands[operand]->type->is_vector()); 271 } 272 273 /* Storage for our result. If our result goes into an assignment, it will 274 * just get copy-propagated out, so no worries. 275 */ 276 this->result = fs_reg(this, ir->type); 277 278 switch (ir->operation) { 279 case ir_unop_logic_not: 280 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 281 * ones complement of the whole register, not just bit 0. 282 */ 283 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 284 break; 285 case ir_unop_neg: 286 op[0].negate = !op[0].negate; 287 this->result = op[0]; 288 break; 289 case ir_unop_abs: 290 op[0].abs = true; 291 op[0].negate = false; 292 this->result = op[0]; 293 break; 294 case ir_unop_sign: 295 temp = fs_reg(this, ir->type); 296 297 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 298 299 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 300 inst->conditional_mod = BRW_CONDITIONAL_G; 301 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 302 inst->predicated = true; 303 304 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 305 inst->conditional_mod = BRW_CONDITIONAL_L; 306 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 307 inst->predicated = true; 308 309 break; 310 case ir_unop_rcp: 311 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 312 break; 313 314 case ir_unop_exp2: 315 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 316 break; 317 case ir_unop_log2: 318 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 319 break; 320 case ir_unop_exp: 321 case ir_unop_log: 322 assert(!"not reached: should be handled by ir_explog_to_explog2"); 323 break; 324 case ir_unop_sin: 325 case ir_unop_sin_reduced: 326 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 327 break; 328 case ir_unop_cos: 329 case ir_unop_cos_reduced: 330 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 331 break; 332 333 case ir_unop_dFdx: 334 emit(FS_OPCODE_DDX, this->result, op[0]); 335 break; 336 case ir_unop_dFdy: 337 emit(FS_OPCODE_DDY, this->result, op[0]); 338 break; 339 340 case ir_binop_add: 341 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 342 break; 343 case ir_binop_sub: 344 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 345 break; 346 347 case ir_binop_mul: 348 if (ir->type->is_integer()) { 349 /* For integer multiplication, the MUL uses the low 16 bits 350 * of one of the operands (src0 on gen6, src1 on gen7). The 351 * MACH accumulates in the contribution of the upper 16 bits 352 * of that operand. 353 * 354 * FINISHME: Emit just the MUL if we know an operand is small 355 * enough. 356 */ 357 if (intel->gen >= 7 && c->dispatch_width == 16) 358 fail("16-wide explicit accumulator operands unsupported\n"); 359 360 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 361 362 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 363 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 364 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 365 } else { 366 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 367 } 368 break; 369 case ir_binop_div: 370 if (intel->gen >= 7 && c->dispatch_width == 16) 371 fail("16-wide INTDIV unsupported\n"); 372 373 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */ 374 assert(ir->type->is_integer()); 375 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]); 376 break; 377 case ir_binop_mod: 378 if (intel->gen >= 7 && c->dispatch_width == 16) 379 fail("16-wide INTDIV unsupported\n"); 380 381 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */ 382 assert(ir->type->is_integer()); 383 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]); 384 break; 385 386 case ir_binop_less: 387 case ir_binop_greater: 388 case ir_binop_lequal: 389 case ir_binop_gequal: 390 case ir_binop_equal: 391 case ir_binop_all_equal: 392 case ir_binop_nequal: 393 case ir_binop_any_nequal: 394 temp = this->result; 395 /* original gen4 does implicit conversion before comparison. */ 396 if (intel->gen < 5) 397 temp.type = op[0].type; 398 399 resolve_ud_negate(&op[0]); 400 resolve_ud_negate(&op[1]); 401 402 resolve_bool_comparison(ir->operands[0], &op[0]); 403 resolve_bool_comparison(ir->operands[1], &op[1]); 404 405 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 406 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 407 break; 408 409 case ir_binop_logic_xor: 410 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 411 break; 412 413 case ir_binop_logic_or: 414 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 415 break; 416 417 case ir_binop_logic_and: 418 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 419 break; 420 421 case ir_binop_dot: 422 case ir_unop_any: 423 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 424 break; 425 426 case ir_unop_noise: 427 assert(!"not reached: should be handled by lower_noise"); 428 break; 429 430 case ir_quadop_vector: 431 assert(!"not reached: should be handled by lower_quadop_vector"); 432 break; 433 434 case ir_unop_sqrt: 435 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 436 break; 437 438 case ir_unop_rsq: 439 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 440 break; 441 442 case ir_unop_i2u: 443 op[0].type = BRW_REGISTER_TYPE_UD; 444 this->result = op[0]; 445 break; 446 case ir_unop_u2i: 447 op[0].type = BRW_REGISTER_TYPE_D; 448 this->result = op[0]; 449 break; 450 case ir_unop_i2f: 451 case ir_unop_u2f: 452 case ir_unop_f2i: 453 emit(BRW_OPCODE_MOV, this->result, op[0]); 454 break; 455 456 case ir_unop_b2i: 457 inst = emit(BRW_OPCODE_AND, this->result, op[0], fs_reg(1)); 458 break; 459 case ir_unop_b2f: 460 temp = fs_reg(this, glsl_type::int_type); 461 emit(BRW_OPCODE_AND, temp, op[0], fs_reg(1)); 462 emit(BRW_OPCODE_MOV, this->result, temp); 463 break; 464 465 case ir_unop_f2b: 466 case ir_unop_i2b: 467 temp = this->result; 468 /* original gen4 does implicit conversion before comparison. */ 469 if (intel->gen < 5) 470 temp.type = op[0].type; 471 472 resolve_ud_negate(&op[0]); 473 474 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 475 inst->conditional_mod = BRW_CONDITIONAL_NZ; 476 break; 477 478 case ir_unop_trunc: 479 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 480 break; 481 case ir_unop_ceil: 482 op[0].negate = !op[0].negate; 483 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 484 this->result.negate = true; 485 break; 486 case ir_unop_floor: 487 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 488 break; 489 case ir_unop_fract: 490 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 491 break; 492 case ir_unop_round_even: 493 emit(BRW_OPCODE_RNDE, this->result, op[0]); 494 break; 495 496 case ir_binop_min: 497 resolve_ud_negate(&op[0]); 498 resolve_ud_negate(&op[1]); 499 500 if (intel->gen >= 6) { 501 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 502 inst->conditional_mod = BRW_CONDITIONAL_L; 503 } else { 504 /* Unalias the destination */ 505 this->result = fs_reg(this, ir->type); 506 507 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 508 inst->conditional_mod = BRW_CONDITIONAL_L; 509 510 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 511 inst->predicated = true; 512 } 513 break; 514 case ir_binop_max: 515 resolve_ud_negate(&op[0]); 516 resolve_ud_negate(&op[1]); 517 518 if (intel->gen >= 6) { 519 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 520 inst->conditional_mod = BRW_CONDITIONAL_GE; 521 } else { 522 /* Unalias the destination */ 523 this->result = fs_reg(this, ir->type); 524 525 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 526 inst->conditional_mod = BRW_CONDITIONAL_G; 527 528 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 529 inst->predicated = true; 530 } 531 break; 532 533 case ir_binop_pow: 534 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 535 break; 536 537 case ir_unop_bit_not: 538 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 539 break; 540 case ir_binop_bit_and: 541 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 542 break; 543 case ir_binop_bit_xor: 544 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 545 break; 546 case ir_binop_bit_or: 547 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 548 break; 549 550 case ir_binop_lshift: 551 inst = emit(BRW_OPCODE_SHL, this->result, op[0], op[1]); 552 break; 553 554 case ir_binop_rshift: 555 if (ir->type->base_type == GLSL_TYPE_INT) 556 inst = emit(BRW_OPCODE_ASR, this->result, op[0], op[1]); 557 else 558 inst = emit(BRW_OPCODE_SHR, this->result, op[0], op[1]); 559 break; 560 } 561} 562 563void 564fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 565 const glsl_type *type, bool predicated) 566{ 567 switch (type->base_type) { 568 case GLSL_TYPE_FLOAT: 569 case GLSL_TYPE_UINT: 570 case GLSL_TYPE_INT: 571 case GLSL_TYPE_BOOL: 572 for (unsigned int i = 0; i < type->components(); i++) { 573 l.type = brw_type_for_base_type(type); 574 r.type = brw_type_for_base_type(type); 575 576 if (predicated || !l.equals(r)) { 577 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 578 inst->predicated = predicated; 579 } 580 581 l.reg_offset++; 582 r.reg_offset++; 583 } 584 break; 585 case GLSL_TYPE_ARRAY: 586 for (unsigned int i = 0; i < type->length; i++) { 587 emit_assignment_writes(l, r, type->fields.array, predicated); 588 } 589 break; 590 591 case GLSL_TYPE_STRUCT: 592 for (unsigned int i = 0; i < type->length; i++) { 593 emit_assignment_writes(l, r, type->fields.structure[i].type, 594 predicated); 595 } 596 break; 597 598 case GLSL_TYPE_SAMPLER: 599 break; 600 601 default: 602 assert(!"not reached"); 603 break; 604 } 605} 606 607/* If the RHS processing resulted in an instruction generating a 608 * temporary value, and it would be easy to rewrite the instruction to 609 * generate its result right into the LHS instead, do so. This ends 610 * up reliably removing instructions where it can be tricky to do so 611 * later without real UD chain information. 612 */ 613bool 614fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 615 fs_reg dst, 616 fs_reg src, 617 fs_inst *pre_rhs_inst, 618 fs_inst *last_rhs_inst) 619{ 620 /* Only attempt if we're doing a direct assignment. */ 621 if (ir->condition || 622 !(ir->lhs->type->is_scalar() || 623 (ir->lhs->type->is_vector() && 624 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 625 return false; 626 627 /* Make sure the last instruction generated our source reg. */ 628 fs_inst *modify = get_instruction_generating_reg(pre_rhs_inst, 629 last_rhs_inst, 630 src); 631 if (!modify) 632 return false; 633 634 /* If last_rhs_inst wrote a different number of components than our LHS, 635 * we can't safely rewrite it. 636 */ 637 if (ir->lhs->type->vector_elements != modify->regs_written()) 638 return false; 639 640 /* Success! Rewrite the instruction. */ 641 modify->dst = dst; 642 643 return true; 644} 645 646void 647fs_visitor::visit(ir_assignment *ir) 648{ 649 fs_reg l, r; 650 fs_inst *inst; 651 652 /* FINISHME: arrays on the lhs */ 653 ir->lhs->accept(this); 654 l = this->result; 655 656 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 657 658 ir->rhs->accept(this); 659 r = this->result; 660 661 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 662 663 assert(l.file != BAD_FILE); 664 assert(r.file != BAD_FILE); 665 666 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 667 return; 668 669 if (ir->condition) { 670 emit_bool_to_cond_code(ir->condition); 671 } 672 673 if (ir->lhs->type->is_scalar() || 674 ir->lhs->type->is_vector()) { 675 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 676 if (ir->write_mask & (1 << i)) { 677 inst = emit(BRW_OPCODE_MOV, l, r); 678 if (ir->condition) 679 inst->predicated = true; 680 r.reg_offset++; 681 } 682 l.reg_offset++; 683 } 684 } else { 685 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 686 } 687} 688 689fs_inst * 690fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 691 int sampler) 692{ 693 int mlen; 694 int base_mrf = 1; 695 bool simd16 = false; 696 fs_reg orig_dst; 697 698 /* g0 header. */ 699 mlen = 1; 700 701 if (ir->shadow_comparitor && ir->op != ir_txd) { 702 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 703 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 704 coordinate.reg_offset++; 705 } 706 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 707 mlen += 3; 708 709 if (ir->op == ir_tex) { 710 /* There's no plain shadow compare message, so we use shadow 711 * compare with a bias of 0.0. 712 */ 713 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 714 mlen++; 715 } else if (ir->op == ir_txb) { 716 ir->lod_info.bias->accept(this); 717 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 718 mlen++; 719 } else { 720 assert(ir->op == ir_txl); 721 ir->lod_info.lod->accept(this); 722 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 723 mlen++; 724 } 725 726 ir->shadow_comparitor->accept(this); 727 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 728 mlen++; 729 } else if (ir->op == ir_tex) { 730 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 731 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 732 coordinate.reg_offset++; 733 } 734 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 735 mlen += 3; 736 } else if (ir->op == ir_txd) { 737 ir->lod_info.grad.dPdx->accept(this); 738 fs_reg dPdx = this->result; 739 740 ir->lod_info.grad.dPdy->accept(this); 741 fs_reg dPdy = this->result; 742 743 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 744 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 745 coordinate.reg_offset++; 746 } 747 /* the slots for u and v are always present, but r is optional */ 748 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 749 750 /* P = u, v, r 751 * dPdx = dudx, dvdx, drdx 752 * dPdy = dudy, dvdy, drdy 753 * 754 * 1-arg: Does not exist. 755 * 756 * 2-arg: dudx dvdx dudy dvdy 757 * dPdx.x dPdx.y dPdy.x dPdy.y 758 * m4 m5 m6 m7 759 * 760 * 3-arg: dudx dvdx drdx dudy dvdy drdy 761 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 762 * m5 m6 m7 m8 m9 m10 763 */ 764 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 765 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 766 dPdx.reg_offset++; 767 } 768 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 769 770 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 771 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 772 dPdy.reg_offset++; 773 } 774 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 775 } else if (ir->op == ir_txs) { 776 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 777 simd16 = true; 778 ir->lod_info.lod->accept(this); 779 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 780 mlen += 2; 781 } else { 782 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 783 * instructions. We'll need to do SIMD16 here. 784 */ 785 simd16 = true; 786 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf); 787 788 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 789 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type), 790 coordinate); 791 coordinate.reg_offset++; 792 } 793 794 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to 795 * be necessary for TXF (ld), but seems wise to do for all messages. 796 */ 797 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) { 798 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)); 799 } 800 801 /* lod/bias appears after u/v/r. */ 802 mlen += 6; 803 804 if (ir->op == ir_txb) { 805 ir->lod_info.bias->accept(this); 806 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 807 mlen++; 808 } else { 809 ir->lod_info.lod->accept(this); 810 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, this->result.type), 811 this->result); 812 mlen++; 813 } 814 815 /* The unused upper half. */ 816 mlen++; 817 } 818 819 if (simd16) { 820 /* Now, since we're doing simd16, the return is 2 interleaved 821 * vec4s where the odd-indexed ones are junk. We'll need to move 822 * this weirdness around to the expected layout. 823 */ 824 orig_dst = dst; 825 const glsl_type *vec_type = 826 glsl_type::get_instance(ir->type->base_type, 4, 1); 827 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 828 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 829 : BRW_REGISTER_TYPE_F; 830 } 831 832 fs_inst *inst = NULL; 833 switch (ir->op) { 834 case ir_tex: 835 inst = emit(SHADER_OPCODE_TEX, dst); 836 break; 837 case ir_txb: 838 inst = emit(FS_OPCODE_TXB, dst); 839 break; 840 case ir_txl: 841 inst = emit(SHADER_OPCODE_TXL, dst); 842 break; 843 case ir_txd: 844 inst = emit(SHADER_OPCODE_TXD, dst); 845 break; 846 case ir_txs: 847 inst = emit(SHADER_OPCODE_TXS, dst); 848 break; 849 case ir_txf: 850 inst = emit(SHADER_OPCODE_TXF, dst); 851 break; 852 } 853 inst->base_mrf = base_mrf; 854 inst->mlen = mlen; 855 inst->header_present = true; 856 857 if (simd16) { 858 for (int i = 0; i < 4; i++) { 859 emit(BRW_OPCODE_MOV, orig_dst, dst); 860 orig_dst.reg_offset++; 861 dst.reg_offset += 2; 862 } 863 } 864 865 return inst; 866} 867 868/* gen5's sampler has slots for u, v, r, array index, then optional 869 * parameters like shadow comparitor or LOD bias. If optional 870 * parameters aren't present, those base slots are optional and don't 871 * need to be included in the message. 872 * 873 * We don't fill in the unnecessary slots regardless, which may look 874 * surprising in the disassembly. 875 */ 876fs_inst * 877fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 878 int sampler) 879{ 880 int mlen = 0; 881 int base_mrf = 2; 882 int reg_width = c->dispatch_width / 8; 883 bool header_present = false; 884 const int vector_elements = 885 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 886 887 if (ir->offset) { 888 /* The offsets set up by the ir_texture visitor are in the 889 * m1 header, so we can't go headerless. 890 */ 891 header_present = true; 892 mlen++; 893 base_mrf--; 894 } 895 896 for (int i = 0; i < vector_elements; i++) { 897 emit(BRW_OPCODE_MOV, 898 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type), 899 coordinate); 900 coordinate.reg_offset++; 901 } 902 mlen += vector_elements * reg_width; 903 904 if (ir->shadow_comparitor && ir->op != ir_txd) { 905 mlen = MAX2(mlen, header_present + 4 * reg_width); 906 907 ir->shadow_comparitor->accept(this); 908 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 909 mlen += reg_width; 910 } 911 912 fs_inst *inst = NULL; 913 switch (ir->op) { 914 case ir_tex: 915 inst = emit(SHADER_OPCODE_TEX, dst); 916 break; 917 case ir_txb: 918 ir->lod_info.bias->accept(this); 919 mlen = MAX2(mlen, header_present + 4 * reg_width); 920 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 921 mlen += reg_width; 922 923 inst = emit(FS_OPCODE_TXB, dst); 924 925 break; 926 case ir_txl: 927 ir->lod_info.lod->accept(this); 928 mlen = MAX2(mlen, header_present + 4 * reg_width); 929 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 930 mlen += reg_width; 931 932 inst = emit(SHADER_OPCODE_TXL, dst); 933 break; 934 case ir_txd: { 935 ir->lod_info.grad.dPdx->accept(this); 936 fs_reg dPdx = this->result; 937 938 ir->lod_info.grad.dPdy->accept(this); 939 fs_reg dPdy = this->result; 940 941 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 942 943 /** 944 * P = u, v, r 945 * dPdx = dudx, dvdx, drdx 946 * dPdy = dudy, dvdy, drdy 947 * 948 * Load up these values: 949 * - dudx dudy dvdx dvdy drdx drdy 950 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 951 */ 952 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 953 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 954 dPdx.reg_offset++; 955 mlen += reg_width; 956 957 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 958 dPdy.reg_offset++; 959 mlen += reg_width; 960 } 961 962 inst = emit(SHADER_OPCODE_TXD, dst); 963 break; 964 } 965 case ir_txs: 966 ir->lod_info.lod->accept(this); 967 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 968 mlen += reg_width; 969 inst = emit(SHADER_OPCODE_TXS, dst); 970 break; 971 case ir_txf: 972 mlen = header_present + 4 * reg_width; 973 974 ir->lod_info.lod->accept(this); 975 emit(BRW_OPCODE_MOV, 976 fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 977 this->result); 978 inst = emit(SHADER_OPCODE_TXF, dst); 979 break; 980 } 981 inst->base_mrf = base_mrf; 982 inst->mlen = mlen; 983 inst->header_present = header_present; 984 985 if (mlen > 11) { 986 fail("Message length >11 disallowed by hardware\n"); 987 } 988 989 return inst; 990} 991 992fs_inst * 993fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 994 int sampler) 995{ 996 int mlen = 0; 997 int base_mrf = 2; 998 int reg_width = c->dispatch_width / 8; 999 bool header_present = false; 1000 int offsets[3]; 1001 1002 if (ir->offset && ir->op != ir_txf) { 1003 /* The offsets set up by the ir_texture visitor are in the 1004 * m1 header, so we can't go headerless. 1005 */ 1006 header_present = true; 1007 mlen++; 1008 base_mrf--; 1009 } 1010 1011 if (ir->shadow_comparitor && ir->op != ir_txd) { 1012 ir->shadow_comparitor->accept(this); 1013 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 1014 mlen += reg_width; 1015 } 1016 1017 /* Set up the LOD info */ 1018 switch (ir->op) { 1019 case ir_tex: 1020 break; 1021 case ir_txb: 1022 ir->lod_info.bias->accept(this); 1023 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 1024 mlen += reg_width; 1025 break; 1026 case ir_txl: 1027 ir->lod_info.lod->accept(this); 1028 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 1029 mlen += reg_width; 1030 break; 1031 case ir_txd: { 1032 if (c->dispatch_width == 16) 1033 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 1034 1035 ir->lod_info.grad.dPdx->accept(this); 1036 fs_reg dPdx = this->result; 1037 1038 ir->lod_info.grad.dPdy->accept(this); 1039 fs_reg dPdy = this->result; 1040 1041 /* Load dPdx and the coordinate together: 1042 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 1043 */ 1044 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 1045 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate); 1046 coordinate.reg_offset++; 1047 mlen += reg_width; 1048 1049 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 1050 dPdx.reg_offset++; 1051 mlen += reg_width; 1052 1053 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 1054 dPdy.reg_offset++; 1055 mlen += reg_width; 1056 } 1057 break; 1058 } 1059 case ir_txs: 1060 ir->lod_info.lod->accept(this); 1061 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 1062 mlen += reg_width; 1063 break; 1064 case ir_txf: 1065 /* It appears that the ld instruction used for txf does its 1066 * address bounds check before adding in the offset. To work 1067 * around this, just add the integer offset to the integer texel 1068 * coordinate, and don't put the offset in the header. 1069 */ 1070 if (ir->offset) { 1071 ir_constant *offset = ir->offset->as_constant(); 1072 offsets[0] = offset->value.i[0]; 1073 offsets[1] = offset->value.i[1]; 1074 offsets[2] = offset->value.i[2]; 1075 } else { 1076 memset(offsets, 0, sizeof(offsets)); 1077 } 1078 1079 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */ 1080 emit(BRW_OPCODE_ADD, 1081 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate, offsets[0]); 1082 coordinate.reg_offset++; 1083 mlen += reg_width; 1084 1085 ir->lod_info.lod->accept(this); 1086 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result); 1087 mlen += reg_width; 1088 1089 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { 1090 emit(BRW_OPCODE_ADD, 1091 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate, offsets[i]); 1092 coordinate.reg_offset++; 1093 mlen += reg_width; 1094 } 1095 break; 1096 } 1097 1098 /* Set up the coordinate (except for cases where it was done above) */ 1099 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { 1100 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 1101 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate); 1102 coordinate.reg_offset++; 1103 mlen += reg_width; 1104 } 1105 } 1106 1107 /* Generate the SEND */ 1108 fs_inst *inst = NULL; 1109 switch (ir->op) { 1110 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break; 1111 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 1112 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break; 1113 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break; 1114 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break; 1115 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break; 1116 } 1117 inst->base_mrf = base_mrf; 1118 inst->mlen = mlen; 1119 inst->header_present = header_present; 1120 1121 if (mlen > 11) { 1122 fail("Message length >11 disallowed by hardware\n"); 1123 } 1124 1125 return inst; 1126} 1127 1128void 1129fs_visitor::visit(ir_texture *ir) 1130{ 1131 fs_inst *inst = NULL; 1132 1133 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1134 sampler = fp->Base.SamplerUnits[sampler]; 1135 1136 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1137 * for textureGrad/TXD need to be emulated with instructions. 1138 */ 1139 bool hw_compare_supported = ir->op != ir_txd; 1140 if (ir->shadow_comparitor && !hw_compare_supported) { 1141 assert(c->key.tex.compare_funcs[sampler] != GL_NONE); 1142 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1143 if (c->key.tex.compare_funcs[sampler] == GL_ALWAYS) 1144 return swizzle_result(ir, fs_reg(1.0f), sampler); 1145 else if (c->key.tex.compare_funcs[sampler] == GL_NEVER) 1146 return swizzle_result(ir, fs_reg(0.0f), sampler); 1147 } 1148 1149 if (ir->coordinate) 1150 ir->coordinate->accept(this); 1151 fs_reg coordinate = this->result; 1152 1153 if (ir->offset != NULL && !(intel->gen == 7 && ir->op == ir_txf)) { 1154 uint32_t offset_bits = brw_texture_offset(ir->offset->as_constant()); 1155 1156 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1157 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1158 fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD))); 1159 1160 /* Then set the offset bits in DWord 2 of the message header. */ 1161 emit(BRW_OPCODE_MOV, 1162 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1163 BRW_REGISTER_TYPE_UD)), 1164 fs_reg(brw_imm_uw(offset_bits))); 1165 } 1166 1167 /* Should be lowered by do_lower_texture_projection */ 1168 assert(!ir->projector); 1169 1170 bool needs_gl_clamp = true; 1171 1172 fs_reg scale_x, scale_y; 1173 1174 /* The 965 requires the EU to do the normalization of GL rectangle 1175 * texture coordinates. We use the program parameter state 1176 * tracking to get the scaling factor. 1177 */ 1178 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT && 1179 (intel->gen < 6 || 1180 (intel->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) || 1181 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) { 1182 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1183 int tokens[STATE_LENGTH] = { 1184 STATE_INTERNAL, 1185 STATE_TEXRECT_SCALE, 1186 sampler, 1187 0, 1188 0 1189 }; 1190 1191 if (c->dispatch_width == 16) { 1192 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1193 this->result = fs_reg(this, ir->type); 1194 return; 1195 } 1196 1197 c->prog_data.param_convert[c->prog_data.nr_params] = 1198 PARAM_NO_CONVERT; 1199 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1200 PARAM_NO_CONVERT; 1201 1202 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1203 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1204 1205 GLuint index = _mesa_add_state_reference(params, 1206 (gl_state_index *)tokens); 1207 1208 this->param_index[c->prog_data.nr_params] = index; 1209 this->param_offset[c->prog_data.nr_params] = 0; 1210 c->prog_data.nr_params++; 1211 this->param_index[c->prog_data.nr_params] = index; 1212 this->param_offset[c->prog_data.nr_params] = 1; 1213 c->prog_data.nr_params++; 1214 } 1215 1216 /* The 965 requires the EU to do the normalization of GL rectangle 1217 * texture coordinates. We use the program parameter state 1218 * tracking to get the scaling factor. 1219 */ 1220 if (intel->gen < 6 && 1221 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1222 fs_reg dst = fs_reg(this, ir->coordinate->type); 1223 fs_reg src = coordinate; 1224 coordinate = dst; 1225 1226 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1227 dst.reg_offset++; 1228 src.reg_offset++; 1229 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1230 } else if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1231 /* On gen6+, the sampler handles the rectangle coordinates 1232 * natively, without needing rescaling. But that means we have 1233 * to do GL_CLAMP clamping at the [0, width], [0, height] scale, 1234 * not [0, 1] like the default case below. 1235 */ 1236 needs_gl_clamp = false; 1237 1238 for (int i = 0; i < 2; i++) { 1239 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) { 1240 fs_reg chan = coordinate; 1241 chan.reg_offset += i; 1242 1243 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0)); 1244 inst->conditional_mod = BRW_CONDITIONAL_G; 1245 1246 /* Our parameter comes in as 1.0/width or 1.0/height, 1247 * because that's what people normally want for doing 1248 * texture rectangle handling. We need width or height 1249 * for clamping, but we don't care enough to make a new 1250 * parameter type, so just invert back. 1251 */ 1252 fs_reg limit = fs_reg(this, glsl_type::float_type); 1253 emit(BRW_OPCODE_MOV, limit, i == 0 ? scale_x : scale_y); 1254 emit(SHADER_OPCODE_RCP, limit, limit); 1255 1256 inst = emit(BRW_OPCODE_SEL, chan, chan, limit); 1257 inst->conditional_mod = BRW_CONDITIONAL_L; 1258 } 1259 } 1260 } 1261 1262 if (ir->coordinate && needs_gl_clamp) { 1263 for (unsigned int i = 0; 1264 i < MIN2(ir->coordinate->type->vector_elements, 3); i++) { 1265 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) { 1266 fs_reg chan = coordinate; 1267 chan.reg_offset += i; 1268 1269 fs_inst *inst = emit(BRW_OPCODE_MOV, chan, chan); 1270 inst->saturate = true; 1271 } 1272 } 1273 } 1274 1275 /* Writemasking doesn't eliminate channels on SIMD8 texture 1276 * samples, so don't worry about them. 1277 */ 1278 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1279 1280 if (intel->gen >= 7) { 1281 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1282 } else if (intel->gen >= 5) { 1283 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1284 } else { 1285 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1286 } 1287 1288 /* If there's an offset, we already set up m1. To avoid the implied move, 1289 * use the null register. Otherwise, we want an implied move from g0. 1290 */ 1291 if (ir->offset != NULL || !inst->header_present) 1292 inst->src[0] = reg_undef; 1293 else 1294 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1295 1296 inst->sampler = sampler; 1297 1298 if (ir->shadow_comparitor) { 1299 if (hw_compare_supported) { 1300 inst->shadow_compare = true; 1301 } else { 1302 ir->shadow_comparitor->accept(this); 1303 fs_reg ref = this->result; 1304 1305 fs_reg value = dst; 1306 dst = fs_reg(this, glsl_type::vec4_type); 1307 1308 /* FINISHME: This needs to be done pre-filtering. */ 1309 1310 uint32_t conditional = 0; 1311 switch (c->key.tex.compare_funcs[sampler]) { 1312 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1313 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1314 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1315 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1316 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1317 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1318 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1319 default: assert(!"Should not get here: bad shadow compare function"); 1320 } 1321 1322 /* Use conditional moves to load 0 or 1 as the result */ 1323 this->current_annotation = "manual shadow comparison"; 1324 for (int i = 0; i < 4; i++) { 1325 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1326 1327 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1328 inst->conditional_mod = conditional; 1329 1330 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1331 inst->predicated = true; 1332 1333 dst.reg_offset++; 1334 value.reg_offset++; 1335 } 1336 dst.reg_offset = 0; 1337 } 1338 } 1339 1340 swizzle_result(ir, dst, sampler); 1341} 1342 1343/** 1344 * Swizzle the result of a texture result. This is necessary for 1345 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1346 */ 1347void 1348fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1349{ 1350 this->result = orig_val; 1351 1352 if (ir->op == ir_txs) 1353 return; 1354 1355 if (ir->type == glsl_type::float_type) { 1356 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1357 assert(ir->sampler->type->sampler_shadow); 1358 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) { 1359 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1360 1361 for (int i = 0; i < 4; i++) { 1362 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i); 1363 fs_reg l = swizzled_result; 1364 l.reg_offset += i; 1365 1366 if (swiz == SWIZZLE_ZERO) { 1367 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1368 } else if (swiz == SWIZZLE_ONE) { 1369 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1370 } else { 1371 fs_reg r = orig_val; 1372 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i); 1373 emit(BRW_OPCODE_MOV, l, r); 1374 } 1375 } 1376 this->result = swizzled_result; 1377 } 1378} 1379 1380void 1381fs_visitor::visit(ir_swizzle *ir) 1382{ 1383 ir->val->accept(this); 1384 fs_reg val = this->result; 1385 1386 if (ir->type->vector_elements == 1) { 1387 this->result.reg_offset += ir->mask.x; 1388 return; 1389 } 1390 1391 fs_reg result = fs_reg(this, ir->type); 1392 this->result = result; 1393 1394 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1395 fs_reg channel = val; 1396 int swiz = 0; 1397 1398 switch (i) { 1399 case 0: 1400 swiz = ir->mask.x; 1401 break; 1402 case 1: 1403 swiz = ir->mask.y; 1404 break; 1405 case 2: 1406 swiz = ir->mask.z; 1407 break; 1408 case 3: 1409 swiz = ir->mask.w; 1410 break; 1411 } 1412 1413 channel.reg_offset += swiz; 1414 emit(BRW_OPCODE_MOV, result, channel); 1415 result.reg_offset++; 1416 } 1417} 1418 1419void 1420fs_visitor::visit(ir_discard *ir) 1421{ 1422 assert(ir->condition == NULL); /* FINISHME */ 1423 1424 emit(FS_OPCODE_DISCARD); 1425 kill_emitted = true; 1426} 1427 1428void 1429fs_visitor::visit(ir_constant *ir) 1430{ 1431 /* Set this->result to reg at the bottom of the function because some code 1432 * paths will cause this visitor to be applied to other fields. This will 1433 * cause the value stored in this->result to be modified. 1434 * 1435 * Make reg constant so that it doesn't get accidentally modified along the 1436 * way. Yes, I actually had this problem. :( 1437 */ 1438 const fs_reg reg(this, ir->type); 1439 fs_reg dst_reg = reg; 1440 1441 if (ir->type->is_array()) { 1442 const unsigned size = type_size(ir->type->fields.array); 1443 1444 for (unsigned i = 0; i < ir->type->length; i++) { 1445 ir->array_elements[i]->accept(this); 1446 fs_reg src_reg = this->result; 1447 1448 dst_reg.type = src_reg.type; 1449 for (unsigned j = 0; j < size; j++) { 1450 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1451 src_reg.reg_offset++; 1452 dst_reg.reg_offset++; 1453 } 1454 } 1455 } else if (ir->type->is_record()) { 1456 foreach_list(node, &ir->components) { 1457 ir_constant *const field = (ir_constant *) node; 1458 const unsigned size = type_size(field->type); 1459 1460 field->accept(this); 1461 fs_reg src_reg = this->result; 1462 1463 dst_reg.type = src_reg.type; 1464 for (unsigned j = 0; j < size; j++) { 1465 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1466 src_reg.reg_offset++; 1467 dst_reg.reg_offset++; 1468 } 1469 } 1470 } else { 1471 const unsigned size = type_size(ir->type); 1472 1473 for (unsigned i = 0; i < size; i++) { 1474 switch (ir->type->base_type) { 1475 case GLSL_TYPE_FLOAT: 1476 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1477 break; 1478 case GLSL_TYPE_UINT: 1479 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1480 break; 1481 case GLSL_TYPE_INT: 1482 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1483 break; 1484 case GLSL_TYPE_BOOL: 1485 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1486 break; 1487 default: 1488 assert(!"Non-float/uint/int/bool constant"); 1489 } 1490 dst_reg.reg_offset++; 1491 } 1492 } 1493 1494 this->result = reg; 1495} 1496 1497void 1498fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1499{ 1500 ir_expression *expr = ir->as_expression(); 1501 1502 if (expr) { 1503 fs_reg op[2]; 1504 fs_inst *inst; 1505 1506 assert(expr->get_num_operands() <= 2); 1507 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1508 assert(expr->operands[i]->type->is_scalar()); 1509 1510 expr->operands[i]->accept(this); 1511 op[i] = this->result; 1512 1513 resolve_ud_negate(&op[i]); 1514 } 1515 1516 switch (expr->operation) { 1517 case ir_unop_logic_not: 1518 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1519 inst->conditional_mod = BRW_CONDITIONAL_Z; 1520 break; 1521 1522 case ir_binop_logic_xor: 1523 case ir_binop_logic_or: 1524 case ir_binop_logic_and: 1525 goto out; 1526 1527 case ir_unop_f2b: 1528 if (intel->gen >= 6) { 1529 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1530 } else { 1531 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1532 } 1533 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1534 break; 1535 1536 case ir_unop_i2b: 1537 if (intel->gen >= 6) { 1538 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1539 } else { 1540 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1541 } 1542 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1543 break; 1544 1545 case ir_binop_greater: 1546 case ir_binop_gequal: 1547 case ir_binop_less: 1548 case ir_binop_lequal: 1549 case ir_binop_equal: 1550 case ir_binop_all_equal: 1551 case ir_binop_nequal: 1552 case ir_binop_any_nequal: 1553 resolve_bool_comparison(expr->operands[0], &op[0]); 1554 resolve_bool_comparison(expr->operands[1], &op[1]); 1555 1556 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1557 inst->conditional_mod = 1558 brw_conditional_for_comparison(expr->operation); 1559 break; 1560 1561 default: 1562 assert(!"not reached"); 1563 fail("bad cond code\n"); 1564 break; 1565 } 1566 return; 1567 } 1568 1569out: 1570 ir->accept(this); 1571 1572 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1573 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1574} 1575 1576/** 1577 * Emit a gen6 IF statement with the comparison folded into the IF 1578 * instruction. 1579 */ 1580void 1581fs_visitor::emit_if_gen6(ir_if *ir) 1582{ 1583 ir_expression *expr = ir->condition->as_expression(); 1584 1585 if (expr) { 1586 fs_reg op[2]; 1587 fs_inst *inst; 1588 fs_reg temp; 1589 1590 assert(expr->get_num_operands() <= 2); 1591 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1592 assert(expr->operands[i]->type->is_scalar()); 1593 1594 expr->operands[i]->accept(this); 1595 op[i] = this->result; 1596 } 1597 1598 switch (expr->operation) { 1599 case ir_unop_logic_not: 1600 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1601 inst->conditional_mod = BRW_CONDITIONAL_Z; 1602 return; 1603 1604 case ir_binop_logic_xor: 1605 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1606 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1607 return; 1608 1609 case ir_binop_logic_or: 1610 temp = fs_reg(this, glsl_type::bool_type); 1611 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1612 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1613 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1614 return; 1615 1616 case ir_binop_logic_and: 1617 temp = fs_reg(this, glsl_type::bool_type); 1618 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1619 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1620 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1621 return; 1622 1623 case ir_unop_f2b: 1624 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1625 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1626 return; 1627 1628 case ir_unop_i2b: 1629 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1630 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1631 return; 1632 1633 case ir_binop_greater: 1634 case ir_binop_gequal: 1635 case ir_binop_less: 1636 case ir_binop_lequal: 1637 case ir_binop_equal: 1638 case ir_binop_all_equal: 1639 case ir_binop_nequal: 1640 case ir_binop_any_nequal: 1641 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1642 inst->conditional_mod = 1643 brw_conditional_for_comparison(expr->operation); 1644 return; 1645 default: 1646 assert(!"not reached"); 1647 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1648 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1649 fail("bad condition\n"); 1650 return; 1651 } 1652 return; 1653 } 1654 1655 ir->condition->accept(this); 1656 1657 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1658 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1659} 1660 1661void 1662fs_visitor::visit(ir_if *ir) 1663{ 1664 fs_inst *inst; 1665 1666 if (intel->gen < 6 && c->dispatch_width == 16) { 1667 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1668 } 1669 1670 /* Don't point the annotation at the if statement, because then it plus 1671 * the then and else blocks get printed. 1672 */ 1673 this->base_ir = ir->condition; 1674 1675 if (intel->gen == 6) { 1676 emit_if_gen6(ir); 1677 } else { 1678 emit_bool_to_cond_code(ir->condition); 1679 1680 inst = emit(BRW_OPCODE_IF); 1681 inst->predicated = true; 1682 } 1683 1684 foreach_list(node, &ir->then_instructions) { 1685 ir_instruction *ir = (ir_instruction *)node; 1686 this->base_ir = ir; 1687 1688 ir->accept(this); 1689 } 1690 1691 if (!ir->else_instructions.is_empty()) { 1692 emit(BRW_OPCODE_ELSE); 1693 1694 foreach_list(node, &ir->else_instructions) { 1695 ir_instruction *ir = (ir_instruction *)node; 1696 this->base_ir = ir; 1697 1698 ir->accept(this); 1699 } 1700 } 1701 1702 emit(BRW_OPCODE_ENDIF); 1703} 1704 1705void 1706fs_visitor::visit(ir_loop *ir) 1707{ 1708 fs_reg counter = reg_undef; 1709 1710 if (intel->gen < 6 && c->dispatch_width == 16) { 1711 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1712 } 1713 1714 if (ir->counter) { 1715 this->base_ir = ir->counter; 1716 ir->counter->accept(this); 1717 counter = *(variable_storage(ir->counter)); 1718 1719 if (ir->from) { 1720 this->base_ir = ir->from; 1721 ir->from->accept(this); 1722 1723 emit(BRW_OPCODE_MOV, counter, this->result); 1724 } 1725 } 1726 1727 this->base_ir = NULL; 1728 emit(BRW_OPCODE_DO); 1729 1730 if (ir->to) { 1731 this->base_ir = ir->to; 1732 ir->to->accept(this); 1733 1734 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1735 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1736 1737 inst = emit(BRW_OPCODE_BREAK); 1738 inst->predicated = true; 1739 } 1740 1741 foreach_list(node, &ir->body_instructions) { 1742 ir_instruction *ir = (ir_instruction *)node; 1743 1744 this->base_ir = ir; 1745 ir->accept(this); 1746 } 1747 1748 if (ir->increment) { 1749 this->base_ir = ir->increment; 1750 ir->increment->accept(this); 1751 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1752 } 1753 1754 this->base_ir = NULL; 1755 emit(BRW_OPCODE_WHILE); 1756} 1757 1758void 1759fs_visitor::visit(ir_loop_jump *ir) 1760{ 1761 switch (ir->mode) { 1762 case ir_loop_jump::jump_break: 1763 emit(BRW_OPCODE_BREAK); 1764 break; 1765 case ir_loop_jump::jump_continue: 1766 emit(BRW_OPCODE_CONTINUE); 1767 break; 1768 } 1769} 1770 1771void 1772fs_visitor::visit(ir_call *ir) 1773{ 1774 assert(!"FINISHME"); 1775} 1776 1777void 1778fs_visitor::visit(ir_return *ir) 1779{ 1780 assert(!"FINISHME"); 1781} 1782 1783void 1784fs_visitor::visit(ir_function *ir) 1785{ 1786 /* Ignore function bodies other than main() -- we shouldn't see calls to 1787 * them since they should all be inlined before we get to ir_to_mesa. 1788 */ 1789 if (strcmp(ir->name, "main") == 0) { 1790 const ir_function_signature *sig; 1791 exec_list empty; 1792 1793 sig = ir->matching_signature(&empty); 1794 1795 assert(sig); 1796 1797 foreach_list(node, &sig->body) { 1798 ir_instruction *ir = (ir_instruction *)node; 1799 this->base_ir = ir; 1800 1801 ir->accept(this); 1802 } 1803 } 1804} 1805 1806void 1807fs_visitor::visit(ir_function_signature *ir) 1808{ 1809 assert(!"not reached"); 1810 (void)ir; 1811} 1812 1813fs_inst * 1814fs_visitor::emit(fs_inst inst) 1815{ 1816 fs_inst *list_inst = new(mem_ctx) fs_inst; 1817 *list_inst = inst; 1818 1819 if (force_uncompressed_stack > 0) 1820 list_inst->force_uncompressed = true; 1821 else if (force_sechalf_stack > 0) 1822 list_inst->force_sechalf = true; 1823 1824 list_inst->annotation = this->current_annotation; 1825 list_inst->ir = this->base_ir; 1826 1827 this->instructions.push_tail(list_inst); 1828 1829 return list_inst; 1830} 1831 1832/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1833void 1834fs_visitor::emit_dummy_fs() 1835{ 1836 int reg_width = c->dispatch_width / 8; 1837 1838 /* Everyone's favorite color. */ 1839 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)); 1840 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)); 1841 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)); 1842 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)); 1843 1844 fs_inst *write; 1845 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1846 write->base_mrf = 2; 1847 write->mlen = 4 * reg_width; 1848 write->eot = true; 1849} 1850 1851/* The register location here is relative to the start of the URB 1852 * data. It will get adjusted to be a real location before 1853 * generate_code() time. 1854 */ 1855struct brw_reg 1856fs_visitor::interp_reg(int location, int channel) 1857{ 1858 int regnr = urb_setup[location] * 2 + channel / 2; 1859 int stride = (channel & 1) * 4; 1860 1861 assert(urb_setup[location] != -1); 1862 1863 return brw_vec1_grf(regnr, stride); 1864} 1865 1866/** Emits the interpolation for the varying inputs. */ 1867void 1868fs_visitor::emit_interpolation_setup_gen4() 1869{ 1870 this->current_annotation = "compute pixel centers"; 1871 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1872 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1873 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1874 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1875 1876 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1877 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1878 1879 this->current_annotation = "compute pixel deltas from v0"; 1880 if (brw->has_pln) { 1881 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1882 fs_reg(this, glsl_type::vec2_type); 1883 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1884 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC]; 1885 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++; 1886 } else { 1887 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1888 fs_reg(this, glsl_type::float_type); 1889 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1890 fs_reg(this, glsl_type::float_type); 1891 } 1892 emit(BRW_OPCODE_ADD, this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1893 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1894 emit(BRW_OPCODE_ADD, this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1895 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1896 1897 this->current_annotation = "compute pos.w and 1/pos.w"; 1898 /* Compute wpos.w. It's always in our setup, since it's needed to 1899 * interpolate the other attributes. 1900 */ 1901 this->wpos_w = fs_reg(this, glsl_type::float_type); 1902 emit(FS_OPCODE_LINTERP, wpos_w, 1903 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1904 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1905 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1906 /* Compute the pixel 1/W value from wpos.w. */ 1907 this->pixel_w = fs_reg(this, glsl_type::float_type); 1908 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1909 this->current_annotation = NULL; 1910} 1911 1912/** Emits the interpolation for the varying inputs. */ 1913void 1914fs_visitor::emit_interpolation_setup_gen6() 1915{ 1916 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1917 1918 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1919 this->current_annotation = "compute pixel centers"; 1920 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1921 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1922 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1923 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1924 emit(BRW_OPCODE_ADD, 1925 int_pixel_x, 1926 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1927 fs_reg(brw_imm_v(0x10101010))); 1928 emit(BRW_OPCODE_ADD, 1929 int_pixel_y, 1930 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1931 fs_reg(brw_imm_v(0x11001100))); 1932 1933 /* As of gen6, we can no longer mix float and int sources. We have 1934 * to turn the integer pixel centers into floats for their actual 1935 * use. 1936 */ 1937 this->pixel_x = fs_reg(this, glsl_type::float_type); 1938 this->pixel_y = fs_reg(this, glsl_type::float_type); 1939 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1940 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1941 1942 this->current_annotation = "compute pos.w"; 1943 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1944 this->wpos_w = fs_reg(this, glsl_type::float_type); 1945 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1946 1947 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) { 1948 uint8_t reg = c->barycentric_coord_reg[i]; 1949 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0)); 1950 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0)); 1951 } 1952 1953 this->current_annotation = NULL; 1954} 1955 1956void 1957fs_visitor::emit_color_write(int target, int index, int first_color_mrf) 1958{ 1959 int reg_width = c->dispatch_width / 8; 1960 fs_inst *inst; 1961 fs_reg color = outputs[target]; 1962 fs_reg mrf; 1963 1964 /* If there's no color data to be written, skip it. */ 1965 if (color.file == BAD_FILE) 1966 return; 1967 1968 color.reg_offset += index; 1969 1970 if (c->dispatch_width == 8 || intel->gen >= 6) { 1971 /* SIMD8 write looks like: 1972 * m + 0: r0 1973 * m + 1: r1 1974 * m + 2: g0 1975 * m + 3: g1 1976 * 1977 * gen6 SIMD16 DP write looks like: 1978 * m + 0: r0 1979 * m + 1: r1 1980 * m + 2: g0 1981 * m + 3: g1 1982 * m + 4: b0 1983 * m + 5: b1 1984 * m + 6: a0 1985 * m + 7: a1 1986 */ 1987 inst = emit(BRW_OPCODE_MOV, 1988 fs_reg(MRF, first_color_mrf + index * reg_width, color.type), 1989 color); 1990 inst->saturate = c->key.clamp_fragment_color; 1991 } else { 1992 /* pre-gen6 SIMD16 single source DP write looks like: 1993 * m + 0: r0 1994 * m + 1: g0 1995 * m + 2: b0 1996 * m + 3: a0 1997 * m + 4: r1 1998 * m + 5: g1 1999 * m + 6: b1 2000 * m + 7: a1 2001 */ 2002 if (brw->has_compr4) { 2003 /* By setting the high bit of the MRF register number, we 2004 * indicate that we want COMPR4 mode - instead of doing the 2005 * usual destination + 1 for the second half we get 2006 * destination + 4. 2007 */ 2008 inst = emit(BRW_OPCODE_MOV, 2009 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index, 2010 color.type), 2011 color); 2012 inst->saturate = c->key.clamp_fragment_color; 2013 } else { 2014 push_force_uncompressed(); 2015 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index, 2016 color.type), 2017 color); 2018 inst->saturate = c->key.clamp_fragment_color; 2019 pop_force_uncompressed(); 2020 2021 push_force_sechalf(); 2022 color.sechalf = true; 2023 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4, 2024 color.type), 2025 color); 2026 inst->saturate = c->key.clamp_fragment_color; 2027 pop_force_sechalf(); 2028 color.sechalf = false; 2029 } 2030 } 2031} 2032 2033void 2034fs_visitor::emit_fb_writes() 2035{ 2036 this->current_annotation = "FB write header"; 2037 bool header_present = true; 2038 /* We can potentially have a message length of up to 15, so we have to set 2039 * base_mrf to either 0 or 1 in order to fit in m0..m15. 2040 */ 2041 int base_mrf = 1; 2042 int nr = base_mrf; 2043 int reg_width = c->dispatch_width / 8; 2044 bool do_dual_src = this->dual_src_output.file != BAD_FILE; 2045 2046 if (c->dispatch_width == 16 && do_dual_src) { 2047 fail("GL_ARB_blend_func_extended not yet supported in 16-wide."); 2048 do_dual_src = false; 2049 } 2050 2051 /* From the Sandy Bridge PRM, volume 4, page 198: 2052 * 2053 * "Dispatched Pixel Enables. One bit per pixel indicating 2054 * which pixels were originally enabled when the thread was 2055 * dispatched. This field is only required for the end-of- 2056 * thread message and on all dual-source messages." 2057 */ 2058 if (intel->gen >= 6 && 2059 !this->kill_emitted && 2060 !do_dual_src && 2061 c->key.nr_color_regions == 1) { 2062 header_present = false; 2063 } 2064 2065 if (header_present) { 2066 /* m2, m3 header */ 2067 nr += 2; 2068 } 2069 2070 if (c->aa_dest_stencil_reg) { 2071 push_force_uncompressed(); 2072 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 2073 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 2074 pop_force_uncompressed(); 2075 } 2076 2077 /* Reserve space for color. It'll be filled in per MRT below. */ 2078 int color_mrf = nr; 2079 nr += 4 * reg_width; 2080 if (do_dual_src) 2081 nr += 4; 2082 2083 if (c->source_depth_to_render_target) { 2084 if (intel->gen == 6 && c->dispatch_width == 16) { 2085 /* For outputting oDepth on gen6, SIMD8 writes have to be 2086 * used. This would require 8-wide moves of each half to 2087 * message regs, kind of like pre-gen5 SIMD16 FB writes. 2088 * Just bail on doing so for now. 2089 */ 2090 fail("Missing support for simd16 depth writes on gen6\n"); 2091 } 2092 2093 if (c->computes_depth) { 2094 /* Hand over gl_FragDepth. */ 2095 assert(this->frag_depth); 2096 fs_reg depth = *(variable_storage(this->frag_depth)); 2097 2098 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 2099 } else { 2100 /* Pass through the payload depth. */ 2101 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 2102 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 2103 } 2104 nr += reg_width; 2105 } 2106 2107 if (c->dest_depth_reg) { 2108 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 2109 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 2110 nr += reg_width; 2111 } 2112 2113 if (do_dual_src) { 2114 fs_reg src0 = this->outputs[0]; 2115 fs_reg src1 = this->dual_src_output; 2116 2117 this->current_annotation = ralloc_asprintf(this->mem_ctx, 2118 "FB write src0"); 2119 for (int i = 0; i < 4; i++) { 2120 fs_inst *inst = emit(BRW_OPCODE_MOV, 2121 fs_reg(MRF, color_mrf + i, src0.type), 2122 src0); 2123 src0.reg_offset++; 2124 inst->saturate = c->key.clamp_fragment_color; 2125 } 2126 2127 this->current_annotation = ralloc_asprintf(this->mem_ctx, 2128 "FB write src1"); 2129 for (int i = 0; i < 4; i++) { 2130 fs_inst *inst = emit(BRW_OPCODE_MOV, 2131 fs_reg(MRF, color_mrf + 4 + i, src1.type), 2132 src1); 2133 src1.reg_offset++; 2134 inst->saturate = c->key.clamp_fragment_color; 2135 } 2136 2137 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 2138 inst->target = 0; 2139 inst->base_mrf = base_mrf; 2140 inst->mlen = nr - base_mrf; 2141 inst->eot = true; 2142 inst->header_present = header_present; 2143 2144 c->prog_data.dual_src_blend = true; 2145 this->current_annotation = NULL; 2146 return; 2147 } 2148 2149 for (int target = 0; target < c->key.nr_color_regions; target++) { 2150 this->current_annotation = ralloc_asprintf(this->mem_ctx, 2151 "FB write target %d", 2152 target); 2153 for (int i = 0; i < 4; i++) 2154 emit_color_write(target, i, color_mrf); 2155 2156 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 2157 inst->target = target; 2158 inst->base_mrf = base_mrf; 2159 inst->mlen = nr - base_mrf; 2160 if (target == c->key.nr_color_regions - 1) 2161 inst->eot = true; 2162 inst->header_present = header_present; 2163 } 2164 2165 if (c->key.nr_color_regions == 0) { 2166 if (c->key.alpha_test) { 2167 /* If the alpha test is enabled but there's no color buffer, 2168 * we still need to send alpha out the pipeline to our null 2169 * renderbuffer. 2170 */ 2171 emit_color_write(0, 3, color_mrf); 2172 } 2173 2174 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 2175 inst->base_mrf = base_mrf; 2176 inst->mlen = nr - base_mrf; 2177 inst->eot = true; 2178 inst->header_present = header_present; 2179 } 2180 2181 this->current_annotation = NULL; 2182} 2183 2184void 2185fs_visitor::resolve_ud_negate(fs_reg *reg) 2186{ 2187 if (reg->type != BRW_REGISTER_TYPE_UD || 2188 !reg->negate) 2189 return; 2190 2191 fs_reg temp = fs_reg(this, glsl_type::uint_type); 2192 emit(BRW_OPCODE_MOV, temp, *reg); 2193 *reg = temp; 2194} 2195 2196void 2197fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg) 2198{ 2199 if (rvalue->type != glsl_type::bool_type) 2200 return; 2201 2202 fs_reg temp = fs_reg(this, glsl_type::bool_type); 2203 emit(BRW_OPCODE_AND, temp, *reg, fs_reg(1)); 2204 *reg = temp; 2205} 2206