brw_fs_visitor.cpp revision 3f78f719732b87e6707f94c187ad6e263c6c2ef0
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "../glsl/glsl_types.h" 50#include "../glsl/ir_optimization.h" 51#include "../glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || this->result.file == GRF); 146 this->result.reg_offset += index->value.i[0] * element_size; 147 } else { 148 assert(!"FINISHME: non-constant array element"); 149 } 150} 151 152/* Instruction selection: Produce a MOV.sat instead of 153 * MIN(MAX(val, 0), 1) when possible. 154 */ 155bool 156fs_visitor::try_emit_saturate(ir_expression *ir) 157{ 158 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 159 160 if (!sat_val) 161 return false; 162 163 this->result = reg_undef; 164 sat_val->accept(this); 165 fs_reg src = this->result; 166 167 this->result = fs_reg(this, ir->type); 168 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 169 inst->saturate = true; 170 171 return true; 172} 173 174void 175fs_visitor::visit(ir_expression *ir) 176{ 177 unsigned int operand; 178 fs_reg op[2], temp; 179 fs_inst *inst; 180 181 assert(ir->get_num_operands() <= 2); 182 183 if (try_emit_saturate(ir)) 184 return; 185 186 /* This is where our caller would like us to put the result, if possible. */ 187 fs_reg saved_result_storage = this->result; 188 189 for (operand = 0; operand < ir->get_num_operands(); operand++) { 190 this->result = reg_undef; 191 ir->operands[operand]->accept(this); 192 if (this->result.file == BAD_FILE) { 193 ir_print_visitor v; 194 fail("Failed to get tree for expression operand:\n"); 195 ir->operands[operand]->accept(&v); 196 } 197 op[operand] = this->result; 198 199 /* Matrix expression operands should have been broken down to vector 200 * operations already. 201 */ 202 assert(!ir->operands[operand]->type->is_matrix()); 203 /* And then those vector operands should have been broken down to scalar. 204 */ 205 assert(!ir->operands[operand]->type->is_vector()); 206 } 207 208 /* Inherit storage from our parent if possible, and otherwise we 209 * alloc a temporary. 210 */ 211 if (saved_result_storage.file == BAD_FILE) { 212 this->result = fs_reg(this, ir->type); 213 } else { 214 this->result = saved_result_storage; 215 } 216 217 switch (ir->operation) { 218 case ir_unop_logic_not: 219 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 220 * ones complement of the whole register, not just bit 0. 221 */ 222 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 223 break; 224 case ir_unop_neg: 225 op[0].negate = !op[0].negate; 226 this->result = op[0]; 227 break; 228 case ir_unop_abs: 229 op[0].abs = true; 230 op[0].negate = false; 231 this->result = op[0]; 232 break; 233 case ir_unop_sign: 234 temp = fs_reg(this, ir->type); 235 236 /* Unalias the destination. (imagine a = sign(a)) */ 237 this->result = fs_reg(this, ir->type); 238 239 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 240 241 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 242 inst->conditional_mod = BRW_CONDITIONAL_G; 243 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 244 inst->predicated = true; 245 246 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 247 inst->conditional_mod = BRW_CONDITIONAL_L; 248 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 249 inst->predicated = true; 250 251 break; 252 case ir_unop_rcp: 253 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 254 break; 255 256 case ir_unop_exp2: 257 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 258 break; 259 case ir_unop_log2: 260 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 261 break; 262 case ir_unop_exp: 263 case ir_unop_log: 264 assert(!"not reached: should be handled by ir_explog_to_explog2"); 265 break; 266 case ir_unop_sin: 267 case ir_unop_sin_reduced: 268 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 269 break; 270 case ir_unop_cos: 271 case ir_unop_cos_reduced: 272 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 273 break; 274 275 case ir_unop_dFdx: 276 emit(FS_OPCODE_DDX, this->result, op[0]); 277 break; 278 case ir_unop_dFdy: 279 emit(FS_OPCODE_DDY, this->result, op[0]); 280 break; 281 282 case ir_binop_add: 283 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 284 break; 285 case ir_binop_sub: 286 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 287 break; 288 289 case ir_binop_mul: 290 if (ir->type->is_integer()) { 291 /* For integer multiplication, the MUL uses the low 16 bits 292 * of one of the operands (src0 on gen6, src1 on gen7). The 293 * MACH accumulates in the contribution of the upper 16 bits 294 * of that operand. 295 * 296 * FINISHME: Emit just the MUL if we know an operand is small 297 * enough. 298 */ 299 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 300 301 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 302 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 303 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 304 } else { 305 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 306 } 307 break; 308 case ir_binop_div: 309 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 310 break; 311 case ir_binop_mod: 312 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 313 break; 314 315 case ir_binop_less: 316 case ir_binop_greater: 317 case ir_binop_lequal: 318 case ir_binop_gequal: 319 case ir_binop_equal: 320 case ir_binop_all_equal: 321 case ir_binop_nequal: 322 case ir_binop_any_nequal: 323 temp = this->result; 324 /* original gen4 does implicit conversion before comparison. */ 325 if (intel->gen < 5) 326 temp.type = op[0].type; 327 328 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 329 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 330 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 331 break; 332 333 case ir_binop_logic_xor: 334 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 335 break; 336 337 case ir_binop_logic_or: 338 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 339 break; 340 341 case ir_binop_logic_and: 342 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 343 break; 344 345 case ir_binop_dot: 346 case ir_unop_any: 347 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 348 break; 349 350 case ir_unop_noise: 351 assert(!"not reached: should be handled by lower_noise"); 352 break; 353 354 case ir_quadop_vector: 355 assert(!"not reached: should be handled by lower_quadop_vector"); 356 break; 357 358 case ir_unop_sqrt: 359 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 360 break; 361 362 case ir_unop_rsq: 363 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 364 break; 365 366 case ir_unop_i2u: 367 op[0].type = BRW_REGISTER_TYPE_UD; 368 this->result = op[0]; 369 break; 370 case ir_unop_u2i: 371 op[0].type = BRW_REGISTER_TYPE_D; 372 this->result = op[0]; 373 break; 374 case ir_unop_i2f: 375 case ir_unop_b2f: 376 case ir_unop_b2i: 377 case ir_unop_f2i: 378 emit(BRW_OPCODE_MOV, this->result, op[0]); 379 break; 380 case ir_unop_f2b: 381 case ir_unop_i2b: 382 temp = this->result; 383 /* original gen4 does implicit conversion before comparison. */ 384 if (intel->gen < 5) 385 temp.type = op[0].type; 386 387 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 388 inst->conditional_mod = BRW_CONDITIONAL_NZ; 389 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 390 break; 391 392 case ir_unop_trunc: 393 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 394 break; 395 case ir_unop_ceil: 396 op[0].negate = !op[0].negate; 397 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 398 this->result.negate = true; 399 break; 400 case ir_unop_floor: 401 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 402 break; 403 case ir_unop_fract: 404 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 405 break; 406 case ir_unop_round_even: 407 emit(BRW_OPCODE_RNDE, this->result, op[0]); 408 break; 409 410 case ir_binop_min: 411 if (intel->gen >= 6) { 412 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 413 inst->conditional_mod = BRW_CONDITIONAL_L; 414 } else { 415 /* Unalias the destination */ 416 this->result = fs_reg(this, ir->type); 417 418 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 419 inst->conditional_mod = BRW_CONDITIONAL_L; 420 421 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 422 inst->predicated = true; 423 } 424 break; 425 case ir_binop_max: 426 if (intel->gen >= 6) { 427 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 428 inst->conditional_mod = BRW_CONDITIONAL_GE; 429 } else { 430 /* Unalias the destination */ 431 this->result = fs_reg(this, ir->type); 432 433 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 434 inst->conditional_mod = BRW_CONDITIONAL_G; 435 436 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 437 inst->predicated = true; 438 } 439 break; 440 441 case ir_binop_pow: 442 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 443 break; 444 445 case ir_unop_bit_not: 446 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 447 break; 448 case ir_binop_bit_and: 449 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 450 break; 451 case ir_binop_bit_xor: 452 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 453 break; 454 case ir_binop_bit_or: 455 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 456 break; 457 458 case ir_unop_u2f: 459 case ir_binop_lshift: 460 case ir_binop_rshift: 461 assert(!"GLSL 1.30 features unsupported"); 462 break; 463 } 464} 465 466void 467fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 468 const glsl_type *type, bool predicated) 469{ 470 switch (type->base_type) { 471 case GLSL_TYPE_FLOAT: 472 case GLSL_TYPE_UINT: 473 case GLSL_TYPE_INT: 474 case GLSL_TYPE_BOOL: 475 for (unsigned int i = 0; i < type->components(); i++) { 476 l.type = brw_type_for_base_type(type); 477 r.type = brw_type_for_base_type(type); 478 479 if (predicated || !l.equals(&r)) { 480 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 481 inst->predicated = predicated; 482 } 483 484 l.reg_offset++; 485 r.reg_offset++; 486 } 487 break; 488 case GLSL_TYPE_ARRAY: 489 for (unsigned int i = 0; i < type->length; i++) { 490 emit_assignment_writes(l, r, type->fields.array, predicated); 491 } 492 break; 493 494 case GLSL_TYPE_STRUCT: 495 for (unsigned int i = 0; i < type->length; i++) { 496 emit_assignment_writes(l, r, type->fields.structure[i].type, 497 predicated); 498 } 499 break; 500 501 case GLSL_TYPE_SAMPLER: 502 break; 503 504 default: 505 assert(!"not reached"); 506 break; 507 } 508} 509 510void 511fs_visitor::visit(ir_assignment *ir) 512{ 513 struct fs_reg l, r; 514 fs_inst *inst; 515 516 /* FINISHME: arrays on the lhs */ 517 this->result = reg_undef; 518 ir->lhs->accept(this); 519 l = this->result; 520 521 /* If we're doing a direct assignment, an RHS expression could 522 * drop its result right into our destination. Otherwise, tell it 523 * not to. 524 */ 525 if (ir->condition || 526 !(ir->lhs->type->is_scalar() || 527 (ir->lhs->type->is_vector() && 528 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) { 529 this->result = reg_undef; 530 } 531 532 ir->rhs->accept(this); 533 r = this->result; 534 535 assert(l.file != BAD_FILE); 536 assert(r.file != BAD_FILE); 537 538 if (ir->condition) { 539 emit_bool_to_cond_code(ir->condition); 540 } 541 542 if (ir->lhs->type->is_scalar() || 543 ir->lhs->type->is_vector()) { 544 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 545 if (ir->write_mask & (1 << i)) { 546 if (ir->condition) { 547 inst = emit(BRW_OPCODE_MOV, l, r); 548 inst->predicated = true; 549 } else if (!l.equals(&r)) { 550 inst = emit(BRW_OPCODE_MOV, l, r); 551 } 552 553 r.reg_offset++; 554 } 555 l.reg_offset++; 556 } 557 } else { 558 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 559 } 560} 561 562fs_inst * 563fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 564 int sampler) 565{ 566 int mlen; 567 int base_mrf = 1; 568 bool simd16 = false; 569 fs_reg orig_dst; 570 571 /* g0 header. */ 572 mlen = 1; 573 574 if (ir->shadow_comparitor && ir->op != ir_txd) { 575 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 576 fs_inst *inst = emit(BRW_OPCODE_MOV, 577 fs_reg(MRF, base_mrf + mlen + i), coordinate); 578 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 579 inst->saturate = true; 580 581 coordinate.reg_offset++; 582 } 583 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 584 mlen += 3; 585 586 if (ir->op == ir_tex) { 587 /* There's no plain shadow compare message, so we use shadow 588 * compare with a bias of 0.0. 589 */ 590 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 591 mlen++; 592 } else if (ir->op == ir_txb) { 593 this->result = reg_undef; 594 ir->lod_info.bias->accept(this); 595 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 596 mlen++; 597 } else { 598 assert(ir->op == ir_txl); 599 this->result = reg_undef; 600 ir->lod_info.lod->accept(this); 601 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 602 mlen++; 603 } 604 605 this->result = reg_undef; 606 ir->shadow_comparitor->accept(this); 607 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 608 mlen++; 609 } else if (ir->op == ir_tex) { 610 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 611 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 612 coordinate); 613 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 614 inst->saturate = true; 615 coordinate.reg_offset++; 616 } 617 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 618 mlen += 3; 619 } else if (ir->op == ir_txd) { 620 this->result = reg_undef; 621 ir->lod_info.grad.dPdx->accept(this); 622 fs_reg dPdx = this->result; 623 624 this->result = reg_undef; 625 ir->lod_info.grad.dPdy->accept(this); 626 fs_reg dPdy = this->result; 627 628 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 629 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 630 coordinate.reg_offset++; 631 } 632 /* the slots for u and v are always present, but r is optional */ 633 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 634 635 /* P = u, v, r 636 * dPdx = dudx, dvdx, drdx 637 * dPdy = dudy, dvdy, drdy 638 * 639 * 1-arg: Does not exist. 640 * 641 * 2-arg: dudx dvdx dudy dvdy 642 * dPdx.x dPdx.y dPdy.x dPdy.y 643 * m4 m5 m6 m7 644 * 645 * 3-arg: dudx dvdx drdx dudy dvdy drdy 646 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 647 * m5 m6 m7 m8 m9 m10 648 */ 649 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 650 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 651 dPdx.reg_offset++; 652 } 653 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 654 655 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 656 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 657 dPdy.reg_offset++; 658 } 659 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 660 } else { 661 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 662 * instructions. We'll need to do SIMD16 here. 663 */ 664 assert(ir->op == ir_txb || ir->op == ir_txl); 665 666 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 667 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 668 base_mrf + mlen + i * 2), 669 coordinate); 670 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 671 inst->saturate = true; 672 coordinate.reg_offset++; 673 } 674 675 /* lod/bias appears after u/v/r. */ 676 mlen += 6; 677 678 if (ir->op == ir_txb) { 679 this->result = reg_undef; 680 ir->lod_info.bias->accept(this); 681 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 682 mlen++; 683 } else { 684 this->result = reg_undef; 685 ir->lod_info.lod->accept(this); 686 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 687 mlen++; 688 } 689 690 /* The unused upper half. */ 691 mlen++; 692 693 /* Now, since we're doing simd16, the return is 2 interleaved 694 * vec4s where the odd-indexed ones are junk. We'll need to move 695 * this weirdness around to the expected layout. 696 */ 697 simd16 = true; 698 orig_dst = dst; 699 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 700 2)); 701 dst.type = BRW_REGISTER_TYPE_F; 702 } 703 704 fs_inst *inst = NULL; 705 switch (ir->op) { 706 case ir_tex: 707 inst = emit(FS_OPCODE_TEX, dst); 708 break; 709 case ir_txb: 710 inst = emit(FS_OPCODE_TXB, dst); 711 break; 712 case ir_txl: 713 inst = emit(FS_OPCODE_TXL, dst); 714 break; 715 case ir_txd: 716 inst = emit(FS_OPCODE_TXD, dst); 717 break; 718 case ir_txf: 719 assert(!"GLSL 1.30 features unsupported"); 720 break; 721 } 722 inst->base_mrf = base_mrf; 723 inst->mlen = mlen; 724 inst->header_present = true; 725 726 if (simd16) { 727 for (int i = 0; i < 4; i++) { 728 emit(BRW_OPCODE_MOV, orig_dst, dst); 729 orig_dst.reg_offset++; 730 dst.reg_offset += 2; 731 } 732 } 733 734 return inst; 735} 736 737/* gen5's sampler has slots for u, v, r, array index, then optional 738 * parameters like shadow comparitor or LOD bias. If optional 739 * parameters aren't present, those base slots are optional and don't 740 * need to be included in the message. 741 * 742 * We don't fill in the unnecessary slots regardless, which may look 743 * surprising in the disassembly. 744 */ 745fs_inst * 746fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 747 int sampler) 748{ 749 int mlen = 0; 750 int base_mrf = 2; 751 int reg_width = c->dispatch_width / 8; 752 bool header_present = false; 753 754 if (ir->offset) { 755 /* The offsets set up by the ir_texture visitor are in the 756 * m1 header, so we can't go headerless. 757 */ 758 header_present = true; 759 mlen++; 760 base_mrf--; 761 } 762 763 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 764 fs_inst *inst = emit(BRW_OPCODE_MOV, 765 fs_reg(MRF, base_mrf + mlen + i * reg_width), 766 coordinate); 767 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 768 inst->saturate = true; 769 coordinate.reg_offset++; 770 } 771 mlen += ir->coordinate->type->vector_elements * reg_width; 772 773 if (ir->shadow_comparitor && ir->op != ir_txd) { 774 mlen = MAX2(mlen, header_present + 4 * reg_width); 775 776 this->result = reg_undef; 777 ir->shadow_comparitor->accept(this); 778 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 779 mlen += reg_width; 780 } 781 782 fs_inst *inst = NULL; 783 switch (ir->op) { 784 case ir_tex: 785 inst = emit(FS_OPCODE_TEX, dst); 786 break; 787 case ir_txb: 788 this->result = reg_undef; 789 ir->lod_info.bias->accept(this); 790 mlen = MAX2(mlen, header_present + 4 * reg_width); 791 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 792 mlen += reg_width; 793 794 inst = emit(FS_OPCODE_TXB, dst); 795 796 break; 797 case ir_txl: 798 this->result = reg_undef; 799 ir->lod_info.lod->accept(this); 800 mlen = MAX2(mlen, header_present + 4 * reg_width); 801 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 802 mlen += reg_width; 803 804 inst = emit(FS_OPCODE_TXL, dst); 805 break; 806 case ir_txd: { 807 this->result = reg_undef; 808 ir->lod_info.grad.dPdx->accept(this); 809 fs_reg dPdx = this->result; 810 811 this->result = reg_undef; 812 ir->lod_info.grad.dPdy->accept(this); 813 fs_reg dPdy = this->result; 814 815 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 816 817 /** 818 * P = u, v, r 819 * dPdx = dudx, dvdx, drdx 820 * dPdy = dudy, dvdy, drdy 821 * 822 * Load up these values: 823 * - dudx dudy dvdx dvdy drdx drdy 824 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 825 */ 826 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 827 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 828 dPdx.reg_offset++; 829 mlen += reg_width; 830 831 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 832 dPdy.reg_offset++; 833 mlen += reg_width; 834 } 835 836 inst = emit(FS_OPCODE_TXD, dst); 837 break; 838 } 839 case ir_txf: 840 assert(!"GLSL 1.30 features unsupported"); 841 break; 842 } 843 inst->base_mrf = base_mrf; 844 inst->mlen = mlen; 845 inst->header_present = header_present; 846 847 if (mlen > 11) { 848 fail("Message length >11 disallowed by hardware\n"); 849 } 850 851 return inst; 852} 853 854fs_inst * 855fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 856 int sampler) 857{ 858 int mlen = 0; 859 int base_mrf = 2; 860 int reg_width = c->dispatch_width / 8; 861 bool header_present = false; 862 863 if (ir->offset) { 864 /* The offsets set up by the ir_texture visitor are in the 865 * m1 header, so we can't go headerless. 866 */ 867 header_present = true; 868 mlen++; 869 base_mrf--; 870 } 871 872 if (ir->shadow_comparitor && ir->op != ir_txd) { 873 this->result = reg_undef; 874 ir->shadow_comparitor->accept(this); 875 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 876 mlen += reg_width; 877 } 878 879 /* Set up the LOD info */ 880 switch (ir->op) { 881 case ir_tex: 882 break; 883 case ir_txb: 884 this->result = reg_undef; 885 ir->lod_info.bias->accept(this); 886 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 887 mlen += reg_width; 888 break; 889 case ir_txl: 890 this->result = reg_undef; 891 ir->lod_info.lod->accept(this); 892 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 893 mlen += reg_width; 894 break; 895 case ir_txd: { 896 if (c->dispatch_width == 16) 897 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 898 899 this->result = reg_undef; 900 ir->lod_info.grad.dPdx->accept(this); 901 fs_reg dPdx = this->result; 902 903 this->result = reg_undef; 904 ir->lod_info.grad.dPdy->accept(this); 905 fs_reg dPdy = this->result; 906 907 /* Load dPdx and the coordinate together: 908 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 909 */ 910 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 911 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 912 coordinate); 913 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 914 inst->saturate = true; 915 coordinate.reg_offset++; 916 mlen += reg_width; 917 918 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 919 dPdx.reg_offset++; 920 mlen += reg_width; 921 922 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 923 dPdy.reg_offset++; 924 mlen += reg_width; 925 } 926 break; 927 } 928 case ir_txf: 929 assert(!"GLSL 1.30 features unsupported"); 930 break; 931 } 932 933 /* Set up the coordinate (except for TXD where it was done earlier) */ 934 if (ir->op != ir_txd) { 935 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 936 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 937 coordinate); 938 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 939 inst->saturate = true; 940 coordinate.reg_offset++; 941 mlen += reg_width; 942 } 943 } 944 945 /* Generate the SEND */ 946 fs_inst *inst = NULL; 947 switch (ir->op) { 948 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 949 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 950 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 951 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 952 case ir_txf: assert(!"TXF unsupported."); 953 } 954 inst->base_mrf = base_mrf; 955 inst->mlen = mlen; 956 inst->header_present = header_present; 957 958 if (mlen > 11) { 959 fail("Message length >11 disallowed by hardware\n"); 960 } 961 962 return inst; 963} 964 965void 966fs_visitor::visit(ir_texture *ir) 967{ 968 fs_inst *inst = NULL; 969 970 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 971 sampler = fp->Base.SamplerUnits[sampler]; 972 973 /* Our hardware doesn't have a sample_d_c message, so shadow compares 974 * for textureGrad/TXD need to be emulated with instructions. 975 */ 976 bool hw_compare_supported = ir->op != ir_txd; 977 if (ir->shadow_comparitor && !hw_compare_supported) { 978 assert(c->key.compare_funcs[sampler] != GL_NONE); 979 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 980 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 981 return swizzle_result(ir, fs_reg(1.0f), sampler); 982 else if (c->key.compare_funcs[sampler] == GL_NEVER) 983 return swizzle_result(ir, fs_reg(0.0f), sampler); 984 } 985 986 this->result = reg_undef; 987 ir->coordinate->accept(this); 988 fs_reg coordinate = this->result; 989 990 if (ir->offset != NULL) { 991 ir_constant *offset = ir->offset->as_constant(); 992 assert(offset != NULL); 993 994 signed char offsets[3]; 995 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 996 offsets[i] = (signed char) offset->value.i[i]; 997 998 /* Combine all three offsets into a single unsigned dword: 999 * 1000 * bits 11:8 - U Offset (X component) 1001 * bits 7:4 - V Offset (Y component) 1002 * bits 3:0 - R Offset (Z component) 1003 */ 1004 unsigned offset_bits = 0; 1005 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1006 const unsigned shift = 4 * (2 - i); 1007 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1008 } 1009 1010 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1011 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1012 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 1013 1014 /* Then set the offset bits in DWord 2 of the message header. */ 1015 emit(BRW_OPCODE_MOV, 1016 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1017 BRW_REGISTER_TYPE_UD)), 1018 fs_reg(brw_imm_uw(offset_bits))); 1019 } 1020 1021 /* Should be lowered by do_lower_texture_projection */ 1022 assert(!ir->projector); 1023 1024 /* The 965 requires the EU to do the normalization of GL rectangle 1025 * texture coordinates. We use the program parameter state 1026 * tracking to get the scaling factor. 1027 */ 1028 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1029 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1030 int tokens[STATE_LENGTH] = { 1031 STATE_INTERNAL, 1032 STATE_TEXRECT_SCALE, 1033 sampler, 1034 0, 1035 0 1036 }; 1037 1038 if (c->dispatch_width == 16) { 1039 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1040 this->result = fs_reg(this, ir->type); 1041 return; 1042 } 1043 1044 c->prog_data.param_convert[c->prog_data.nr_params] = 1045 PARAM_NO_CONVERT; 1046 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1047 PARAM_NO_CONVERT; 1048 1049 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1050 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1051 GLuint index = _mesa_add_state_reference(params, 1052 (gl_state_index *)tokens); 1053 1054 this->param_index[c->prog_data.nr_params] = index; 1055 this->param_offset[c->prog_data.nr_params] = 0; 1056 c->prog_data.nr_params++; 1057 this->param_index[c->prog_data.nr_params] = index; 1058 this->param_offset[c->prog_data.nr_params] = 1; 1059 c->prog_data.nr_params++; 1060 1061 fs_reg dst = fs_reg(this, ir->coordinate->type); 1062 fs_reg src = coordinate; 1063 coordinate = dst; 1064 1065 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1066 dst.reg_offset++; 1067 src.reg_offset++; 1068 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1069 } 1070 1071 /* Writemasking doesn't eliminate channels on SIMD8 texture 1072 * samples, so don't worry about them. 1073 */ 1074 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 1075 1076 if (intel->gen >= 7) { 1077 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1078 } else if (intel->gen >= 5) { 1079 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1080 } else { 1081 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1082 } 1083 1084 /* If there's an offset, we already set up m1. To avoid the implied move, 1085 * use the null register. Otherwise, we want an implied move from g0. 1086 */ 1087 if (ir->offset != NULL || !inst->header_present) 1088 inst->src[0] = reg_undef; 1089 else 1090 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1091 1092 inst->sampler = sampler; 1093 1094 if (ir->shadow_comparitor) { 1095 if (hw_compare_supported) { 1096 inst->shadow_compare = true; 1097 } else { 1098 this->result = reg_undef; 1099 ir->shadow_comparitor->accept(this); 1100 fs_reg ref = this->result; 1101 1102 fs_reg value = dst; 1103 dst = fs_reg(this, glsl_type::vec4_type); 1104 1105 /* FINISHME: This needs to be done pre-filtering. */ 1106 1107 uint32_t conditional = 0; 1108 switch (c->key.compare_funcs[sampler]) { 1109 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1110 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1111 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1112 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1113 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1114 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1115 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1116 default: assert(!"Should not get here: bad shadow compare function"); 1117 } 1118 1119 /* Use conditional moves to load 0 or 1 as the result */ 1120 this->current_annotation = "manual shadow comparison"; 1121 for (int i = 0; i < 4; i++) { 1122 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1123 1124 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1125 inst->conditional_mod = conditional; 1126 1127 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1128 inst->predicated = true; 1129 1130 dst.reg_offset++; 1131 value.reg_offset++; 1132 } 1133 dst.reg_offset = 0; 1134 } 1135 } 1136 1137 swizzle_result(ir, dst, sampler); 1138} 1139 1140/** 1141 * Swizzle the result of a texture result. This is necessary for 1142 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1143 */ 1144void 1145fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1146{ 1147 this->result = orig_val; 1148 1149 if (ir->type == glsl_type::float_type) { 1150 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1151 assert(ir->sampler->type->sampler_shadow); 1152 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1153 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1154 1155 for (int i = 0; i < 4; i++) { 1156 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1157 fs_reg l = swizzled_result; 1158 l.reg_offset += i; 1159 1160 if (swiz == SWIZZLE_ZERO) { 1161 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1162 } else if (swiz == SWIZZLE_ONE) { 1163 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1164 } else { 1165 fs_reg r = orig_val; 1166 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1167 emit(BRW_OPCODE_MOV, l, r); 1168 } 1169 } 1170 this->result = swizzled_result; 1171 } 1172} 1173 1174void 1175fs_visitor::visit(ir_swizzle *ir) 1176{ 1177 this->result = reg_undef; 1178 ir->val->accept(this); 1179 fs_reg val = this->result; 1180 1181 if (ir->type->vector_elements == 1) { 1182 this->result.reg_offset += ir->mask.x; 1183 return; 1184 } 1185 1186 fs_reg result = fs_reg(this, ir->type); 1187 this->result = result; 1188 1189 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1190 fs_reg channel = val; 1191 int swiz = 0; 1192 1193 switch (i) { 1194 case 0: 1195 swiz = ir->mask.x; 1196 break; 1197 case 1: 1198 swiz = ir->mask.y; 1199 break; 1200 case 2: 1201 swiz = ir->mask.z; 1202 break; 1203 case 3: 1204 swiz = ir->mask.w; 1205 break; 1206 } 1207 1208 channel.reg_offset += swiz; 1209 emit(BRW_OPCODE_MOV, result, channel); 1210 result.reg_offset++; 1211 } 1212} 1213 1214void 1215fs_visitor::visit(ir_discard *ir) 1216{ 1217 assert(ir->condition == NULL); /* FINISHME */ 1218 1219 emit(FS_OPCODE_DISCARD); 1220 kill_emitted = true; 1221} 1222 1223void 1224fs_visitor::visit(ir_constant *ir) 1225{ 1226 /* Set this->result to reg at the bottom of the function because some code 1227 * paths will cause this visitor to be applied to other fields. This will 1228 * cause the value stored in this->result to be modified. 1229 * 1230 * Make reg constant so that it doesn't get accidentally modified along the 1231 * way. Yes, I actually had this problem. :( 1232 */ 1233 const fs_reg reg(this, ir->type); 1234 fs_reg dst_reg = reg; 1235 1236 if (ir->type->is_array()) { 1237 const unsigned size = type_size(ir->type->fields.array); 1238 1239 for (unsigned i = 0; i < ir->type->length; i++) { 1240 this->result = reg_undef; 1241 ir->array_elements[i]->accept(this); 1242 fs_reg src_reg = this->result; 1243 1244 dst_reg.type = src_reg.type; 1245 for (unsigned j = 0; j < size; j++) { 1246 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1247 src_reg.reg_offset++; 1248 dst_reg.reg_offset++; 1249 } 1250 } 1251 } else if (ir->type->is_record()) { 1252 foreach_list(node, &ir->components) { 1253 ir_instruction *const field = (ir_instruction *) node; 1254 const unsigned size = type_size(field->type); 1255 1256 this->result = reg_undef; 1257 field->accept(this); 1258 fs_reg src_reg = this->result; 1259 1260 dst_reg.type = src_reg.type; 1261 for (unsigned j = 0; j < size; j++) { 1262 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1263 src_reg.reg_offset++; 1264 dst_reg.reg_offset++; 1265 } 1266 } 1267 } else { 1268 const unsigned size = type_size(ir->type); 1269 1270 for (unsigned i = 0; i < size; i++) { 1271 switch (ir->type->base_type) { 1272 case GLSL_TYPE_FLOAT: 1273 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1274 break; 1275 case GLSL_TYPE_UINT: 1276 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1277 break; 1278 case GLSL_TYPE_INT: 1279 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1280 break; 1281 case GLSL_TYPE_BOOL: 1282 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1283 break; 1284 default: 1285 assert(!"Non-float/uint/int/bool constant"); 1286 } 1287 dst_reg.reg_offset++; 1288 } 1289 } 1290 1291 this->result = reg; 1292} 1293 1294void 1295fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1296{ 1297 ir_expression *expr = ir->as_expression(); 1298 1299 if (expr) { 1300 fs_reg op[2]; 1301 fs_inst *inst; 1302 1303 assert(expr->get_num_operands() <= 2); 1304 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1305 assert(expr->operands[i]->type->is_scalar()); 1306 1307 this->result = reg_undef; 1308 expr->operands[i]->accept(this); 1309 op[i] = this->result; 1310 } 1311 1312 switch (expr->operation) { 1313 case ir_unop_logic_not: 1314 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1315 inst->conditional_mod = BRW_CONDITIONAL_Z; 1316 break; 1317 1318 case ir_binop_logic_xor: 1319 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1320 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1321 break; 1322 1323 case ir_binop_logic_or: 1324 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1325 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1326 break; 1327 1328 case ir_binop_logic_and: 1329 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1330 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1331 break; 1332 1333 case ir_unop_f2b: 1334 if (intel->gen >= 6) { 1335 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1336 } else { 1337 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1338 } 1339 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1340 break; 1341 1342 case ir_unop_i2b: 1343 if (intel->gen >= 6) { 1344 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1345 } else { 1346 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1347 } 1348 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1349 break; 1350 1351 case ir_binop_greater: 1352 case ir_binop_gequal: 1353 case ir_binop_less: 1354 case ir_binop_lequal: 1355 case ir_binop_equal: 1356 case ir_binop_all_equal: 1357 case ir_binop_nequal: 1358 case ir_binop_any_nequal: 1359 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1360 inst->conditional_mod = 1361 brw_conditional_for_comparison(expr->operation); 1362 break; 1363 1364 default: 1365 assert(!"not reached"); 1366 fail("bad cond code\n"); 1367 break; 1368 } 1369 return; 1370 } 1371 1372 this->result = reg_undef; 1373 ir->accept(this); 1374 1375 if (intel->gen >= 6) { 1376 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1377 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1378 } else { 1379 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1380 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1381 } 1382} 1383 1384/** 1385 * Emit a gen6 IF statement with the comparison folded into the IF 1386 * instruction. 1387 */ 1388void 1389fs_visitor::emit_if_gen6(ir_if *ir) 1390{ 1391 ir_expression *expr = ir->condition->as_expression(); 1392 1393 if (expr) { 1394 fs_reg op[2]; 1395 fs_inst *inst; 1396 fs_reg temp; 1397 1398 assert(expr->get_num_operands() <= 2); 1399 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1400 assert(expr->operands[i]->type->is_scalar()); 1401 1402 this->result = reg_undef; 1403 expr->operands[i]->accept(this); 1404 op[i] = this->result; 1405 } 1406 1407 switch (expr->operation) { 1408 case ir_unop_logic_not: 1409 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1410 inst->conditional_mod = BRW_CONDITIONAL_Z; 1411 return; 1412 1413 case ir_binop_logic_xor: 1414 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1415 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1416 return; 1417 1418 case ir_binop_logic_or: 1419 temp = fs_reg(this, glsl_type::bool_type); 1420 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1421 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1422 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1423 return; 1424 1425 case ir_binop_logic_and: 1426 temp = fs_reg(this, glsl_type::bool_type); 1427 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1428 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1429 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1430 return; 1431 1432 case ir_unop_f2b: 1433 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1434 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1435 return; 1436 1437 case ir_unop_i2b: 1438 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1439 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1440 return; 1441 1442 case ir_binop_greater: 1443 case ir_binop_gequal: 1444 case ir_binop_less: 1445 case ir_binop_lequal: 1446 case ir_binop_equal: 1447 case ir_binop_all_equal: 1448 case ir_binop_nequal: 1449 case ir_binop_any_nequal: 1450 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1451 inst->conditional_mod = 1452 brw_conditional_for_comparison(expr->operation); 1453 return; 1454 default: 1455 assert(!"not reached"); 1456 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1457 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1458 fail("bad condition\n"); 1459 return; 1460 } 1461 return; 1462 } 1463 1464 this->result = reg_undef; 1465 ir->condition->accept(this); 1466 1467 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1468 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1469} 1470 1471void 1472fs_visitor::visit(ir_if *ir) 1473{ 1474 fs_inst *inst; 1475 1476 if (intel->gen != 6 && c->dispatch_width == 16) { 1477 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1478 } 1479 1480 /* Don't point the annotation at the if statement, because then it plus 1481 * the then and else blocks get printed. 1482 */ 1483 this->base_ir = ir->condition; 1484 1485 if (intel->gen == 6) { 1486 emit_if_gen6(ir); 1487 } else { 1488 emit_bool_to_cond_code(ir->condition); 1489 1490 inst = emit(BRW_OPCODE_IF); 1491 inst->predicated = true; 1492 } 1493 1494 foreach_list(node, &ir->then_instructions) { 1495 ir_instruction *ir = (ir_instruction *)node; 1496 this->base_ir = ir; 1497 this->result = reg_undef; 1498 ir->accept(this); 1499 } 1500 1501 if (!ir->else_instructions.is_empty()) { 1502 emit(BRW_OPCODE_ELSE); 1503 1504 foreach_list(node, &ir->else_instructions) { 1505 ir_instruction *ir = (ir_instruction *)node; 1506 this->base_ir = ir; 1507 this->result = reg_undef; 1508 ir->accept(this); 1509 } 1510 } 1511 1512 emit(BRW_OPCODE_ENDIF); 1513} 1514 1515void 1516fs_visitor::visit(ir_loop *ir) 1517{ 1518 fs_reg counter = reg_undef; 1519 1520 if (c->dispatch_width == 16) { 1521 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1522 } 1523 1524 if (ir->counter) { 1525 this->base_ir = ir->counter; 1526 ir->counter->accept(this); 1527 counter = *(variable_storage(ir->counter)); 1528 1529 if (ir->from) { 1530 this->result = counter; 1531 1532 this->base_ir = ir->from; 1533 this->result = counter; 1534 ir->from->accept(this); 1535 1536 if (!this->result.equals(&counter)) 1537 emit(BRW_OPCODE_MOV, counter, this->result); 1538 } 1539 } 1540 1541 emit(BRW_OPCODE_DO); 1542 1543 if (ir->to) { 1544 this->base_ir = ir->to; 1545 this->result = reg_undef; 1546 ir->to->accept(this); 1547 1548 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1549 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1550 1551 inst = emit(BRW_OPCODE_BREAK); 1552 inst->predicated = true; 1553 } 1554 1555 foreach_list(node, &ir->body_instructions) { 1556 ir_instruction *ir = (ir_instruction *)node; 1557 1558 this->base_ir = ir; 1559 this->result = reg_undef; 1560 ir->accept(this); 1561 } 1562 1563 if (ir->increment) { 1564 this->base_ir = ir->increment; 1565 this->result = reg_undef; 1566 ir->increment->accept(this); 1567 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1568 } 1569 1570 emit(BRW_OPCODE_WHILE); 1571} 1572 1573void 1574fs_visitor::visit(ir_loop_jump *ir) 1575{ 1576 switch (ir->mode) { 1577 case ir_loop_jump::jump_break: 1578 emit(BRW_OPCODE_BREAK); 1579 break; 1580 case ir_loop_jump::jump_continue: 1581 emit(BRW_OPCODE_CONTINUE); 1582 break; 1583 } 1584} 1585 1586void 1587fs_visitor::visit(ir_call *ir) 1588{ 1589 assert(!"FINISHME"); 1590} 1591 1592void 1593fs_visitor::visit(ir_return *ir) 1594{ 1595 assert(!"FINISHME"); 1596} 1597 1598void 1599fs_visitor::visit(ir_function *ir) 1600{ 1601 /* Ignore function bodies other than main() -- we shouldn't see calls to 1602 * them since they should all be inlined before we get to ir_to_mesa. 1603 */ 1604 if (strcmp(ir->name, "main") == 0) { 1605 const ir_function_signature *sig; 1606 exec_list empty; 1607 1608 sig = ir->matching_signature(&empty); 1609 1610 assert(sig); 1611 1612 foreach_list(node, &sig->body) { 1613 ir_instruction *ir = (ir_instruction *)node; 1614 this->base_ir = ir; 1615 this->result = reg_undef; 1616 ir->accept(this); 1617 } 1618 } 1619} 1620 1621void 1622fs_visitor::visit(ir_function_signature *ir) 1623{ 1624 assert(!"not reached"); 1625 (void)ir; 1626} 1627 1628fs_inst * 1629fs_visitor::emit(fs_inst inst) 1630{ 1631 fs_inst *list_inst = new(mem_ctx) fs_inst; 1632 *list_inst = inst; 1633 1634 if (force_uncompressed_stack > 0) 1635 list_inst->force_uncompressed = true; 1636 else if (force_sechalf_stack > 0) 1637 list_inst->force_sechalf = true; 1638 1639 list_inst->annotation = this->current_annotation; 1640 list_inst->ir = this->base_ir; 1641 1642 this->instructions.push_tail(list_inst); 1643 1644 return list_inst; 1645} 1646 1647/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1648void 1649fs_visitor::emit_dummy_fs() 1650{ 1651 /* Everyone's favorite color. */ 1652 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1653 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1654 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1655 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1656 1657 fs_inst *write; 1658 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1659 write->base_mrf = 2; 1660} 1661 1662/* The register location here is relative to the start of the URB 1663 * data. It will get adjusted to be a real location before 1664 * generate_code() time. 1665 */ 1666struct brw_reg 1667fs_visitor::interp_reg(int location, int channel) 1668{ 1669 int regnr = urb_setup[location] * 2 + channel / 2; 1670 int stride = (channel & 1) * 4; 1671 1672 assert(urb_setup[location] != -1); 1673 1674 return brw_vec1_grf(regnr, stride); 1675} 1676 1677/** Emits the interpolation for the varying inputs. */ 1678void 1679fs_visitor::emit_interpolation_setup_gen4() 1680{ 1681 this->current_annotation = "compute pixel centers"; 1682 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1683 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1684 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1685 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1686 1687 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1688 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1689 1690 this->current_annotation = "compute pixel deltas from v0"; 1691 if (brw->has_pln) { 1692 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1693 this->delta_y = this->delta_x; 1694 this->delta_y.reg_offset++; 1695 } else { 1696 this->delta_x = fs_reg(this, glsl_type::float_type); 1697 this->delta_y = fs_reg(this, glsl_type::float_type); 1698 } 1699 emit(BRW_OPCODE_ADD, this->delta_x, 1700 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1701 emit(BRW_OPCODE_ADD, this->delta_y, 1702 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1703 1704 this->current_annotation = "compute pos.w and 1/pos.w"; 1705 /* Compute wpos.w. It's always in our setup, since it's needed to 1706 * interpolate the other attributes. 1707 */ 1708 this->wpos_w = fs_reg(this, glsl_type::float_type); 1709 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1710 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1711 /* Compute the pixel 1/W value from wpos.w. */ 1712 this->pixel_w = fs_reg(this, glsl_type::float_type); 1713 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1714 this->current_annotation = NULL; 1715} 1716 1717/** Emits the interpolation for the varying inputs. */ 1718void 1719fs_visitor::emit_interpolation_setup_gen6() 1720{ 1721 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1722 1723 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1724 this->current_annotation = "compute pixel centers"; 1725 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1726 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1727 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1728 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1729 emit(BRW_OPCODE_ADD, 1730 int_pixel_x, 1731 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1732 fs_reg(brw_imm_v(0x10101010))); 1733 emit(BRW_OPCODE_ADD, 1734 int_pixel_y, 1735 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1736 fs_reg(brw_imm_v(0x11001100))); 1737 1738 /* As of gen6, we can no longer mix float and int sources. We have 1739 * to turn the integer pixel centers into floats for their actual 1740 * use. 1741 */ 1742 this->pixel_x = fs_reg(this, glsl_type::float_type); 1743 this->pixel_y = fs_reg(this, glsl_type::float_type); 1744 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1745 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1746 1747 this->current_annotation = "compute pos.w"; 1748 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1749 this->wpos_w = fs_reg(this, glsl_type::float_type); 1750 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1751 1752 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1753 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1754 1755 this->current_annotation = NULL; 1756} 1757 1758void 1759fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1760{ 1761 int reg_width = c->dispatch_width / 8; 1762 fs_inst *inst; 1763 1764 if (c->dispatch_width == 8 || intel->gen == 6) { 1765 /* SIMD8 write looks like: 1766 * m + 0: r0 1767 * m + 1: r1 1768 * m + 2: g0 1769 * m + 3: g1 1770 * 1771 * gen6 SIMD16 DP write looks like: 1772 * m + 0: r0 1773 * m + 1: r1 1774 * m + 2: g0 1775 * m + 3: g1 1776 * m + 4: b0 1777 * m + 5: b1 1778 * m + 6: a0 1779 * m + 7: a1 1780 */ 1781 inst = emit(BRW_OPCODE_MOV, 1782 fs_reg(MRF, first_color_mrf + index * reg_width), 1783 color); 1784 inst->saturate = c->key.clamp_fragment_color; 1785 } else { 1786 /* pre-gen6 SIMD16 single source DP write looks like: 1787 * m + 0: r0 1788 * m + 1: g0 1789 * m + 2: b0 1790 * m + 3: a0 1791 * m + 4: r1 1792 * m + 5: g1 1793 * m + 6: b1 1794 * m + 7: a1 1795 */ 1796 if (brw->has_compr4) { 1797 /* By setting the high bit of the MRF register number, we 1798 * indicate that we want COMPR4 mode - instead of doing the 1799 * usual destination + 1 for the second half we get 1800 * destination + 4. 1801 */ 1802 inst = emit(BRW_OPCODE_MOV, 1803 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1804 color); 1805 inst->saturate = c->key.clamp_fragment_color; 1806 } else { 1807 push_force_uncompressed(); 1808 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1809 color); 1810 inst->saturate = c->key.clamp_fragment_color; 1811 pop_force_uncompressed(); 1812 1813 push_force_sechalf(); 1814 color.sechalf = true; 1815 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1816 color); 1817 inst->saturate = c->key.clamp_fragment_color; 1818 pop_force_sechalf(); 1819 color.sechalf = false; 1820 } 1821 } 1822} 1823 1824void 1825fs_visitor::emit_fb_writes() 1826{ 1827 this->current_annotation = "FB write header"; 1828 GLboolean header_present = GL_TRUE; 1829 int base_mrf = 2; 1830 int nr = base_mrf; 1831 int reg_width = c->dispatch_width / 8; 1832 1833 if (intel->gen >= 6 && 1834 !this->kill_emitted && 1835 c->key.nr_color_regions == 1) { 1836 header_present = false; 1837 } 1838 1839 if (header_present) { 1840 /* m2, m3 header */ 1841 nr += 2; 1842 } 1843 1844 if (c->aa_dest_stencil_reg) { 1845 push_force_uncompressed(); 1846 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1847 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1848 pop_force_uncompressed(); 1849 } 1850 1851 /* Reserve space for color. It'll be filled in per MRT below. */ 1852 int color_mrf = nr; 1853 nr += 4 * reg_width; 1854 1855 if (c->source_depth_to_render_target) { 1856 if (intel->gen == 6 && c->dispatch_width == 16) { 1857 /* For outputting oDepth on gen6, SIMD8 writes have to be 1858 * used. This would require 8-wide moves of each half to 1859 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1860 * Just bail on doing so for now. 1861 */ 1862 fail("Missing support for simd16 depth writes on gen6\n"); 1863 } 1864 1865 if (c->computes_depth) { 1866 /* Hand over gl_FragDepth. */ 1867 assert(this->frag_depth); 1868 fs_reg depth = *(variable_storage(this->frag_depth)); 1869 1870 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1871 } else { 1872 /* Pass through the payload depth. */ 1873 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1874 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1875 } 1876 nr += reg_width; 1877 } 1878 1879 if (c->dest_depth_reg) { 1880 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1881 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1882 nr += reg_width; 1883 } 1884 1885 fs_reg color = reg_undef; 1886 if (this->frag_color) 1887 color = *(variable_storage(this->frag_color)); 1888 else if (this->frag_data) { 1889 color = *(variable_storage(this->frag_data)); 1890 color.type = BRW_REGISTER_TYPE_F; 1891 } 1892 1893 for (int target = 0; target < c->key.nr_color_regions; target++) { 1894 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1895 "FB write target %d", 1896 target); 1897 if (this->frag_color || this->frag_data) { 1898 for (int i = 0; i < 4; i++) { 1899 emit_color_write(i, color_mrf, color); 1900 color.reg_offset++; 1901 } 1902 } 1903 1904 if (this->frag_color) 1905 color.reg_offset -= 4; 1906 1907 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1908 inst->target = target; 1909 inst->base_mrf = base_mrf; 1910 inst->mlen = nr - base_mrf; 1911 if (target == c->key.nr_color_regions - 1) 1912 inst->eot = true; 1913 inst->header_present = header_present; 1914 } 1915 1916 if (c->key.nr_color_regions == 0) { 1917 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1918 /* If the alpha test is enabled but there's no color buffer, 1919 * we still need to send alpha out the pipeline to our null 1920 * renderbuffer. 1921 */ 1922 color.reg_offset += 3; 1923 emit_color_write(3, color_mrf, color); 1924 } 1925 1926 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1927 inst->base_mrf = base_mrf; 1928 inst->mlen = nr - base_mrf; 1929 inst->eot = true; 1930 inst->header_present = header_present; 1931 } 1932 1933 this->current_annotation = NULL; 1934} 1935