1ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 2ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj/*---------------------------------------------------------------*/ 3752f90673ebbb6b2f55fc5e46606dea371313713sewardj/*--- begin libvex.h ---*/ 4ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj/*---------------------------------------------------------------*/ 5ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 6f8ed9d874a7b8651654591c68c6d431c758d787csewardj/* 7752f90673ebbb6b2f55fc5e46606dea371313713sewardj This file is part of Valgrind, a dynamic binary instrumentation 8752f90673ebbb6b2f55fc5e46606dea371313713sewardj framework. 9f8ed9d874a7b8651654591c68c6d431c758d787csewardj 1089ae8477745fd2a15453557d729a50e627325ee2sewardj Copyright (C) 2004-2013 OpenWorks LLP 11752f90673ebbb6b2f55fc5e46606dea371313713sewardj info@open-works.net 127bd6ffe203f3aa9e7b25f7eae40a9b9cf48710cfsewardj 13752f90673ebbb6b2f55fc5e46606dea371313713sewardj This program is free software; you can redistribute it and/or 14752f90673ebbb6b2f55fc5e46606dea371313713sewardj modify it under the terms of the GNU General Public License as 15752f90673ebbb6b2f55fc5e46606dea371313713sewardj published by the Free Software Foundation; either version 2 of the 16752f90673ebbb6b2f55fc5e46606dea371313713sewardj License, or (at your option) any later version. 177bd6ffe203f3aa9e7b25f7eae40a9b9cf48710cfsewardj 18752f90673ebbb6b2f55fc5e46606dea371313713sewardj This program is distributed in the hope that it will be useful, but 19752f90673ebbb6b2f55fc5e46606dea371313713sewardj WITHOUT ANY WARRANTY; without even the implied warranty of 20752f90673ebbb6b2f55fc5e46606dea371313713sewardj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21752f90673ebbb6b2f55fc5e46606dea371313713sewardj General Public License for more details. 22752f90673ebbb6b2f55fc5e46606dea371313713sewardj 23752f90673ebbb6b2f55fc5e46606dea371313713sewardj You should have received a copy of the GNU General Public License 24752f90673ebbb6b2f55fc5e46606dea371313713sewardj along with this program; if not, write to the Free Software 25752f90673ebbb6b2f55fc5e46606dea371313713sewardj Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 267bd6ffe203f3aa9e7b25f7eae40a9b9cf48710cfsewardj 02110-1301, USA. 277bd6ffe203f3aa9e7b25f7eae40a9b9cf48710cfsewardj 28752f90673ebbb6b2f55fc5e46606dea371313713sewardj The GNU General Public License is contained in the file COPYING. 29f8ed9d874a7b8651654591c68c6d431c758d787csewardj 30f8ed9d874a7b8651654591c68c6d431c758d787csewardj Neither the names of the U.S. Department of Energy nor the 31f8ed9d874a7b8651654591c68c6d431c758d787csewardj University of California nor the names of its contributors may be 32f8ed9d874a7b8651654591c68c6d431c758d787csewardj used to endorse or promote products derived from this software 33f8ed9d874a7b8651654591c68c6d431c758d787csewardj without prior written permission. 34f8ed9d874a7b8651654591c68c6d431c758d787csewardj*/ 35f8ed9d874a7b8651654591c68c6d431c758d787csewardj 36887a11a609f3e61d2ae8fe4e67f176207715da7esewardj#ifndef __LIBVEX_H 37887a11a609f3e61d2ae8fe4e67f176207715da7esewardj#define __LIBVEX_H 38ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 39ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 40887a11a609f3e61d2ae8fe4e67f176207715da7esewardj#include "libvex_basictypes.h" 41887a11a609f3e61d2ae8fe4e67f176207715da7esewardj#include "libvex_ir.h" 42ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 43ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 44ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj/*---------------------------------------------------------------*/ 45d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*--- This file defines the top-level interface to LibVEX. ---*/ 46ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj/*---------------------------------------------------------------*/ 47ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 48d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 4927e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj/*--- Architectures, variants, and other arch info ---*/ 50d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 51bef170b7e84713d1e2181b9204d9415d29de3d65sewardj 52bef170b7e84713d1e2181b9204d9415d29de3d65sewardjtypedef 53bef170b7e84713d1e2181b9204d9415d29de3d65sewardj enum { 549b76916dcc1628e133d57db001563429c6e3a590sewardj VexArch_INVALID=0x400, 55bef170b7e84713d1e2181b9204d9415d29de3d65sewardj VexArchX86, 56bef170b7e84713d1e2181b9204d9415d29de3d65sewardj VexArchAMD64, 57896a1373cfdbaa25f4ab73ed4f27554016defecccerion VexArchARM, 58bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj VexArchARM64, 59d953ebb9b04cbad6891676df597bf0c542b1ec89cerion VexArchPPC32, 602019a976f07ff418dde2dfc7cc74667ef66d7764sewardj VexArchPPC64, 61d0e5fe765fb79e5495206f8d0969133178b871f2sewardj VexArchS390X, 62b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj VexArchMIPS32, 630de80192f57cd132b31b233c65734de04939ce65sewardj VexArchMIPS64, 640de80192f57cd132b31b233c65734de04939ce65sewardj VexArchTILEGX 65bef170b7e84713d1e2181b9204d9415d29de3d65sewardj } 66bef170b7e84713d1e2181b9204d9415d29de3d65sewardj VexArch; 67bef170b7e84713d1e2181b9204d9415d29de3d65sewardj 685117ce116f47141cb23d1b49cc826e19323add97sewardj 699b76916dcc1628e133d57db001563429c6e3a590sewardj/* Information about endianness. */ 709b76916dcc1628e133d57db001563429c6e3a590sewardjtypedef 719b76916dcc1628e133d57db001563429c6e3a590sewardj enum { 729b76916dcc1628e133d57db001563429c6e3a590sewardj VexEndness_INVALID=0x600, /* unknown endianness */ 739b76916dcc1628e133d57db001563429c6e3a590sewardj VexEndnessLE, /* little endian */ 749b76916dcc1628e133d57db001563429c6e3a590sewardj VexEndnessBE /* big endian */ 759b76916dcc1628e133d57db001563429c6e3a590sewardj } 769b76916dcc1628e133d57db001563429c6e3a590sewardj VexEndness; 779b76916dcc1628e133d57db001563429c6e3a590sewardj 789b76916dcc1628e133d57db001563429c6e3a590sewardj 795117ce116f47141cb23d1b49cc826e19323add97sewardj/* For a given architecture, these specify extra capabilities beyond 805117ce116f47141cb23d1b49cc826e19323add97sewardj the minimum supported (baseline) capabilities. They may be OR'd 815117ce116f47141cb23d1b49cc826e19323add97sewardj together, although some combinations don't make sense. (eg, SSE2 825117ce116f47141cb23d1b49cc826e19323add97sewardj but not SSE1). LibVEX_Translate will check for nonsensical 835117ce116f47141cb23d1b49cc826e19323add97sewardj combinations. */ 845117ce116f47141cb23d1b49cc826e19323add97sewardj 85e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj/* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE), with 866c65c12ecf69436421ebc1b5637ee13bb4aaf41emjw cmpxchg8b. MMXEXT is a special AMD only subset of SSE1 (Integer SSE). */ 876c65c12ecf69436421ebc1b5637ee13bb4aaf41emjw#define VEX_HWCAPS_X86_MMXEXT (1<<1) /* A subset of SSE1 on early AMD */ 886c65c12ecf69436421ebc1b5637ee13bb4aaf41emjw#define VEX_HWCAPS_X86_SSE1 (1<<2) /* SSE1 support (Pentium III) */ 896c65c12ecf69436421ebc1b5637ee13bb4aaf41emjw#define VEX_HWCAPS_X86_SSE2 (1<<3) /* SSE2 support (Pentium 4) */ 906c65c12ecf69436421ebc1b5637ee13bb4aaf41emjw#define VEX_HWCAPS_X86_SSE3 (1<<4) /* SSE3 support (>= Prescott) */ 916c65c12ecf69436421ebc1b5637ee13bb4aaf41emjw#define VEX_HWCAPS_X86_LZCNT (1<<5) /* SSE4a LZCNT insn */ 925117ce116f47141cb23d1b49cc826e19323add97sewardj 93e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj/* amd64: baseline capability is SSE2, with cmpxchg8b but not 94e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj cmpxchg16b. */ 95cc3d219c3120150c9ab67f1f4850be0f39a9499csewardj#define VEX_HWCAPS_AMD64_SSE3 (1<<5) /* SSE3 support */ 96cc3d219c3120150c9ab67f1f4850be0f39a9499csewardj#define VEX_HWCAPS_AMD64_CX16 (1<<6) /* cmpxchg16b support */ 97cc3d219c3120150c9ab67f1f4850be0f39a9499csewardj#define VEX_HWCAPS_AMD64_LZCNT (1<<7) /* SSE4a LZCNT insn */ 98cc3d219c3120150c9ab67f1f4850be0f39a9499csewardj#define VEX_HWCAPS_AMD64_AVX (1<<8) /* AVX instructions */ 99cc3d219c3120150c9ab67f1f4850be0f39a9499csewardj#define VEX_HWCAPS_AMD64_RDTSCP (1<<9) /* RDTSCP instruction */ 100cc3d219c3120150c9ab67f1f4850be0f39a9499csewardj#define VEX_HWCAPS_AMD64_BMI (1<<10) /* BMI1 instructions */ 101cc3d219c3120150c9ab67f1f4850be0f39a9499csewardj#define VEX_HWCAPS_AMD64_AVX2 (1<<11) /* AVX2 instructions */ 1025117ce116f47141cb23d1b49cc826e19323add97sewardj 1035117ce116f47141cb23d1b49cc826e19323add97sewardj/* ppc32: baseline capability is integer only */ 104536fbabcc3770f42bb7370efd75e8e30e9a841c8sewardj#define VEX_HWCAPS_PPC32_F (1<<8) /* basic (non-optional) FP */ 105536fbabcc3770f42bb7370efd75e8e30e9a841c8sewardj#define VEX_HWCAPS_PPC32_V (1<<9) /* Altivec (VMX) */ 106536fbabcc3770f42bb7370efd75e8e30e9a841c8sewardj#define VEX_HWCAPS_PPC32_FX (1<<10) /* FP extns (fsqrt, fsqrts) */ 107536fbabcc3770f42bb7370efd75e8e30e9a841c8sewardj#define VEX_HWCAPS_PPC32_GX (1<<11) /* Graphics extns 108536fbabcc3770f42bb7370efd75e8e30e9a841c8sewardj (fres,frsqrte,fsel,stfiwx) */ 10966d5ef2c2a31fb52cdd4f02304489e30268ea13fsewardj#define VEX_HWCAPS_PPC32_VX (1<<12) /* Vector-scalar floating-point (VSX); implies ISA 2.06 or higher */ 110a0fb119d673f7be5a8fb22ab1cef362ce77029basewardj#define VEX_HWCAPS_PPC32_DFP (1<<17) /* Decimal Floating Point (DFP) -- e.g., dadd */ 1110c74bb5aa3240f693df0568d578baabf0c376dc4carll#define VEX_HWCAPS_PPC32_ISA2_07 (1<<19) /* ISA 2.07 -- e.g., mtvsrd */ 1125117ce116f47141cb23d1b49cc826e19323add97sewardj 1135117ce116f47141cb23d1b49cc826e19323add97sewardj/* ppc64: baseline capability is integer and basic FP insns */ 11466d5ef2c2a31fb52cdd4f02304489e30268ea13fsewardj#define VEX_HWCAPS_PPC64_V (1<<13) /* Altivec (VMX) */ 11566d5ef2c2a31fb52cdd4f02304489e30268ea13fsewardj#define VEX_HWCAPS_PPC64_FX (1<<14) /* FP extns (fsqrt, fsqrts) */ 11666d5ef2c2a31fb52cdd4f02304489e30268ea13fsewardj#define VEX_HWCAPS_PPC64_GX (1<<15) /* Graphics extns 117536fbabcc3770f42bb7370efd75e8e30e9a841c8sewardj (fres,frsqrte,fsel,stfiwx) */ 11866d5ef2c2a31fb52cdd4f02304489e30268ea13fsewardj#define VEX_HWCAPS_PPC64_VX (1<<16) /* Vector-scalar floating-point (VSX); implies ISA 2.06 or higher */ 119c66d6fa5d9397f167b162483cf3419051cc01a80sewardj#define VEX_HWCAPS_PPC64_DFP (1<<18) /* Decimal Floating Point (DFP) -- e.g., dadd */ 1200c74bb5aa3240f693df0568d578baabf0c376dc4carll#define VEX_HWCAPS_PPC64_ISA2_07 (1<<20) /* ISA 2.07 -- e.g., mtvsrd */ 121c66d6fa5d9397f167b162483cf3419051cc01a80sewardj 122652b56aecd7af6012e82801557b3833f74b19b59sewardj/* s390x: Hardware capability encoding 123652b56aecd7af6012e82801557b3833f74b19b59sewardj 124beef61a4a8141e06a3b2d7196b89f80c06a4b8b0florian Bits [26:31] encode the machine model (see VEX_S390X_MODEL... below) 125beef61a4a8141e06a3b2d7196b89f80c06a4b8b0florian Bits [0:20] encode specific hardware capabilities 126beef61a4a8141e06a3b2d7196b89f80c06a4b8b0florian (see VEX_HWAPS_S390X_... below) 127652b56aecd7af6012e82801557b3833f74b19b59sewardj*/ 128652b56aecd7af6012e82801557b3833f74b19b59sewardj 129652b56aecd7af6012e82801557b3833f74b19b59sewardj/* Model numbers must be assigned in chronological order. 130652b56aecd7af6012e82801557b3833f74b19b59sewardj They are used as array index. */ 131652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z900 0 132652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z800 1 133652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z990 2 134652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z890 3 135652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z9_EC 4 136652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z9_BC 5 137652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z10_EC 6 138652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z10_BC 7 139652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_Z196 8 14087b48b69ee1bda198d6955264ecbc27708801e87florian#define VEX_S390X_MODEL_Z114 9 141c9e43b19b6f3e8854378ae4b82b23a67c14d1dd8florian#define VEX_S390X_MODEL_ZEC12 10 1421bdaac5b4b1a10477f8a2f5d6be0fc498b310496florian#define VEX_S390X_MODEL_ZBC12 11 143dee60eda1c6106c302497213f98024991071ef80florian#define VEX_S390X_MODEL_Z13 12 144dee60eda1c6106c302497213f98024991071ef80florian#define VEX_S390X_MODEL_UNKNOWN 13 /* always last in list */ 145652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL_MASK 0x3F 146652b56aecd7af6012e82801557b3833f74b19b59sewardj 147d07b8566ab17faf70748cfce1304699f1d15c34esewardj#define VEX_HWCAPS_S390X_LDISP (1<<6) /* Long-displacement facility */ 148d07b8566ab17faf70748cfce1304699f1d15c34esewardj#define VEX_HWCAPS_S390X_EIMM (1<<7) /* Extended-immediate facility */ 149d07b8566ab17faf70748cfce1304699f1d15c34esewardj#define VEX_HWCAPS_S390X_GIE (1<<8) /* General-instruction-extension facility */ 150d07b8566ab17faf70748cfce1304699f1d15c34esewardj#define VEX_HWCAPS_S390X_DFP (1<<9) /* Decimal floating point facility */ 151d07b8566ab17faf70748cfce1304699f1d15c34esewardj#define VEX_HWCAPS_S390X_FGX (1<<10) /* FPR-GR transfer facility */ 1529af37696459713188bd0742e7016f3ecde7f8fcdflorian#define VEX_HWCAPS_S390X_ETF2 (1<<11) /* ETF2-enhancement facility */ 15390ece048e612e0b1a2e567cc0a2b58a2ac3b8d27florian#define VEX_HWCAPS_S390X_STFLE (1<<12) /* STFLE facility */ 15479bee4b05db8c5faf12ac48a8e620ab9b14120b5florian#define VEX_HWCAPS_S390X_ETF3 (1<<13) /* ETF3-enhancement facility */ 155a4c3669e976619e71d05605eaa1b29e8bff282eeflorian#define VEX_HWCAPS_S390X_STCKF (1<<14) /* STCKF facility */ 15660b665bdd97b474b14ba27e1ca9f9cff2c2677a5florian#define VEX_HWCAPS_S390X_FPEXT (1<<15) /* Floating point extension facility */ 157aec8e057c2fa910eabc8e665ab63bc16badb3c27florian#define VEX_HWCAPS_S390X_LSC (1<<16) /* Conditional load/store facility */ 15878d5ef75d89e5aa6c629a2d47f7e04ddbf1253c3florian#define VEX_HWCAPS_S390X_PFPO (1<<17) /* Perform floating point ops facility */ 159652b56aecd7af6012e82801557b3833f74b19b59sewardj 1602019a976f07ff418dde2dfc7cc74667ef66d7764sewardj/* Special value representing all available s390x hwcaps */ 1612019a976f07ff418dde2dfc7cc74667ef66d7764sewardj#define VEX_HWCAPS_S390X_ALL (VEX_HWCAPS_S390X_LDISP | \ 1622019a976f07ff418dde2dfc7cc74667ef66d7764sewardj VEX_HWCAPS_S390X_EIMM | \ 1632019a976f07ff418dde2dfc7cc74667ef66d7764sewardj VEX_HWCAPS_S390X_GIE | \ 164d07b8566ab17faf70748cfce1304699f1d15c34esewardj VEX_HWCAPS_S390X_DFP | \ 1659af37696459713188bd0742e7016f3ecde7f8fcdflorian VEX_HWCAPS_S390X_FGX | \ 16690ece048e612e0b1a2e567cc0a2b58a2ac3b8d27florian VEX_HWCAPS_S390X_STFLE | \ 167a4c3669e976619e71d05605eaa1b29e8bff282eeflorian VEX_HWCAPS_S390X_STCKF | \ 16860b665bdd97b474b14ba27e1ca9f9cff2c2677a5florian VEX_HWCAPS_S390X_FPEXT | \ 169aec8e057c2fa910eabc8e665ab63bc16badb3c27florian VEX_HWCAPS_S390X_LSC | \ 17079bee4b05db8c5faf12ac48a8e620ab9b14120b5florian VEX_HWCAPS_S390X_ETF3 | \ 17178d5ef75d89e5aa6c629a2d47f7e04ddbf1253c3florian VEX_HWCAPS_S390X_ETF2 | \ 17278d5ef75d89e5aa6c629a2d47f7e04ddbf1253c3florian VEX_HWCAPS_S390X_PFPO) 1732019a976f07ff418dde2dfc7cc74667ef66d7764sewardj 174652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_HWCAPS_S390X(x) ((x) & ~VEX_S390X_MODEL_MASK) 175652b56aecd7af6012e82801557b3833f74b19b59sewardj#define VEX_S390X_MODEL(x) ((x) & VEX_S390X_MODEL_MASK) 176652b56aecd7af6012e82801557b3833f74b19b59sewardj 1770de80192f57cd132b31b233c65734de04939ce65sewardj/* Tilegx: baseline capability is TILEGX36 */ 1780de80192f57cd132b31b233c65734de04939ce65sewardj#define VEX_HWCAPS_TILEGX_BASE (1<<16) /* TILEGX Baseline */ 1790de80192f57cd132b31b233c65734de04939ce65sewardj 1805117ce116f47141cb23d1b49cc826e19323add97sewardj/* arm: baseline capability is ARMv4 */ 181ec0d9a028955060c5216341c6fc37400ec0cb4besewardj/* Bits 5:0 - architecture level (e.g. 5 for v5, 6 for v6 etc) */ 182ec0d9a028955060c5216341c6fc37400ec0cb4besewardj#define VEX_HWCAPS_ARM_VFP (1<<6) /* VFP extension */ 183ec0d9a028955060c5216341c6fc37400ec0cb4besewardj#define VEX_HWCAPS_ARM_VFP2 (1<<7) /* VFPv2 */ 184ec0d9a028955060c5216341c6fc37400ec0cb4besewardj#define VEX_HWCAPS_ARM_VFP3 (1<<8) /* VFPv3 */ 185ec0d9a028955060c5216341c6fc37400ec0cb4besewardj/* Bits 15:10 reserved for (possible) future VFP revisions */ 186ec0d9a028955060c5216341c6fc37400ec0cb4besewardj#define VEX_HWCAPS_ARM_NEON (1<<16) /* Advanced SIMD also known as NEON */ 187ec0d9a028955060c5216341c6fc37400ec0cb4besewardj 188ec0d9a028955060c5216341c6fc37400ec0cb4besewardj/* Get an ARM architecure level from HWCAPS */ 189ec0d9a028955060c5216341c6fc37400ec0cb4besewardj#define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f) 190bef170b7e84713d1e2181b9204d9415d29de3d65sewardj 191bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj/* ARM64: baseline capability is AArch64 v8. */ 192bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj/* (no definitions since no variants so far) */ 193bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj 194d0e5fe765fb79e5495206f8d0969133178b871f2sewardj/* MIPS baseline capability */ 195d0e5fe765fb79e5495206f8d0969133178b871f2sewardj/* Assigned Company values for bits 23:16 of the PRId Register 196d0e5fe765fb79e5495206f8d0969133178b871f2sewardj (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from 197d0e5fe765fb79e5495206f8d0969133178b871f2sewardj MTI, the PRId register is defined in this (backwards compatible) 198d0e5fe765fb79e5495206f8d0969133178b871f2sewardj way: 199d0e5fe765fb79e5495206f8d0969133178b871f2sewardj 200d0e5fe765fb79e5495206f8d0969133178b871f2sewardj +----------------+----------------+----------------+----------------+ 201d0e5fe765fb79e5495206f8d0969133178b871f2sewardj | Company Options| Company ID | Processor ID | Revision | 202d0e5fe765fb79e5495206f8d0969133178b871f2sewardj +----------------+----------------+----------------+----------------+ 203d0e5fe765fb79e5495206f8d0969133178b871f2sewardj 31 24 23 16 15 8 7 204d0e5fe765fb79e5495206f8d0969133178b871f2sewardj 205d0e5fe765fb79e5495206f8d0969133178b871f2sewardj*/ 206d0e5fe765fb79e5495206f8d0969133178b871f2sewardj 207d0e5fe765fb79e5495206f8d0969133178b871f2sewardj#define VEX_PRID_COMP_MIPS 0x00010000 208d0e5fe765fb79e5495206f8d0969133178b871f2sewardj#define VEX_PRID_COMP_BROADCOM 0x00020000 209bc7d6f46346df80207c8454b35055b04f16bc1adpetarj#define VEX_PRID_COMP_NETLOGIC 0x000C0000 210bc7d6f46346df80207c8454b35055b04f16bc1adpetarj#define VEX_PRID_COMP_CAVIUM 0x000D0000 211d0e5fe765fb79e5495206f8d0969133178b871f2sewardj 212bc7d6f46346df80207c8454b35055b04f16bc1adpetarj/* 213bc7d6f46346df80207c8454b35055b04f16bc1adpetarj * These are the PRID's for when 23:16 == PRID_COMP_MIPS 214bc7d6f46346df80207c8454b35055b04f16bc1adpetarj */ 215bc7d6f46346df80207c8454b35055b04f16bc1adpetarj#define VEX_PRID_IMP_34K 0x9500 216bc7d6f46346df80207c8454b35055b04f16bc1adpetarj#define VEX_PRID_IMP_74K 0x9700 217bc7d6f46346df80207c8454b35055b04f16bc1adpetarj 2180e006f25d4016d7845bd016b65b5d2676a4e8c92dejanj/* CPU has FPU and 32 dbl. prec. FP registers */ 2190e006f25d4016d7845bd016b65b5d2676a4e8c92dejanj#define VEX_PRID_CPU_32FPR 0x00000040 2200e006f25d4016d7845bd016b65b5d2676a4e8c92dejanj 221bc7d6f46346df80207c8454b35055b04f16bc1adpetarj/* Get MIPS Company ID from HWCAPS */ 222bc7d6f46346df80207c8454b35055b04f16bc1adpetarj#define VEX_MIPS_COMP_ID(x) ((x) & 0x00FF0000) 223bc7d6f46346df80207c8454b35055b04f16bc1adpetarj/* Get MIPS Processor ID from HWCAPS */ 2240e006f25d4016d7845bd016b65b5d2676a4e8c92dejanj#define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FF00) 2250e006f25d4016d7845bd016b65b5d2676a4e8c92dejanj/* Get MIPS Revision from HWCAPS */ 2260e006f25d4016d7845bd016b65b5d2676a4e8c92dejanj#define VEX_MIPS_REV(x) ((x) & 0x000000FF) 227bc7d6f46346df80207c8454b35055b04f16bc1adpetarj/* Check if the processor supports DSP ASE Rev 2. */ 228bc7d6f46346df80207c8454b35055b04f16bc1adpetarj#define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \ 229bc7d6f46346df80207c8454b35055b04f16bc1adpetarj (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_74K)) 230bc7d6f46346df80207c8454b35055b04f16bc1adpetarj/* Check if the processor supports DSP ASE Rev 1. */ 231bc7d6f46346df80207c8454b35055b04f16bc1adpetarj#define VEX_MIPS_PROC_DSP(x) (VEX_MIPS_PROC_DSP2(x) || \ 232bc7d6f46346df80207c8454b35055b04f16bc1adpetarj ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \ 233bc7d6f46346df80207c8454b35055b04f16bc1adpetarj (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_34K))) 234c3fee0debd7287a8c6a3b89ee6bc1ec58241938bdejanj 235bef170b7e84713d1e2181b9204d9415d29de3d65sewardj/* These return statically allocated strings. */ 236bef170b7e84713d1e2181b9204d9415d29de3d65sewardj 237bef170b7e84713d1e2181b9204d9415d29de3d65sewardjextern const HChar* LibVEX_ppVexArch ( VexArch ); 2389b76916dcc1628e133d57db001563429c6e3a590sewardjextern const HChar* LibVEX_ppVexEndness ( VexEndness endness ); 2395117ce116f47141cb23d1b49cc826e19323add97sewardjextern const HChar* LibVEX_ppVexHwCaps ( VexArch, UInt ); 240bef170b7e84713d1e2181b9204d9415d29de3d65sewardj 241bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj 242f192a391bc556ff6e074ec055df5b883895e5b52florian/* The various kinds of caches */ 243f192a391bc556ff6e074ec055df5b883895e5b52floriantypedef enum { 2449b76916dcc1628e133d57db001563429c6e3a590sewardj DATA_CACHE=0x500, 245f192a391bc556ff6e074ec055df5b883895e5b52florian INSN_CACHE, 246f192a391bc556ff6e074ec055df5b883895e5b52florian UNIFIED_CACHE 247f192a391bc556ff6e074ec055df5b883895e5b52florian} VexCacheKind; 248f192a391bc556ff6e074ec055df5b883895e5b52florian 249f192a391bc556ff6e074ec055df5b883895e5b52florian/* Information about a particular cache */ 250f192a391bc556ff6e074ec055df5b883895e5b52floriantypedef struct { 251f192a391bc556ff6e074ec055df5b883895e5b52florian VexCacheKind kind; 252f192a391bc556ff6e074ec055df5b883895e5b52florian UInt level; /* level this cache is at, e.g. 1 for L1 cache */ 253f192a391bc556ff6e074ec055df5b883895e5b52florian UInt sizeB; /* size of this cache in bytes */ 254f192a391bc556ff6e074ec055df5b883895e5b52florian UInt line_sizeB; /* cache line size in bytes */ 255f192a391bc556ff6e074ec055df5b883895e5b52florian UInt assoc; /* set associativity */ 25680ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian Bool is_trace_cache; /* False, except for certain Pentium 4 models */ 257f192a391bc556ff6e074ec055df5b883895e5b52florian} VexCache; 258f192a391bc556ff6e074ec055df5b883895e5b52florian 259f192a391bc556ff6e074ec055df5b883895e5b52florian/* Convenience macro to initialise a VexCache */ 260f192a391bc556ff6e074ec055df5b883895e5b52florian#define VEX_CACHE_INIT(_kind, _level, _size, _line_size, _assoc) \ 261f192a391bc556ff6e074ec055df5b883895e5b52florian ({ (VexCache) { .kind = _kind, .level = _level, .sizeB = _size, \ 26280ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian .line_sizeB = _line_size, .assoc = _assoc, \ 26380ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian .is_trace_cache = False }; }) 264f192a391bc556ff6e074ec055df5b883895e5b52florian 265f192a391bc556ff6e074ec055df5b883895e5b52florian/* Information about the cache system as a whole */ 266f192a391bc556ff6e074ec055df5b883895e5b52floriantypedef struct { 267f192a391bc556ff6e074ec055df5b883895e5b52florian UInt num_levels; 268f192a391bc556ff6e074ec055df5b883895e5b52florian UInt num_caches; 269f192a391bc556ff6e074ec055df5b883895e5b52florian /* Unordered array of caches for this host. NULL if there are 27080ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian no caches. The following can always be assumed: 27180ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian (1) There is at most one cache of a given kind per cache level. 27280ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian (2) If there exists a unified cache at a particular level then 27380ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian no other cache exists at that level. 27480ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian (3) The existence of a cache at level N > 1 implies the existence of 27580ab2655aa6db2cc08bbcff8429236a57cba8f0cflorian at least one cache at level N-1. */ 276f192a391bc556ff6e074ec055df5b883895e5b52florian VexCache *caches; 277f192a391bc556ff6e074ec055df5b883895e5b52florian Bool icaches_maintain_coherence; 278f192a391bc556ff6e074ec055df5b883895e5b52florian} VexCacheInfo; 279f192a391bc556ff6e074ec055df5b883895e5b52florian 280ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 28127e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj/* This struct is a bit of a hack, but is needed to carry misc 282aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj important bits of info about an arch. Fields which are meaningless 283f192a391bc556ff6e074ec055df5b883895e5b52florian or ignored for the platform in question should be set to zero. 284f192a391bc556ff6e074ec055df5b883895e5b52florian Nb: if you add fields to the struct make sure to update function 285f192a391bc556ff6e074ec055df5b883895e5b52florian LibVEX_default_VexArchInfo. */ 28627e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj 28727e1dd6317760f3222f8a82185fa0e8ba138c85bsewardjtypedef 28827e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj struct { 2899b76916dcc1628e133d57db001563429c6e3a590sewardj /* The following three fields are mandatory. */ 2909b76916dcc1628e133d57db001563429c6e3a590sewardj UInt hwcaps; 2919b76916dcc1628e133d57db001563429c6e3a590sewardj VexEndness endness; 292f192a391bc556ff6e074ec055df5b883895e5b52florian VexCacheInfo hwcache_info; 2939138b1779efcff4b12896ccd10744d8118e89a70florian /* PPC32/PPC64 only: size of instruction cache line */ 2949138b1779efcff4b12896ccd10744d8118e89a70florian Int ppc_icache_line_szB; 295e971c6a8b613ab2ea92a34f802a0e39c01e84b19sewardj /* PPC32/PPC64 only: sizes zeroed by the dcbz/dcbzl instructions 29665902992da28822e4753594c7b72f7cb177fe3a6sewardj (bug#135264) */ 297e971c6a8b613ab2ea92a34f802a0e39c01e84b19sewardj UInt ppc_dcbz_szB; 298e971c6a8b613ab2ea92a34f802a0e39c01e84b19sewardj UInt ppc_dcbzl_szB; /* 0 means unsupported (SIGILL) */ 29965902992da28822e4753594c7b72f7cb177fe3a6sewardj /* ARM64: I- and D- minimum line sizes in log2(bytes), as 30065902992da28822e4753594c7b72f7cb177fe3a6sewardj obtained from ctr_el0.DminLine and .IminLine. For example, a 30165902992da28822e4753594c7b72f7cb177fe3a6sewardj line size of 64 bytes would be encoded here as 6. */ 30265902992da28822e4753594c7b72f7cb177fe3a6sewardj UInt arm64_dMinLine_lg2_szB; 30365902992da28822e4753594c7b72f7cb177fe3a6sewardj UInt arm64_iMinLine_lg2_szB; 30427e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj } 30527e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj VexArchInfo; 30627e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj 30727e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj/* Write default settings info *vai. */ 30827e1dd6317760f3222f8a82185fa0e8ba138c85bsewardjextern 30927e1dd6317760f3222f8a82185fa0e8ba138c85bsewardjvoid LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ); 31027e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj 31127e1dd6317760f3222f8a82185fa0e8ba138c85bsewardj 312aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj/* This struct carries guest and host ABI variant information that may 313aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj be needed. Fields which are meaningless or ignored for the 314aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj platform in question should be set to zero. 315aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 316aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj Settings which are believed to be correct are: 317aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 318aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest_stack_redzone_size 319aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is ppc32-linux ==> 0 320aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is ppc64-linux ==> 288 321aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is amd64-linux ==> 128 322aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is other ==> inapplicable 323aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 324e2cc4defff3eec3be8e38ccc21df5ee460f930e9philippe guest_amd64_assume_fs_is_const 3252e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj guest is amd64-linux ==> True 3262e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj guest is amd64-darwin ==> False 3272e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj guest is other ==> inapplicable 3282e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj 329e2cc4defff3eec3be8e38ccc21df5ee460f930e9philippe guest_amd64_assume_gs_is_const 3302e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj guest is amd64-darwin ==> True 331e2cc4defff3eec3be8e38ccc21df5ee460f930e9philippe guest is amd64-linux ==> True 3322e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj guest is other ==> inapplicable 3332e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj 334aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest_ppc_zap_RZ_at_blr 335aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is ppc64-linux ==> True 336aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is ppc32-linux ==> False 337aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is other ==> inapplicable 338aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 339aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest_ppc_zap_RZ_at_bl 340aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is ppc64-linux ==> const True 341aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is ppc32-linux ==> const False 342aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest is other ==> inapplicable 343aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 344aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj host_ppc_calls_use_fndescrs: 345aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj host is ppc32-linux ==> False 346aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj host is ppc64-linux ==> True 347aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj host is other ==> inapplicable 348aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj*/ 349aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 350aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardjtypedef 351aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj struct { 352aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj /* PPC and AMD64 GUESTS only: how many bytes below the 353aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj stack pointer are validly addressible? */ 354aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj Int guest_stack_redzone_size; 355aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 3562e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj /* AMD64 GUESTS only: should we translate %fs-prefixed 3572e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj instructions using the assumption that %fs always contains 358e2cc4defff3eec3be8e38ccc21df5ee460f930e9philippe the same value? (typically zero on linux) */ 359e2cc4defff3eec3be8e38ccc21df5ee460f930e9philippe Bool guest_amd64_assume_fs_is_const; 3602e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj 3612e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj /* AMD64 GUESTS only: should we translate %gs-prefixed 3622e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj instructions using the assumption that %gs always contains 363e2cc4defff3eec3be8e38ccc21df5ee460f930e9philippe the same value? (typically 0x60 on darwin)? */ 364e2cc4defff3eec3be8e38ccc21df5ee460f930e9philippe Bool guest_amd64_assume_gs_is_const; 3652e28ac4ec6d9bc40e2e1ec35d779e38a717dcba7sewardj 366aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj /* PPC GUESTS only: should we zap the stack red zone at a 'blr' 367aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj (function return) ? */ 368aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj Bool guest_ppc_zap_RZ_at_blr; 369aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 370aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj /* PPC GUESTS only: should we zap the stack red zone at a 'bl' 371aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj (function call) ? Is supplied with the guest address of the 372aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj target of the call since that may be significant. If NULL, 373aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj is assumed equivalent to a fn which always returns False. */ 374bdf99f06a5f44fd617c51ac80861ff07da09a50fflorian Bool (*guest_ppc_zap_RZ_at_bl)(Addr); 375aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 376aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj /* PPC32/PPC64 HOSTS only: does '&f' give us a pointer to a 377aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj function descriptor on the host, or to the function code 378aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj itself? True => descriptor, False => code. */ 379aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj Bool host_ppc_calls_use_fndescrs; 380aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj } 381dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardj VexAbiInfo; 382aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 383dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardj/* Write default settings info *vbi. */ 384aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardjextern 385dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardjvoid LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ); 386aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 387aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj 388d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 389d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*--- Control of Vex's optimiser (iropt). ---*/ 390d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 391d887b8634b2c2685f528bd968459c628e8f86a34sewardj 392c8e2f983c84affb3cbe4cebee1516aedaf944f79philippe 393c8e2f983c84affb3cbe4cebee1516aedaf944f79philippe/* VexRegisterUpdates specifies when to ensure that the guest state is 394ca2c3c75784d35d136fc7c952717cdee5063c193sewardj up to date, in order of increasing accuracy but increasing expense. 395ca2c3c75784d35d136fc7c952717cdee5063c193sewardj 396ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpdSpAtMemAccess: all registers are updated at superblock 397ca2c3c75784d35d136fc7c952717cdee5063c193sewardj exits, and SP is also up to date at memory exception points. The 398ca2c3c75784d35d136fc7c952717cdee5063c193sewardj SP is described by the arch specific functions 399ca2c3c75784d35d136fc7c952717cdee5063c193sewardj guest_<arch>_state_requires_precise_mem_exns. 400ca2c3c75784d35d136fc7c952717cdee5063c193sewardj 401ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpdUnwindregsAtMemAccess: registers needed to make a stack 402ca2c3c75784d35d136fc7c952717cdee5063c193sewardj trace are up to date at memory exception points. Typically, 403ca2c3c75784d35d136fc7c952717cdee5063c193sewardj these are PC/SP/FP. The minimal registers are described by the 404ca2c3c75784d35d136fc7c952717cdee5063c193sewardj arch specific functions guest_<arch>_state_requires_precise_mem_exns. 405ca2c3c75784d35d136fc7c952717cdee5063c193sewardj This is what Valgrind sets as the default. 406ca2c3c75784d35d136fc7c952717cdee5063c193sewardj 407ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpdAllregsAtMemAccess: all registers up to date at memory 408ca2c3c75784d35d136fc7c952717cdee5063c193sewardj exception points. This is what normally might be considered as 409ca2c3c75784d35d136fc7c952717cdee5063c193sewardj providing "precise exceptions for memory", but does not 410ca2c3c75784d35d136fc7c952717cdee5063c193sewardj necessarily provide precise register values at any other kind of 411ca2c3c75784d35d136fc7c952717cdee5063c193sewardj exception. 412ca2c3c75784d35d136fc7c952717cdee5063c193sewardj 413ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpdAllregsAtEachInsn: all registers up to date at each 414ca2c3c75784d35d136fc7c952717cdee5063c193sewardj instruction. 415ca2c3c75784d35d136fc7c952717cdee5063c193sewardj*/ 416ca2c3c75784d35d136fc7c952717cdee5063c193sewardjtypedef 417ca2c3c75784d35d136fc7c952717cdee5063c193sewardj enum { 418ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpd_INVALID=0x700, 419ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpdSpAtMemAccess, 420ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpdUnwindregsAtMemAccess, 421ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpdAllregsAtMemAccess, 422ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegUpdAllregsAtEachInsn 423ca2c3c75784d35d136fc7c952717cdee5063c193sewardj } 424ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegisterUpdates; 425c8e2f983c84affb3cbe4cebee1516aedaf944f79philippe 42608613749b639323cc7582c1bbe56c6e21c69774fsewardj/* Control of Vex's optimiser. */ 42708613749b639323cc7582c1bbe56c6e21c69774fsewardj 42808613749b639323cc7582c1bbe56c6e21c69774fsewardjtypedef 42908613749b639323cc7582c1bbe56c6e21c69774fsewardj struct { 43008613749b639323cc7582c1bbe56c6e21c69774fsewardj /* Controls verbosity of iropt. 0 = no output. */ 43108613749b639323cc7582c1bbe56c6e21c69774fsewardj Int iropt_verbosity; 43208613749b639323cc7582c1bbe56c6e21c69774fsewardj /* Control aggressiveness of iropt. 0 = no opt, 1 = simple 43308613749b639323cc7582c1bbe56c6e21c69774fsewardj opts, 2 (default) = max optimisation. */ 43408613749b639323cc7582c1bbe56c6e21c69774fsewardj Int iropt_level; 435ca2c3c75784d35d136fc7c952717cdee5063c193sewardj /* Controls when registers are updated in guest state. Note 436ca2c3c75784d35d136fc7c952717cdee5063c193sewardj that this is the default value. The VEX client can override 437ca2c3c75784d35d136fc7c952717cdee5063c193sewardj this on a per-IRSB basis if it wants. bb_to_IR() will query 438ca2c3c75784d35d136fc7c952717cdee5063c193sewardj the client to ask if it wants a different setting for the 439ca2c3c75784d35d136fc7c952717cdee5063c193sewardj block under construction, and that new setting is transported 440ca2c3c75784d35d136fc7c952717cdee5063c193sewardj back to LibVEX_Translate, which feeds it to iropt via the 441ca2c3c75784d35d136fc7c952717cdee5063c193sewardj various do_iropt_BB calls. */ 442ca2c3c75784d35d136fc7c952717cdee5063c193sewardj VexRegisterUpdates iropt_register_updates_default; 44308613749b639323cc7582c1bbe56c6e21c69774fsewardj /* How aggressive should iropt be in unrolling loops? Higher 44408613749b639323cc7582c1bbe56c6e21c69774fsewardj numbers make it more enthusiastic about loop unrolling. 44508613749b639323cc7582c1bbe56c6e21c69774fsewardj Default=120. A setting of zero disables unrolling. */ 44608613749b639323cc7582c1bbe56c6e21c69774fsewardj Int iropt_unroll_thresh; 44708613749b639323cc7582c1bbe56c6e21c69774fsewardj /* What's the maximum basic block length the front end(s) allow? 44808613749b639323cc7582c1bbe56c6e21c69774fsewardj BBs longer than this are split up. Default=50 (guest 44908613749b639323cc7582c1bbe56c6e21c69774fsewardj insns). */ 45008613749b639323cc7582c1bbe56c6e21c69774fsewardj Int guest_max_insns; 45108613749b639323cc7582c1bbe56c6e21c69774fsewardj /* How aggressive should front ends be in following 45208613749b639323cc7582c1bbe56c6e21c69774fsewardj unconditional branches to known destinations? Default=10, 45308613749b639323cc7582c1bbe56c6e21c69774fsewardj meaning that if a block contains less than 10 guest insns so 45408613749b639323cc7582c1bbe56c6e21c69774fsewardj far, the front end(s) will attempt to chase into its 45508613749b639323cc7582c1bbe56c6e21c69774fsewardj successor. A setting of zero disables chasing. */ 45608613749b639323cc7582c1bbe56c6e21c69774fsewardj Int guest_chase_thresh; 457984d9b164dd17f07e603c41fe1e506e641e57d18sewardj /* EXPERIMENTAL: chase across conditional branches? Not all 458984d9b164dd17f07e603c41fe1e506e641e57d18sewardj front ends honour this. Default: NO. */ 459984d9b164dd17f07e603c41fe1e506e641e57d18sewardj Bool guest_chase_cond; 46008613749b639323cc7582c1bbe56c6e21c69774fsewardj } 46108613749b639323cc7582c1bbe56c6e21c69774fsewardj VexControl; 46208613749b639323cc7582c1bbe56c6e21c69774fsewardj 46308613749b639323cc7582c1bbe56c6e21c69774fsewardj 46408613749b639323cc7582c1bbe56c6e21c69774fsewardj/* Write the default settings into *vcon. */ 465bef170b7e84713d1e2181b9204d9415d29de3d65sewardj 466d887b8634b2c2685f528bd968459c628e8f86a34sewardjextern 467d887b8634b2c2685f528bd968459c628e8f86a34sewardjvoid LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ); 46880f5fceef55dc74b2ccca99d957699cbfc495176sewardj 46980f5fceef55dc74b2ccca99d957699cbfc495176sewardj 470d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 471d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*--- Storage management control ---*/ 472d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 473443cd9d34617dd7608e5dd4b4b0b4674d4f433e7sewardj 474d887b8634b2c2685f528bd968459c628e8f86a34sewardj/* Allocate in Vex's temporary allocation area. Be careful with this. 475d887b8634b2c2685f528bd968459c628e8f86a34sewardj You can only call it inside an instrumentation or optimisation 476d887b8634b2c2685f528bd968459c628e8f86a34sewardj callback that you have previously specified in a call to 477d887b8634b2c2685f528bd968459c628e8f86a34sewardj LibVEX_Translate. The storage allocated will only stay alive until 478bde340633ae5d586ad1e46b7d8989353f3870f10florian translation of the current basic block is complete. */ 47904fc6b1eab791c7387b81b9fd820f4ae6aaf90a2florianextern void* LibVEX_Alloc ( SizeT nbytes ); 480443cd9d34617dd7608e5dd4b4b0b4674d4f433e7sewardj 481d887b8634b2c2685f528bd968459c628e8f86a34sewardj/* Show Vex allocation statistics. */ 482d887b8634b2c2685f528bd968459c628e8f86a34sewardjextern void LibVEX_ShowAllocStats ( void ); 483443cd9d34617dd7608e5dd4b4b0b4674d4f433e7sewardj 484ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 485d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 486d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*--- Describing guest state layout ---*/ 487d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 488ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 48949651f4b59b1ab7e0e70cccd34001630eafbe957sewardj/* Describe the guest state enough that the instrumentation 49049651f4b59b1ab7e0e70cccd34001630eafbe957sewardj functions can work. */ 49149651f4b59b1ab7e0e70cccd34001630eafbe957sewardj 492eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj/* The max number of guest state chunks which we can describe as 493eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj always defined (for the benefit of Memcheck). */ 494e86310f555a233cc2ca02e1a5d0adb555f12bdcdsewardj#define VEXGLO_N_ALWAYSDEFD 24 495eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj 49649651f4b59b1ab7e0e70cccd34001630eafbe957sewardjtypedef 49749651f4b59b1ab7e0e70cccd34001630eafbe957sewardj struct { 498cf7879021370aabcccb1a9347244fcc7d5680141sewardj /* Total size of the guest state, in bytes. Must be 49995a487bc73c0f8c9371ad500988a51c9e78ee34aflorian 16-aligned. */ 500eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj Int total_sizeB; 50149651f4b59b1ab7e0e70cccd34001630eafbe957sewardj /* Whereabouts is the stack pointer? */ 50249651f4b59b1ab7e0e70cccd34001630eafbe957sewardj Int offset_SP; 50349651f4b59b1ab7e0e70cccd34001630eafbe957sewardj Int sizeof_SP; /* 4 or 8 */ 504a203330aad67bc3e52ca1395a55e94ef9a091223sewardj /* Whereabouts is the frame pointer? */ 505a203330aad67bc3e52ca1395a55e94ef9a091223sewardj Int offset_FP; 506a203330aad67bc3e52ca1395a55e94ef9a091223sewardj Int sizeof_FP; /* 4 or 8 */ 507cf7879021370aabcccb1a9347244fcc7d5680141sewardj /* Whereabouts is the instruction pointer? */ 508cf7879021370aabcccb1a9347244fcc7d5680141sewardj Int offset_IP; 509cf7879021370aabcccb1a9347244fcc7d5680141sewardj Int sizeof_IP; /* 4 or 8 */ 510eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj /* Describe parts of the guest state regarded as 'always 511eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj defined'. */ 512eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj Int n_alwaysDefd; 513eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj struct { 514eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj Int offset; 515eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj Int size; 516eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj } alwaysDefd[VEXGLO_N_ALWAYSDEFD]; 51749651f4b59b1ab7e0e70cccd34001630eafbe957sewardj } 518eeac841fbfcadbc19e97c7ef56bfa3354ba78637sewardj VexGuestLayout; 51949651f4b59b1ab7e0e70cccd34001630eafbe957sewardj 520d887b8634b2c2685f528bd968459c628e8f86a34sewardj/* A note about guest state layout. 521d887b8634b2c2685f528bd968459c628e8f86a34sewardj 522d887b8634b2c2685f528bd968459c628e8f86a34sewardj LibVEX defines the layout for the guest state, in the file 523478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj pub/libvex_guest_<arch>.h. The struct will have an 16-aligned 524478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj size. Each translated bb is assumed to be entered with a specified 525478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj register pointing at such a struct. Beyond that is two copies of 526478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj the shadow state area with the same size as the struct. Beyond 527478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj that is a spill area that LibVEX may spill into. It must have size 528d887b8634b2c2685f528bd968459c628e8f86a34sewardj LibVEX_N_SPILL_BYTES, and this must be a 16-aligned number. 529d887b8634b2c2685f528bd968459c628e8f86a34sewardj 530478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj On entry, the baseblock pointer register must be 16-aligned. 531478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj 532478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj There must be no holes in between the primary guest state, its two 533478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj copies, and the spill area. In short, all 4 areas must have a 534478646f54befaba01cbceb40fd5e46cdf562fdb5sewardj 16-aligned size and be 16-aligned, and placed back-to-back. 535d887b8634b2c2685f528bd968459c628e8f86a34sewardj*/ 536d887b8634b2c2685f528bd968459c628e8f86a34sewardj 537d652012dee9c391721b91200a3172b3e8c4b2077sewardj#define LibVEX_N_SPILL_BYTES 4096 538d887b8634b2c2685f528bd968459c628e8f86a34sewardj 5395074b493ae4af5e6017fac208f823d283c6123c0florian/* The size of the guest state must be a multiple of this number. */ 5405074b493ae4af5e6017fac208f823d283c6123c0florian#define LibVEX_GUEST_STATE_ALIGN 16 54149651f4b59b1ab7e0e70cccd34001630eafbe957sewardj 542d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 543d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*--- Initialisation of the library ---*/ 544d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 545d887b8634b2c2685f528bd968459c628e8f86a34sewardj 546d887b8634b2c2685f528bd968459c628e8f86a34sewardj/* Initialise the library. You must call this first. */ 547d887b8634b2c2685f528bd968459c628e8f86a34sewardj 548d887b8634b2c2685f528bd968459c628e8f86a34sewardjextern void LibVEX_Init ( 5496312e80eb6b87773188e8a9d897460a004133c2csewardj 550d887b8634b2c2685f528bd968459c628e8f86a34sewardj /* failure exit function */ 5516312e80eb6b87773188e8a9d897460a004133c2csewardj# if __cplusplus == 1 && __GNUC__ && __GNUC__ <= 3 5526312e80eb6b87773188e8a9d897460a004133c2csewardj /* g++ 3.x doesn't understand attributes on function parameters. 5536312e80eb6b87773188e8a9d897460a004133c2csewardj See #265762. */ 5546312e80eb6b87773188e8a9d897460a004133c2csewardj# else 555d887b8634b2c2685f528bd968459c628e8f86a34sewardj __attribute__ ((noreturn)) 5566312e80eb6b87773188e8a9d897460a004133c2csewardj# endif 557d887b8634b2c2685f528bd968459c628e8f86a34sewardj void (*failure_exit) ( void ), 5586312e80eb6b87773188e8a9d897460a004133c2csewardj 559d887b8634b2c2685f528bd968459c628e8f86a34sewardj /* logging output function */ 56004fc6b1eab791c7387b81b9fd820f4ae6aaf90a2florian void (*log_bytes) ( const HChar*, SizeT nbytes ), 5616312e80eb6b87773188e8a9d897460a004133c2csewardj 562d887b8634b2c2685f528bd968459c628e8f86a34sewardj /* debug paranoia level */ 563d887b8634b2c2685f528bd968459c628e8f86a34sewardj Int debuglevel, 5646312e80eb6b87773188e8a9d897460a004133c2csewardj 565d887b8634b2c2685f528bd968459c628e8f86a34sewardj /* Control ... */ 566f72c2c12a06fdfada40f8a42fac44514c2d9c181florian const VexControl* vcon 567d887b8634b2c2685f528bd968459c628e8f86a34sewardj); 568d887b8634b2c2685f528bd968459c628e8f86a34sewardj 569d887b8634b2c2685f528bd968459c628e8f86a34sewardj 570d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 571d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*--- Make a translation ---*/ 572d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 573ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 57472c72814ab82c51d8ee8accad1a00f2d37942545sewardj/* Describes the outcome of a translation attempt. */ 575ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardjtypedef 576bc161a407b3cbd722821812afb8fb47420ae538fsewardj struct { 577bc161a407b3cbd722821812afb8fb47420ae538fsewardj /* overall status */ 5789b76916dcc1628e133d57db001563429c6e3a590sewardj enum { VexTransOK=0x800, 579bc161a407b3cbd722821812afb8fb47420ae538fsewardj VexTransAccessFail, VexTransOutputFull } status; 580bc161a407b3cbd722821812afb8fb47420ae538fsewardj /* The number of extents that have a self-check (0 to 3) */ 581bc161a407b3cbd722821812afb8fb47420ae538fsewardj UInt n_sc_extents; 582c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj /* Offset in generated code of the profile inc, or -1 if 583c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj none. Needed for later patching. */ 584c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Int offs_profInc; 585fadbbe2870ffba4e4565563f21fc20b9ab89fd8fsewardj /* Stats only: the number of guest insns included in the 586fadbbe2870ffba4e4565563f21fc20b9ab89fd8fsewardj translation. It may be zero (!). */ 587fadbbe2870ffba4e4565563f21fc20b9ab89fd8fsewardj UInt n_guest_instrs; 588d887b8634b2c2685f528bd968459c628e8f86a34sewardj } 589d887b8634b2c2685f528bd968459c628e8f86a34sewardj VexTranslateResult; 590ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 59172c72814ab82c51d8ee8accad1a00f2d37942545sewardj 59272c72814ab82c51d8ee8accad1a00f2d37942545sewardj/* Describes precisely the pieces of guest code that a translation 59372c72814ab82c51d8ee8accad1a00f2d37942545sewardj covers. Now that Vex can chase across BB boundaries, the old 59472c72814ab82c51d8ee8accad1a00f2d37942545sewardj scheme of describing a chunk of guest code merely by its start 59572c72814ab82c51d8ee8accad1a00f2d37942545sewardj address and length is inadequate. 59672c72814ab82c51d8ee8accad1a00f2d37942545sewardj 597bdf99f06a5f44fd617c51ac80861ff07da09a50fflorian This struct uses 20 bytes on a 32-bit archtecture and 32 bytes on a 598bdf99f06a5f44fd617c51ac80861ff07da09a50fflorian 64-bit architecture. Space is important as clients will have to store 599bdf99f06a5f44fd617c51ac80861ff07da09a50fflorian one of these for each translation made. 60072c72814ab82c51d8ee8accad1a00f2d37942545sewardj*/ 60172c72814ab82c51d8ee8accad1a00f2d37942545sewardjtypedef 60272c72814ab82c51d8ee8accad1a00f2d37942545sewardj struct { 603bdf99f06a5f44fd617c51ac80861ff07da09a50fflorian Addr base[3]; 60472c72814ab82c51d8ee8accad1a00f2d37942545sewardj UShort len[3]; 60572c72814ab82c51d8ee8accad1a00f2d37942545sewardj UShort n_used; 60672c72814ab82c51d8ee8accad1a00f2d37942545sewardj } 60772c72814ab82c51d8ee8accad1a00f2d37942545sewardj VexGuestExtents; 60872c72814ab82c51d8ee8accad1a00f2d37942545sewardj 60972c72814ab82c51d8ee8accad1a00f2d37942545sewardj 61017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj/* A structure to carry arguments for LibVEX_Translate. There are so 61117c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj many of them, it seems better to have a structure. */ 61217c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardjtypedef 61317c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj struct { 614aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj /* IN: The instruction sets we are translating from and to. And 615aca070a5b3418a6a9b01e3c57a7eb0fbb5050908sewardj guest/host misc info. */ 61617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj VexArch arch_guest; 61717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj VexArchInfo archinfo_guest; 61817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj VexArch arch_host; 61917c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj VexArchInfo archinfo_host; 620dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardj VexAbiInfo abiinfo_both; 62117c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 622c716aea1cafe66ee431dc7d6909c98f18788a028sewardj /* IN: an opaque value which is passed as the first arg to all 623c716aea1cafe66ee431dc7d6909c98f18788a028sewardj callback functions supplied in this struct. Vex has no idea 624c716aea1cafe66ee431dc7d6909c98f18788a028sewardj what's at the other end of this pointer. */ 625c716aea1cafe66ee431dc7d6909c98f18788a028sewardj void* callback_opaque; 626c716aea1cafe66ee431dc7d6909c98f18788a028sewardj 62717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* IN: the block to translate, and its guest address. */ 62817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* where are the actual bytes in the host's address space? */ 6298462d113e3efeacceb304222dada8d85f748295aflorian const UChar* guest_bytes; 63017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* where do the bytes really come from in the guest's aspace? 631c716aea1cafe66ee431dc7d6909c98f18788a028sewardj This is the post-redirection guest address. Not that Vex 632c716aea1cafe66ee431dc7d6909c98f18788a028sewardj understands anything about redirection; that is all done on 633c716aea1cafe66ee431dc7d6909c98f18788a028sewardj the Valgrind side. */ 634d4cc0deec55ec0be1f2ac3b20f0d340265341f83florian Addr guest_bytes_addr; 63517c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 63617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* Is it OK to chase into this guest address? May not be 63717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj NULL. */ 638beac530a718fcc646bc61fe60a86f599df54e1d7florian Bool (*chase_into_ok) ( /*callback_opaque*/void*, Addr ); 63917c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 64017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* OUT: which bits of guest code actually got translated */ 64117c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj VexGuestExtents* guest_extents; 64217c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 64317c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* IN: a place to put the resulting code, and its size */ 64417c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj UChar* host_bytes; 64517c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj Int host_bytes_size; 64617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* OUT: how much of the output area is used. */ 64717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj Int* host_bytes_used; 64817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 64917c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* IN: optionally, two instrumentation functions. May be 65017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj NULL. */ 651dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardj IRSB* (*instrument1) ( /*callback_opaque*/void*, 652dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardj IRSB*, 6530a5494ebb258459db1f829c6100962485762db27florian const VexGuestLayout*, 6540a5494ebb258459db1f829c6100962485762db27florian const VexGuestExtents*, 6550a5494ebb258459db1f829c6100962485762db27florian const VexArchInfo*, 65617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj IRType gWordTy, IRType hWordTy ); 657dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardj IRSB* (*instrument2) ( /*callback_opaque*/void*, 658dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardj IRSB*, 6590a5494ebb258459db1f829c6100962485762db27florian const VexGuestLayout*, 6600a5494ebb258459db1f829c6100962485762db27florian const VexGuestExtents*, 6610a5494ebb258459db1f829c6100962485762db27florian const VexArchInfo*, 66217c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj IRType gWordTy, IRType hWordTy ); 66317c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 664be1b6ff6cdb576c59734762fb778ae48eb8e7a10sewardj IRSB* (*finaltidy) ( IRSB* ); 665be1b6ff6cdb576c59734762fb778ae48eb8e7a10sewardj 666bc161a407b3cbd722821812afb8fb47420ae538fsewardj /* IN: a callback used to ask the caller which of the extents, 6672eeeb9bc9367c26449deaa632e9f8eafa60c4685florian if any, a self check is required for. Must not be NULL. 6682eeeb9bc9367c26449deaa632e9f8eafa60c4685florian The returned value is a bitmask with a 1 in position i indicating 6692eeeb9bc9367c26449deaa632e9f8eafa60c4685florian that the i'th extent needs a check. Since there can be at most 670ca2c3c75784d35d136fc7c952717cdee5063c193sewardj 3 extents, the returned values must be between 0 and 7. 671ca2c3c75784d35d136fc7c952717cdee5063c193sewardj 672ca2c3c75784d35d136fc7c952717cdee5063c193sewardj This call also gives the VEX client the opportunity to change 673ca2c3c75784d35d136fc7c952717cdee5063c193sewardj the precision of register update preservation as performed by 674ca2c3c75784d35d136fc7c952717cdee5063c193sewardj the IR optimiser. Before the call, VEX will set *pxControl 675ca2c3c75784d35d136fc7c952717cdee5063c193sewardj to hold the default register-update status value as specified 676ca2c3c75784d35d136fc7c952717cdee5063c193sewardj by VexControl::iropt_register_updates_default as passed to 677ca2c3c75784d35d136fc7c952717cdee5063c193sewardj LibVEX_Init at library initialisation time. The client (in 678ca2c3c75784d35d136fc7c952717cdee5063c193sewardj this callback) can if it wants, inspect the value and change 679ca2c3c75784d35d136fc7c952717cdee5063c193sewardj it to something different, and that value will be used for 680ca2c3c75784d35d136fc7c952717cdee5063c193sewardj subsequent IR optimisation of the block. */ 681bc161a407b3cbd722821812afb8fb47420ae538fsewardj UInt (*needs_self_check)( /*callback_opaque*/void*, 682ca2c3c75784d35d136fc7c952717cdee5063c193sewardj /*MAYBE_MOD*/VexRegisterUpdates* pxControl, 6830a5494ebb258459db1f829c6100962485762db27florian const VexGuestExtents* ); 684c716aea1cafe66ee431dc7d6909c98f18788a028sewardj 685c716aea1cafe66ee431dc7d6909c98f18788a028sewardj /* IN: optionally, a callback which allows the caller to add its 686c716aea1cafe66ee431dc7d6909c98f18788a028sewardj own IR preamble following the self-check and any other 687c716aea1cafe66ee431dc7d6909c98f18788a028sewardj VEX-generated preamble, if any. May be NULL. If non-NULL, 688f6c8ebf1294fea43756683ba7089b746168abb8esewardj the IRSB under construction is handed to this function, which 689c716aea1cafe66ee431dc7d6909c98f18788a028sewardj presumably adds IR statements to it. The callback may 690c716aea1cafe66ee431dc7d6909c98f18788a028sewardj optionally complete the block and direct bb_to_IR not to 691c716aea1cafe66ee431dc7d6909c98f18788a028sewardj disassemble any instructions into it; this is indicated by 692c716aea1cafe66ee431dc7d6909c98f18788a028sewardj the callback returning True. 693c716aea1cafe66ee431dc7d6909c98f18788a028sewardj */ 694dd40fdf58cc8a6fe9466c4f00bdfc9fe9bf00449sewardj Bool (*preamble_function)(/*callback_opaque*/void*, IRSB*); 695ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj 69617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj /* IN: debug: trace vex activity at various points */ 69717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj Int traceflags; 69817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 699442e51a26cf3bc7f243167a4ff3fbfb02206f6e6sewardj /* IN: debug: print diagnostics when an illegal instr is detected */ 700442e51a26cf3bc7f243167a4ff3fbfb02206f6e6sewardj Bool sigill_diag; 701442e51a26cf3bc7f243167a4ff3fbfb02206f6e6sewardj 702c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj /* IN: profiling: add a 64 bit profiler counter increment to the 703c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj translation? */ 704c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Bool addProfInc; 705c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 706010ac5400c3294a8c0991fac7b382578e5b91b1csewardj /* IN: address of the dispatcher entry points. Describes the 707010ac5400c3294a8c0991fac7b382578e5b91b1csewardj places where generated code should jump to at the end of each 70817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj bb. 70917c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 71017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj At the end of each translation, the next guest address is 71117c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj placed in the host's standard return register (x86: %eax, 71217c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj amd64: %rax, ppc32: %r3, ppc64: %r3). Optionally, the guest 71317c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj state pointer register (on host x86: %ebp; amd64: %rbp; 71417c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj ppc32/64: r31) may be set to a VEX_TRC_ value to indicate any 71517c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj special action required before the next block is run. 71617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 71717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj Control is then passed back to the dispatcher (beyond Vex's 71817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj control; caller supplies this) in the following way: 71917c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 72017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj - On host archs which lack a link register (x86, amd64), by a 721010ac5400c3294a8c0991fac7b382578e5b91b1csewardj jump to the host address specified in 722010ac5400c3294a8c0991fac7b382578e5b91b1csewardj 'dispatcher_assisted', if the guest state pointer has been 723010ac5400c3294a8c0991fac7b382578e5b91b1csewardj changed so as to request some action before the next block 724010ac5400c3294a8c0991fac7b382578e5b91b1csewardj is run, or 'dispatcher_unassisted' (the fast path), in 725010ac5400c3294a8c0991fac7b382578e5b91b1csewardj which it is assumed that the guest state pointer is 726010ac5400c3294a8c0991fac7b382578e5b91b1csewardj unchanged and we wish to continue directly with the next 727010ac5400c3294a8c0991fac7b382578e5b91b1csewardj translation. Both of these must be non-NULL. 72817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 72917c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj - On host archs which have a link register (ppc32, ppc64), by 73017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj a branch to the link register (which is guaranteed to be 73117c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj unchanged from whatever it was at entry to the 732010ac5400c3294a8c0991fac7b382578e5b91b1csewardj translation). 'dispatch_assisted' and 733010ac5400c3294a8c0991fac7b382578e5b91b1csewardj 'dispatch_unassisted' must be NULL. 73417c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 73517c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj The aim is to get back and forth between translations and the 73617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj dispatcher without creating memory traffic to store return 73717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj addresses. 738c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 739c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj FIXME: update this comment 74017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj */ 7418462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_chain_me_to_slowEP; 7428462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_chain_me_to_fastEP; 7438462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_xindir; 7448462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_xassisted; 74517c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj } 74617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj VexTranslateArgs; 74717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 74817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 749ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardjextern 75017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardjVexTranslateResult LibVEX_Translate ( VexTranslateArgs* ); 75117c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 752c24824a245cd1883e037af8e952e664a837f9437sewardj/* A subtlety re interaction between self-checking translations and 753c24824a245cd1883e037af8e952e664a837f9437sewardj bb-chasing. The supplied chase_into_ok function should say NO 754c24824a245cd1883e037af8e952e664a837f9437sewardj (False) when presented with any address for which you might want to 755c24824a245cd1883e037af8e952e664a837f9437sewardj make a self-checking translation. 756c24824a245cd1883e037af8e952e664a837f9437sewardj 757c24824a245cd1883e037af8e952e664a837f9437sewardj If it doesn't do that, you may end up with Vex chasing from BB #1 758c24824a245cd1883e037af8e952e664a837f9437sewardj to BB #2 (fine); but if you wanted checking for #2 and not #1, that 759c24824a245cd1883e037af8e952e664a837f9437sewardj would not be the result. Therefore chase_into_ok should disallow 760c24824a245cd1883e037af8e952e664a837f9437sewardj following into #2. That will force the caller to eventually 761c24824a245cd1883e037af8e952e664a837f9437sewardj request a new translation starting at #2, at which point Vex will 762c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj correctly observe the make-a-self-check flag. 763c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 764c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj FIXME: is this still up to date? */ 765c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 766c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 767c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/*-------------------------------------------------------*/ 768c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/*--- Patch existing translations ---*/ 769c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/*-------------------------------------------------------*/ 770c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 7715ea257be80e49474f724426939d4c398c8bfab1bflorian/* A host address range that was modified by the functions below. 7725ea257be80e49474f724426939d4c398c8bfab1bflorian Callers must request I-cache syncing after the call as appropriate. */ 773c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjtypedef 774c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj struct { 775c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj HWord start; 7765ea257be80e49474f724426939d4c398c8bfab1bflorian HWord len; /* always > 0 */ 777c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj } 778c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj VexInvalRange; 779c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 780c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/* Chain an XDirect jump located at place_to_chain so it jumps to 781c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj place_to_jump_to. It is expected (and checked) that this site 782c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj currently contains a call to the dispatcher specified by 783c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj disp_cp_chain_me_EXPECTED. */ 784c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern 7857d6f81de12e6d8deb3e119ab318f361d97a10a65florianVexInvalRange LibVEX_Chain ( VexArch arch_host, 7867d6f81de12e6d8deb3e119ab318f361d97a10a65florian VexEndness endhess_host, 7877d6f81de12e6d8deb3e119ab318f361d97a10a65florian void* place_to_chain, 7887d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* disp_cp_chain_me_EXPECTED, 7897d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* place_to_jump_to ); 790c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 791c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/* Undo an XDirect jump located at place_to_unchain, so it is 792c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj converted back into a call to disp_cp_chain_me. It is expected 793c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj (and checked) that this site currently contains a jump directly to 794c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj the address specified by place_to_jump_to_EXPECTED. */ 795c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern 7967d6f81de12e6d8deb3e119ab318f361d97a10a65florianVexInvalRange LibVEX_UnChain ( VexArch arch_host, 7977d6f81de12e6d8deb3e119ab318f361d97a10a65florian VexEndness endness_host, 7987d6f81de12e6d8deb3e119ab318f361d97a10a65florian void* place_to_unchain, 7997d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* place_to_jump_to_EXPECTED, 8007d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* disp_cp_chain_me ); 801c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 802c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/* Returns a constant -- the size of the event check that is put at 803c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj the start of every translation. This makes it possible to 804c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj calculate the fast entry point address if the slow entry point 805c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj address is known (the usual case), or vice versa. */ 806c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern 8077ce2cc883c5b36586babec833838951ecf9f2a76florianInt LibVEX_evCheckSzB ( VexArch arch_host ); 808c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 809c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 810c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/* Patch the counter location into an existing ProfInc point. The 811c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj specified point is checked to make sure it is plausible. */ 812c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern 8137d6f81de12e6d8deb3e119ab318f361d97a10a65florianVexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, 8147d6f81de12e6d8deb3e119ab318f361d97a10a65florian VexEndness endness_host, 8157d6f81de12e6d8deb3e119ab318f361d97a10a65florian void* place_to_patch, 8167d6f81de12e6d8deb3e119ab318f361d97a10a65florian const ULong* location_of_counter ); 817c24824a245cd1883e037af8e952e664a837f9437sewardj 818ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 819d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 820d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*--- Show accumulated statistics ---*/ 821d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 822ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 823887a11a609f3e61d2ae8fe4e67f176207715da7esewardjextern void LibVEX_ShowStats ( void ); 824ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 8252245ce9e834193d49261b8a433b4a0bd128c878eflorian/*-------------------------------------------------------*/ 8262245ce9e834193d49261b8a433b4a0bd128c878eflorian/*-- IR injection --*/ 8272245ce9e834193d49261b8a433b4a0bd128c878eflorian/*-------------------------------------------------------*/ 8282245ce9e834193d49261b8a433b4a0bd128c878eflorian 8292245ce9e834193d49261b8a433b4a0bd128c878eflorian/* IR Injection Control Block */ 8302245ce9e834193d49261b8a433b4a0bd128c878eflorian 8312245ce9e834193d49261b8a433b4a0bd128c878eflorian#define NO_ROUNDING_MODE (~0u) 8322245ce9e834193d49261b8a433b4a0bd128c878eflorian 8332245ce9e834193d49261b8a433b4a0bd128c878efloriantypedef 8342245ce9e834193d49261b8a433b4a0bd128c878eflorian struct { 8352245ce9e834193d49261b8a433b4a0bd128c878eflorian IROp op; // the operation to perform 8362245ce9e834193d49261b8a433b4a0bd128c878eflorian HWord result; // address of the result 8372245ce9e834193d49261b8a433b4a0bd128c878eflorian HWord opnd1; // address of 1st operand 8382245ce9e834193d49261b8a433b4a0bd128c878eflorian HWord opnd2; // address of 2nd operand 8392245ce9e834193d49261b8a433b4a0bd128c878eflorian HWord opnd3; // address of 3rd operand 8402245ce9e834193d49261b8a433b4a0bd128c878eflorian HWord opnd4; // address of 4th operand 8412245ce9e834193d49261b8a433b4a0bd128c878eflorian IRType t_result; // type of result 8422245ce9e834193d49261b8a433b4a0bd128c878eflorian IRType t_opnd1; // type of 1st operand 8432245ce9e834193d49261b8a433b4a0bd128c878eflorian IRType t_opnd2; // type of 2nd operand 8442245ce9e834193d49261b8a433b4a0bd128c878eflorian IRType t_opnd3; // type of 3rd operand 8452245ce9e834193d49261b8a433b4a0bd128c878eflorian IRType t_opnd4; // type of 4th operand 8462245ce9e834193d49261b8a433b4a0bd128c878eflorian UInt rounding_mode; 8472245ce9e834193d49261b8a433b4a0bd128c878eflorian UInt num_operands; // excluding rounding mode, if any 84816d12b458fdc540ba33efd0f14c5ae873ea03179florian Bool shift_amount_is_immediate; 8492245ce9e834193d49261b8a433b4a0bd128c878eflorian } 8502245ce9e834193d49261b8a433b4a0bd128c878eflorian IRICB; 8512245ce9e834193d49261b8a433b4a0bd128c878eflorian 8522245ce9e834193d49261b8a433b4a0bd128c878eflorianextern void LibVEX_InitIRI ( const IRICB * ); 853ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 854d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 855d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*--- Notes ---*/ 856d887b8634b2c2685f528bd968459c628e8f86a34sewardj/*-------------------------------------------------------*/ 857812a858ee395c40817f43cf2b5fb161be1dd7081sewardj 858812a858ee395c40817f43cf2b5fb161be1dd7081sewardj/* Code generation conventions that need to be recorded somewhere. 859812a858ee395c40817f43cf2b5fb161be1dd7081sewardj ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 860812a858ee395c40817f43cf2b5fb161be1dd7081sewardj 861812a858ee395c40817f43cf2b5fb161be1dd7081sewardj x86 862812a858ee395c40817f43cf2b5fb161be1dd7081sewardj ~~~ 86317c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj Generated code should be entered using a JMP instruction. On 864812a858ee395c40817f43cf2b5fb161be1dd7081sewardj entry, %ebp should point to the guest state, and %esp should be a 865812a858ee395c40817f43cf2b5fb161be1dd7081sewardj valid stack pointer. The generated code may change %eax, %ebx, 866812a858ee395c40817f43cf2b5fb161be1dd7081sewardj %ecx, %edx, %esi, %edi, all the FP registers and control state, and 867812a858ee395c40817f43cf2b5fb161be1dd7081sewardj all the XMM registers. 868812a858ee395c40817f43cf2b5fb161be1dd7081sewardj 8696915b973f99496ac1b1baf070ec11bc608b297c6sewardj On entry, the FPU control word should be set to 0x027F, and the SSE 870812a858ee395c40817f43cf2b5fb161be1dd7081sewardj control word (%mxcsr) should be set to 0x1F80. On exit, they 871812a858ee395c40817f43cf2b5fb161be1dd7081sewardj should still have those values (after masking off the lowest 6 bits 872812a858ee395c40817f43cf2b5fb161be1dd7081sewardj of %mxcsr). If they don't, there is a bug in VEX-generated code. 873812a858ee395c40817f43cf2b5fb161be1dd7081sewardj 87417c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj Generated code returns to the scheduler using a JMP instruction, to 87517c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj the address specified in the .dispatch field of VexTranslateArgs. 876812a858ee395c40817f43cf2b5fb161be1dd7081sewardj %eax (or %eax:%edx, if simulating a 64-bit target) will contain the 87717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj guest address of the next block to execute. %ebp may be changed 87817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj to a VEX_TRC_ value, otherwise it should be as it was at entry. 879812a858ee395c40817f43cf2b5fb161be1dd7081sewardj 880812a858ee395c40817f43cf2b5fb161be1dd7081sewardj CRITICAL ISSUES in x86 code generation. The only known critical 881812a858ee395c40817f43cf2b5fb161be1dd7081sewardj issue is that the host FPU and SSE state is not properly saved 882812a858ee395c40817f43cf2b5fb161be1dd7081sewardj across calls to helper functions. If any helper references any 883812a858ee395c40817f43cf2b5fb161be1dd7081sewardj such state, it is likely (1) to misbehave itself, since the FP 884812a858ee395c40817f43cf2b5fb161be1dd7081sewardj stack tags will not be as expected, and (2) after returning to 885812a858ee395c40817f43cf2b5fb161be1dd7081sewardj generated code, the generated code is likely to go wrong. This 886812a858ee395c40817f43cf2b5fb161be1dd7081sewardj really should be fixed. 887812a858ee395c40817f43cf2b5fb161be1dd7081sewardj 88817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj amd64 88917c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj ~~~~~ 89017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj Analogous to x86. 89117c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 89217c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj ppc32 89317c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj ~~~~~ 89417c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj On entry, guest state pointer is r31. .dispatch must be NULL. 89517c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj Control is returned with a branch to the link register. Generated 89617c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj code will not change lr. At return, r3 holds the next guest addr 89717c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj (or r3:r4 ?). r31 may be may be changed to a VEX_TRC_ value, 89817c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj otherwise it should be as it was at entry. 89917c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 90017c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj ppc64 90117c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj ~~~~~ 9025b2325f209f6d3c7ab9c4e819d15060f8d1f09efcerion Same as ppc32. 90317c7f95c78bb3c8ced934e41a4bf1aae6d857d59sewardj 904bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj arm32 905bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj ~~~~~ 906bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj r8 is GSP. 907bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj 908bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj arm64 909bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj ~~~~~ 910bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj r21 is GSP. 911bbcf188f6ae64a44fb31414eb9e1a738b4befcc0sewardj 912db4738ab05bf88fabe7fd931a24fab2fa2060e73sewardj ALL GUEST ARCHITECTURES 913db4738ab05bf88fabe7fd931a24fab2fa2060e73sewardj ~~~~~~~~~~~~~~~~~~~~~~~ 91405f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj The guest state must contain two pseudo-registers, guest_CMSTART 91505f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj and guest_CMLEN. These are used to specify guest address ranges, 91605f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj either of code to be invalidated, when used in conjunction with 91705f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj Ijk_InvalICache, or of d-cache ranges to be flushed, when used in 91805f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj conjunction with Ijk_FlushDCache. In such cases, the two _CM 91905f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj pseudo-regs should be filled in by the IR, and then an exit with 92005f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj one of the two abovementioned Ijk_ kinds should happen, so that the 92105f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj dispatcher can action them. Both pseudo-regs must have size equal 92205f5e0172384dd2983fb16fbb7deebd74d71cd35sewardj to the guest word size. 923ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj 924ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj The architecture must a third pseudo-register, guest_NRADDR, also 925ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj guest-word-sized. This is used to record the unredirected guest 926ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj address at the start of a translation whose start has been 927ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj redirected. By reading this pseudo-register shortly afterwards, 928ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj the translation can find out what the corresponding no-redirection 929ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj address was. Note, this is only set for wrap-style redirects, not 930ce02aa77bc02dbe225a068df0fb6b31faddedcdfsewardj for replace-style ones. 931db4738ab05bf88fabe7fd931a24fab2fa2060e73sewardj*/ 932887a11a609f3e61d2ae8fe4e67f176207715da7esewardj#endif /* ndef __LIBVEX_H */ 933ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj 934ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj/*---------------------------------------------------------------*/ 935887a11a609f3e61d2ae8fe4e67f176207715da7esewardj/*--- libvex.h ---*/ 936ac9af021b93dfe6f35c01d9c6fd15a3d67685843sewardj/*---------------------------------------------------------------*/ 937