Searched defs:left_op (Results 1 - 4 of 4) sorted by relevance
/art/compiler/dex/quick/mips/ |
H A D | int_mips.cc | 280 void MipsMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, argument 287 LIR* ne_branchover = OpCmpBranch(code, left_op, right_op, nullptr);
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/art/compiler/dex/quick/arm/ |
H A D | int_arm.cc | 217 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, argument 227 OpRegRegReg(kOpSub, rs_dest, left_op, right_op); 235 OpRegReg(kOpCmp, left_op, right_op); // Same?
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/art/compiler/dex/quick/arm64/ |
H A D | int_arm64.cc | 112 RegStorage left_op = RegStorage::InvalidReg(); // The operands. local 120 left_op = zero_reg; 122 left_op = rs_dest; 132 right_op = left_op; 135 right_op = left_op; 138 right_op = left_op; 141 // left_op is zero_reg. 165 OpRegRegImm(kOpAdd, t_reg2, left_op, delta); 178 DCHECK(left_op.Valid() && right_op.Valid()); 179 NewLIR4(is_wide ? WIDE(opcode) : opcode, rs_dest.GetReg(), left_op [all...] |
/art/compiler/dex/quick/x86/ |
H A D | int_x86.cc | 212 void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, argument 215 DCHECK(!left_op.IsPair() && !right_op.IsPair() && !rs_dest.IsPair()); 216 DCHECK(!left_op.IsFloat() && !right_op.IsFloat() && !rs_dest.IsFloat()); 225 const bool dest_intersect = IsSameReg(rs_dest, left_op) || IsSameReg(rs_dest, right_op); 232 OpRegReg(kOpCmp, left_op, right_op); 252 OpRegReg(kOpCmp, left_op, right_op); 261 LIR* cmp_branch = OpCmpBranch(code, left_op, right_op, nullptr);
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