Searched refs:false_val (Results 1 - 9 of 9) sorted by relevance
/art/compiler/dex/quick/arm64/ |
H A D | int_arm64.cc | 99 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode, argument 101 if (false_val == 0 || // 0 is better as first operand. 104 true_val == false_val + 1) { // Potentially Csinc. 106 std::swap(true_val, false_val); 125 if (false_val == 1) { 128 } else if (false_val == -1) { 131 } else if (false_val == true_val + 1) { 134 } else if (false_val == -true_val) { 137 } else if (false_val == ~true_val) { 143 LoadConstantNoClobber(rs_dest, false_val); [all...] |
H A D | codegen_arm64.h | 182 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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/art/compiler/dex/quick/arm/ |
H A D | int_arm.cc | 218 int32_t true_val, int32_t false_val, RegStorage rs_dest, 223 DCHECK(InexpensiveConstantInt(false_val)); 226 (false_val == 0 && code == kCondNe)) { 230 LoadConstant(rs_dest, code == kCondEq ? false_val : true_val); 238 LoadConstant(rs_dest, false_val); // .eq case - load true 255 int false_val = mir->dalvikInsn.vC; local 260 std::swap(true_val, false_val); 262 bool cheap_false_val = InexpensiveConstantInt(false_val); 267 LoadConstant(rl_result.reg, false_val); 273 LoadConstant(rl_result.reg, false_val); 217 GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, int32_t true_val, int32_t false_val, RegStorage rs_dest, RegisterClass dest_reg_class) argument [all...] |
H A D | codegen_arm.h | 181 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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/art/compiler/dex/quick/x86/ |
H A D | int_x86.cc | 213 int32_t true_val, int32_t false_val, RegStorage rs_dest, 220 if (true_val == false_val) { 227 const bool zero_one_case = (true_val == 0 && false_val == 1) || (true_val == 1 && false_val == 0); 244 if (false_val == 0 && dest_intersect) { 246 std::swap(true_val, false_val); 249 LoadConstantNoClobber(rs_dest, false_val); 254 LoadConstantNoClobber(rs_dest, false_val); 262 LoadConstantNoClobber(rs_dest, false_val); 288 int false_val local 212 GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, int32_t true_val, int32_t false_val, RegStorage rs_dest, RegisterClass dest_reg_class) argument [all...] |
H A D | codegen_x86.h | 272 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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/art/compiler/dex/quick/mips/ |
H A D | codegen_mips.h | 182 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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H A D | int_mips.cc | 281 int32_t true_val, int32_t false_val, RegStorage rs_dest, 288 LoadConstant(rs_dest, false_val); 280 GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, int32_t true_val, int32_t false_val, RegStorage rs_dest, RegisterClass dest_reg_class) argument
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/art/compiler/dex/quick/ |
H A D | mir_to_lir.h | 1364 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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