| /art/runtime/arch/arm/ |
| H A D | memcmp16_arm.S | 33 pld [r1, #0]
36 cmp r0, r1
56 pld [r1, #32]
59 ldrh ip, [r1], #2
78 ldrh ip, [r1], #2
91 eor r0, r3, r1
101 ldr ip, [r1]
107 pld [r1, #64]
109 ldr lr, [r1, #4]!
112 ldreq ip, [r1, #
[all...] |
| H A D | instruction_set_features_assembly_tests.S | 27 mov r1,#1
31 // sdiv r0,r1,r1 is two words: 0xfb91 0xf1f0. We need little endian.
|
| H A D | jni_entrypoints_arm.S | 24 push {r0, r1, r2, r3, lr} @ spill regs
27 .cfi_rel_offset r1, 4
38 pop {r0, r1, r2, r3, lr} @ restore regs
41 .cfi_restore r1
47 pop {r0, r1, r2, r3, pc} @ restore regs and return to caller to handle exception
|
| H A D | quick_entrypoints_arm.S | 110 push {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
112 .cfi_rel_offset r1, 0
153 pop {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves
154 .cfi_restore r1
187 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r0, r1 @ save callee saves for throw
195 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r0, r1 // save all registers as basis for long jump context
204 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r1, r2 // save all registers as basis for long jump context
205 mov r1, r9 @ pass Thread::Current
228 RETURN_OR_DELIVER_PENDING_EXCEPTION_REG r1
245 SETUP_REFS_ONLY_CALLEE_SAVE_FRAME r1, r
[all...] |
| /art/compiler/driver/ |
| H A D | compiler_driver.h | 702 static constexpr uint32_t r1 = 15; local
716 k = (k << r1) | (k >> (32 - r1));
737 k1 = (k1 << r1) | (k1 >> (32 - r1));
|
| /art/compiler/dex/quick/arm/ |
| H A D | arm_lir.h | 33 * r0-r1: As in C/C++ r0 is 32-bit return register and r0/r1 is 64-bit
48 * 5 core temps that codegen can use (r0, r1, r2, r3, r12)
63 * o r1-r3 will be used for up to the first 3 words of arguments
116 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1, enumerator in enum:art::ArmNativeRegisterPool
210 constexpr RegStorage rs_r1(RegStorage::kValid | r1);
302 // RegisterLocation templates return values (r0, r0/r1, s0, or d0).
|
| /art/runtime/gc/allocator/ |
| H A D | rosalloc.h | 409 bool operator()(const RosAlloc::Run* r1, const RosAlloc::Run* r2) const {
410 return r1 == r2;
|
| /art/compiler/dex/quick/x86/ |
| H A D | x86_lir.h | 38 * r1/ecx: caller | caller, arg4 | caller, arg1, scratch | caller, arg3, scratch
125 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1, enumerator in enum:art::X86NativeRegisterPool
127 rCX = r1,
230 constexpr RegStorage rs_r1(RegStorage::kValid | r1);
|
| /art/compiler/optimizing/ |
| H A D | code_generator_mips64.cc | 736 GpuRegister r1 = loc1.AsRegister<GpuRegister>(); local
739 __ Move(r2, r1);
740 __ Move(r1, TMP);
743 FpuRegister r1 = loc1.AsFpuRegister<FpuRegister>(); local
748 __ Dmfc1(AT, r1);
749 __ Dmtc1(TMP, r1);
|
| /art/test/082-inline-execute/src/ |
| H A D | Main.java | 1024 long r1 = Long.reverse(l1);
1041 return (r1 / i1) + (r2 / i2) + i3 + i4 + i5 + i6 + i7 + i8;
|
| /art/runtime/arch/mips/ |
| H A D | quick_entrypoints_mips.S | 375 move $v0, $zero # clear result registers r0 and r1
1081 * r0 holds the proxy method; r1, r2 and r3 may contain arguments.
1332 * r1: high word
|