target_x86.cc revision 60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "dex/reg_storage_eq.h" 24#include "mirror/array.h" 25#include "mirror/string.h" 26#include "x86_lir.h" 27 28namespace art { 29 30static constexpr RegStorage core_regs_arr_32[] = { 31 rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, 32}; 33static constexpr RegStorage core_regs_arr_64[] = { 34 rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, 35 rs_r8, rs_r9, rs_r10, rs_r11, rs_r12, rs_r13, rs_r14, rs_r15 36}; 37static constexpr RegStorage core_regs_arr_64q[] = { 38 rs_r0q, rs_r1q, rs_r2q, rs_r3q, rs_rX86_SP_64, rs_r5q, rs_r6q, rs_r7q, 39 rs_r8q, rs_r9q, rs_r10q, rs_r11q, rs_r12q, rs_r13q, rs_r14q, rs_r15q 40}; 41static constexpr RegStorage sp_regs_arr_32[] = { 42 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 43}; 44static constexpr RegStorage sp_regs_arr_64[] = { 45 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 46 rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 47}; 48static constexpr RegStorage dp_regs_arr_32[] = { 49 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 50}; 51static constexpr RegStorage dp_regs_arr_64[] = { 52 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 53 rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 54}; 55static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32}; 56static constexpr RegStorage reserved_regs_arr_64[] = {rs_rX86_SP_32}; 57static constexpr RegStorage reserved_regs_arr_64q[] = {rs_rX86_SP_64}; 58static constexpr RegStorage core_temps_arr_32[] = {rs_rAX, rs_rCX, rs_rDX, rs_rBX}; 59static constexpr RegStorage core_temps_arr_64[] = { 60 rs_rAX, rs_rCX, rs_rDX, rs_rSI, rs_rDI, 61 rs_r8, rs_r9, rs_r10, rs_r11 62}; 63static constexpr RegStorage core_temps_arr_64q[] = { 64 rs_r0q, rs_r1q, rs_r2q, rs_r6q, rs_r7q, 65 rs_r8q, rs_r9q, rs_r10q, rs_r11q 66}; 67static constexpr RegStorage sp_temps_arr_32[] = { 68 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 69}; 70static constexpr RegStorage sp_temps_arr_64[] = { 71 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 72 rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 73}; 74static constexpr RegStorage dp_temps_arr_32[] = { 75 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 76}; 77static constexpr RegStorage dp_temps_arr_64[] = { 78 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 79 rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 80}; 81 82static constexpr RegStorage xp_temps_arr_32[] = { 83 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 84}; 85static constexpr RegStorage xp_temps_arr_64[] = { 86 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 87 rs_xr8, rs_xr9, rs_xr10, rs_xr11, rs_xr12, rs_xr13, rs_xr14, rs_xr15 88}; 89 90static constexpr ArrayRef<const RegStorage> empty_pool; 91static constexpr ArrayRef<const RegStorage> core_regs_32(core_regs_arr_32); 92static constexpr ArrayRef<const RegStorage> core_regs_64(core_regs_arr_64); 93static constexpr ArrayRef<const RegStorage> core_regs_64q(core_regs_arr_64q); 94static constexpr ArrayRef<const RegStorage> sp_regs_32(sp_regs_arr_32); 95static constexpr ArrayRef<const RegStorage> sp_regs_64(sp_regs_arr_64); 96static constexpr ArrayRef<const RegStorage> dp_regs_32(dp_regs_arr_32); 97static constexpr ArrayRef<const RegStorage> dp_regs_64(dp_regs_arr_64); 98static constexpr ArrayRef<const RegStorage> reserved_regs_32(reserved_regs_arr_32); 99static constexpr ArrayRef<const RegStorage> reserved_regs_64(reserved_regs_arr_64); 100static constexpr ArrayRef<const RegStorage> reserved_regs_64q(reserved_regs_arr_64q); 101static constexpr ArrayRef<const RegStorage> core_temps_32(core_temps_arr_32); 102static constexpr ArrayRef<const RegStorage> core_temps_64(core_temps_arr_64); 103static constexpr ArrayRef<const RegStorage> core_temps_64q(core_temps_arr_64q); 104static constexpr ArrayRef<const RegStorage> sp_temps_32(sp_temps_arr_32); 105static constexpr ArrayRef<const RegStorage> sp_temps_64(sp_temps_arr_64); 106static constexpr ArrayRef<const RegStorage> dp_temps_32(dp_temps_arr_32); 107static constexpr ArrayRef<const RegStorage> dp_temps_64(dp_temps_arr_64); 108 109static constexpr ArrayRef<const RegStorage> xp_temps_32(xp_temps_arr_32); 110static constexpr ArrayRef<const RegStorage> xp_temps_64(xp_temps_arr_64); 111 112RegStorage rs_rX86_SP; 113 114X86NativeRegisterPool rX86_ARG0; 115X86NativeRegisterPool rX86_ARG1; 116X86NativeRegisterPool rX86_ARG2; 117X86NativeRegisterPool rX86_ARG3; 118X86NativeRegisterPool rX86_ARG4; 119X86NativeRegisterPool rX86_ARG5; 120X86NativeRegisterPool rX86_FARG0; 121X86NativeRegisterPool rX86_FARG1; 122X86NativeRegisterPool rX86_FARG2; 123X86NativeRegisterPool rX86_FARG3; 124X86NativeRegisterPool rX86_FARG4; 125X86NativeRegisterPool rX86_FARG5; 126X86NativeRegisterPool rX86_FARG6; 127X86NativeRegisterPool rX86_FARG7; 128X86NativeRegisterPool rX86_RET0; 129X86NativeRegisterPool rX86_RET1; 130X86NativeRegisterPool rX86_INVOKE_TGT; 131X86NativeRegisterPool rX86_COUNT; 132 133RegStorage rs_rX86_ARG0; 134RegStorage rs_rX86_ARG1; 135RegStorage rs_rX86_ARG2; 136RegStorage rs_rX86_ARG3; 137RegStorage rs_rX86_ARG4; 138RegStorage rs_rX86_ARG5; 139RegStorage rs_rX86_FARG0; 140RegStorage rs_rX86_FARG1; 141RegStorage rs_rX86_FARG2; 142RegStorage rs_rX86_FARG3; 143RegStorage rs_rX86_FARG4; 144RegStorage rs_rX86_FARG5; 145RegStorage rs_rX86_FARG6; 146RegStorage rs_rX86_FARG7; 147RegStorage rs_rX86_RET0; 148RegStorage rs_rX86_RET1; 149RegStorage rs_rX86_INVOKE_TGT; 150RegStorage rs_rX86_COUNT; 151 152RegLocation X86Mir2Lir::LocCReturn() { 153 return x86_loc_c_return; 154} 155 156RegLocation X86Mir2Lir::LocCReturnRef() { 157 return cu_->target64 ? x86_64_loc_c_return_ref : x86_loc_c_return_ref; 158} 159 160RegLocation X86Mir2Lir::LocCReturnWide() { 161 return cu_->target64 ? x86_64_loc_c_return_wide : x86_loc_c_return_wide; 162} 163 164RegLocation X86Mir2Lir::LocCReturnFloat() { 165 return x86_loc_c_return_float; 166} 167 168RegLocation X86Mir2Lir::LocCReturnDouble() { 169 return x86_loc_c_return_double; 170} 171 172// Return a target-dependent special register for 32-bit. 173RegStorage X86Mir2Lir::TargetReg32(SpecialTargetRegister reg) { 174 RegStorage res_reg = RegStorage::InvalidReg(); 175 switch (reg) { 176 case kSelf: res_reg = RegStorage::InvalidReg(); break; 177 case kSuspend: res_reg = RegStorage::InvalidReg(); break; 178 case kLr: res_reg = RegStorage::InvalidReg(); break; 179 case kPc: res_reg = RegStorage::InvalidReg(); break; 180 case kSp: res_reg = rs_rX86_SP; break; 181 case kArg0: res_reg = rs_rX86_ARG0; break; 182 case kArg1: res_reg = rs_rX86_ARG1; break; 183 case kArg2: res_reg = rs_rX86_ARG2; break; 184 case kArg3: res_reg = rs_rX86_ARG3; break; 185 case kArg4: res_reg = rs_rX86_ARG4; break; 186 case kArg5: res_reg = rs_rX86_ARG5; break; 187 case kFArg0: res_reg = rs_rX86_FARG0; break; 188 case kFArg1: res_reg = rs_rX86_FARG1; break; 189 case kFArg2: res_reg = rs_rX86_FARG2; break; 190 case kFArg3: res_reg = rs_rX86_FARG3; break; 191 case kFArg4: res_reg = rs_rX86_FARG4; break; 192 case kFArg5: res_reg = rs_rX86_FARG5; break; 193 case kFArg6: res_reg = rs_rX86_FARG6; break; 194 case kFArg7: res_reg = rs_rX86_FARG7; break; 195 case kRet0: res_reg = rs_rX86_RET0; break; 196 case kRet1: res_reg = rs_rX86_RET1; break; 197 case kInvokeTgt: res_reg = rs_rX86_INVOKE_TGT; break; 198 case kHiddenArg: res_reg = rs_rAX; break; 199 case kHiddenFpArg: DCHECK(!cu_->target64); res_reg = rs_fr0; break; 200 case kCount: res_reg = rs_rX86_COUNT; break; 201 default: res_reg = RegStorage::InvalidReg(); 202 } 203 return res_reg; 204} 205 206RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 207 LOG(FATAL) << "Do not use this function!!!"; 208 return RegStorage::InvalidReg(); 209} 210 211/* 212 * Decode the register id. 213 */ 214ResourceMask X86Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { 215 /* Double registers in x86 are just a single FP register. This is always just a single bit. */ 216 return ResourceMask::Bit( 217 /* FP register starts at bit position 16 */ 218 ((reg.IsFloat() || reg.StorageSize() > 8) ? kX86FPReg0 : 0) + reg.GetRegNum()); 219} 220 221ResourceMask X86Mir2Lir::GetPCUseDefEncoding() const { 222 /* 223 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 224 * able to clean up some of the x86/Arm_Mips differences 225 */ 226 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 227 return kEncodeNone; 228} 229 230void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, 231 ResourceMask* use_mask, ResourceMask* def_mask) { 232 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 233 DCHECK(!lir->flags.use_def_invalid); 234 235 // X86-specific resource map setup here. 236 if (flags & REG_USE_SP) { 237 use_mask->SetBit(kX86RegSP); 238 } 239 240 if (flags & REG_DEF_SP) { 241 def_mask->SetBit(kX86RegSP); 242 } 243 244 if (flags & REG_DEFA) { 245 SetupRegMask(def_mask, rs_rAX.GetReg()); 246 } 247 248 if (flags & REG_DEFD) { 249 SetupRegMask(def_mask, rs_rDX.GetReg()); 250 } 251 if (flags & REG_USEA) { 252 SetupRegMask(use_mask, rs_rAX.GetReg()); 253 } 254 255 if (flags & REG_USEC) { 256 SetupRegMask(use_mask, rs_rCX.GetReg()); 257 } 258 259 if (flags & REG_USED) { 260 SetupRegMask(use_mask, rs_rDX.GetReg()); 261 } 262 263 if (flags & REG_USEB) { 264 SetupRegMask(use_mask, rs_rBX.GetReg()); 265 } 266 267 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 268 if (lir->opcode == kX86RepneScasw) { 269 SetupRegMask(use_mask, rs_rAX.GetReg()); 270 SetupRegMask(use_mask, rs_rCX.GetReg()); 271 SetupRegMask(use_mask, rs_rDI.GetReg()); 272 SetupRegMask(def_mask, rs_rDI.GetReg()); 273 } 274 275 if (flags & USE_FP_STACK) { 276 use_mask->SetBit(kX86FPStack); 277 def_mask->SetBit(kX86FPStack); 278 } 279} 280 281/* For dumping instructions */ 282static const char* x86RegName[] = { 283 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 284 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 285}; 286 287static const char* x86CondName[] = { 288 "O", 289 "NO", 290 "B/NAE/C", 291 "NB/AE/NC", 292 "Z/EQ", 293 "NZ/NE", 294 "BE/NA", 295 "NBE/A", 296 "S", 297 "NS", 298 "P/PE", 299 "NP/PO", 300 "L/NGE", 301 "NL/GE", 302 "LE/NG", 303 "NLE/G" 304}; 305 306/* 307 * Interpret a format string and build a string no longer than size 308 * See format key in Assemble.cc. 309 */ 310std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 311 std::string buf; 312 size_t i = 0; 313 size_t fmt_len = strlen(fmt); 314 while (i < fmt_len) { 315 if (fmt[i] != '!') { 316 buf += fmt[i]; 317 i++; 318 } else { 319 i++; 320 DCHECK_LT(i, fmt_len); 321 char operand_number_ch = fmt[i]; 322 i++; 323 if (operand_number_ch == '!') { 324 buf += "!"; 325 } else { 326 int operand_number = operand_number_ch - '0'; 327 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 328 DCHECK_LT(i, fmt_len); 329 int operand = lir->operands[operand_number]; 330 switch (fmt[i]) { 331 case 'c': 332 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 333 buf += x86CondName[operand]; 334 break; 335 case 'd': 336 buf += StringPrintf("%d", operand); 337 break; 338 case 'q': { 339 int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 | 340 static_cast<uint32_t>(lir->operands[operand_number+1])); 341 buf +=StringPrintf("%" PRId64, value); 342 } 343 case 'p': { 344 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 345 buf += StringPrintf("0x%08x", tab_rec->offset); 346 break; 347 } 348 case 'r': 349 if (RegStorage::IsFloat(operand)) { 350 int fp_reg = RegStorage::RegNum(operand); 351 buf += StringPrintf("xmm%d", fp_reg); 352 } else { 353 int reg_num = RegStorage::RegNum(operand); 354 DCHECK_LT(static_cast<size_t>(reg_num), sizeof(x86RegName)); 355 buf += x86RegName[reg_num]; 356 } 357 break; 358 case 't': 359 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 360 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 361 lir->target); 362 break; 363 default: 364 buf += StringPrintf("DecodeError '%c'", fmt[i]); 365 break; 366 } 367 i++; 368 } 369 } 370 } 371 return buf; 372} 373 374void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, const ResourceMask& mask, const char *prefix) { 375 char buf[256]; 376 buf[0] = 0; 377 378 if (mask.Equals(kEncodeAll)) { 379 strcpy(buf, "all"); 380 } else { 381 char num[8]; 382 int i; 383 384 for (i = 0; i < kX86RegEnd; i++) { 385 if (mask.HasBit(i)) { 386 snprintf(num, arraysize(num), "%d ", i); 387 strcat(buf, num); 388 } 389 } 390 391 if (mask.HasBit(ResourceMask::kCCode)) { 392 strcat(buf, "cc "); 393 } 394 /* Memory bits */ 395 if (x86LIR && (mask.HasBit(ResourceMask::kDalvikReg))) { 396 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 397 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 398 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 399 } 400 if (mask.HasBit(ResourceMask::kLiteral)) { 401 strcat(buf, "lit "); 402 } 403 404 if (mask.HasBit(ResourceMask::kHeapRef)) { 405 strcat(buf, "heap "); 406 } 407 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 408 strcat(buf, "noalias "); 409 } 410 } 411 if (buf[0]) { 412 LOG(INFO) << prefix << ": " << buf; 413 } 414} 415 416void X86Mir2Lir::AdjustSpillMask() { 417 // Adjustment for LR spilling, x86 has no LR so nothing to do here 418 core_spill_mask_ |= (1 << rs_rRET.GetRegNum()); 419 num_core_spills_++; 420} 421 422RegStorage X86Mir2Lir::AllocateByteRegister() { 423 RegStorage reg = AllocTypedTemp(false, kCoreReg); 424 if (!cu_->target64) { 425 DCHECK_LT(reg.GetRegNum(), rs_rX86_SP.GetRegNum()); 426 } 427 return reg; 428} 429 430RegStorage X86Mir2Lir::Get128BitRegister(RegStorage reg) { 431 return GetRegInfo(reg)->FindMatchingView(RegisterInfo::k128SoloStorageMask)->GetReg(); 432} 433 434bool X86Mir2Lir::IsByteRegister(RegStorage reg) { 435 return cu_->target64 || reg.GetRegNum() < rs_rX86_SP.GetRegNum(); 436} 437 438/* Clobber all regs that might be used by an external C call */ 439void X86Mir2Lir::ClobberCallerSave() { 440 Clobber(rs_rAX); 441 Clobber(rs_rCX); 442 Clobber(rs_rDX); 443 Clobber(rs_rBX); 444 445 Clobber(rs_fr0); 446 Clobber(rs_fr1); 447 Clobber(rs_fr2); 448 Clobber(rs_fr3); 449 Clobber(rs_fr4); 450 Clobber(rs_fr5); 451 Clobber(rs_fr6); 452 Clobber(rs_fr7); 453 454 if (cu_->target64) { 455 Clobber(rs_r8); 456 Clobber(rs_r9); 457 Clobber(rs_r10); 458 Clobber(rs_r11); 459 460 Clobber(rs_fr8); 461 Clobber(rs_fr9); 462 Clobber(rs_fr10); 463 Clobber(rs_fr11); 464 Clobber(rs_fr12); 465 Clobber(rs_fr13); 466 Clobber(rs_fr14); 467 Clobber(rs_fr15); 468 } 469} 470 471RegLocation X86Mir2Lir::GetReturnWideAlt() { 472 RegLocation res = LocCReturnWide(); 473 DCHECK(res.reg.GetLowReg() == rs_rAX.GetReg()); 474 DCHECK(res.reg.GetHighReg() == rs_rDX.GetReg()); 475 Clobber(rs_rAX); 476 Clobber(rs_rDX); 477 MarkInUse(rs_rAX); 478 MarkInUse(rs_rDX); 479 MarkWide(res.reg); 480 return res; 481} 482 483RegLocation X86Mir2Lir::GetReturnAlt() { 484 RegLocation res = LocCReturn(); 485 res.reg.SetReg(rs_rDX.GetReg()); 486 Clobber(rs_rDX); 487 MarkInUse(rs_rDX); 488 return res; 489} 490 491/* To be used when explicitly managing register use */ 492void X86Mir2Lir::LockCallTemps() { 493 LockTemp(rs_rX86_ARG0); 494 LockTemp(rs_rX86_ARG1); 495 LockTemp(rs_rX86_ARG2); 496 LockTemp(rs_rX86_ARG3); 497 if (cu_->target64) { 498 LockTemp(rs_rX86_ARG4); 499 LockTemp(rs_rX86_ARG5); 500 LockTemp(rs_rX86_FARG0); 501 LockTemp(rs_rX86_FARG1); 502 LockTemp(rs_rX86_FARG2); 503 LockTemp(rs_rX86_FARG3); 504 LockTemp(rs_rX86_FARG4); 505 LockTemp(rs_rX86_FARG5); 506 LockTemp(rs_rX86_FARG6); 507 LockTemp(rs_rX86_FARG7); 508 } 509} 510 511/* To be used when explicitly managing register use */ 512void X86Mir2Lir::FreeCallTemps() { 513 FreeTemp(rs_rX86_ARG0); 514 FreeTemp(rs_rX86_ARG1); 515 FreeTemp(rs_rX86_ARG2); 516 FreeTemp(rs_rX86_ARG3); 517 if (cu_->target64) { 518 FreeTemp(rs_rX86_ARG4); 519 FreeTemp(rs_rX86_ARG5); 520 FreeTemp(rs_rX86_FARG0); 521 FreeTemp(rs_rX86_FARG1); 522 FreeTemp(rs_rX86_FARG2); 523 FreeTemp(rs_rX86_FARG3); 524 FreeTemp(rs_rX86_FARG4); 525 FreeTemp(rs_rX86_FARG5); 526 FreeTemp(rs_rX86_FARG6); 527 FreeTemp(rs_rX86_FARG7); 528 } 529} 530 531bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { 532 switch (opcode) { 533 case kX86LockCmpxchgMR: 534 case kX86LockCmpxchgAR: 535 case kX86LockCmpxchg64M: 536 case kX86LockCmpxchg64A: 537 case kX86XchgMR: 538 case kX86Mfence: 539 // Atomic memory instructions provide full barrier. 540 return true; 541 default: 542 break; 543 } 544 545 // Conservative if cannot prove it provides full barrier. 546 return false; 547} 548 549bool X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 550#if ANDROID_SMP != 0 551 // Start off with using the last LIR as the barrier. If it is not enough, then we will update it. 552 LIR* mem_barrier = last_lir_insn_; 553 554 bool ret = false; 555 /* 556 * According to the JSR-133 Cookbook, for x86 only StoreLoad barriers need memory fence. All other barriers 557 * (LoadLoad, LoadStore, StoreStore) are nops due to the x86 memory model. For those cases, all we need 558 * to ensure is that there is a scheduling barrier in place. 559 */ 560 if (barrier_kind == kStoreLoad) { 561 // If no LIR exists already that can be used a barrier, then generate an mfence. 562 if (mem_barrier == nullptr) { 563 mem_barrier = NewLIR0(kX86Mfence); 564 ret = true; 565 } 566 567 // If last instruction does not provide full barrier, then insert an mfence. 568 if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) { 569 mem_barrier = NewLIR0(kX86Mfence); 570 ret = true; 571 } 572 } 573 574 // Now ensure that a scheduling barrier is in place. 575 if (mem_barrier == nullptr) { 576 GenBarrier(); 577 } else { 578 // Mark as a scheduling barrier. 579 DCHECK(!mem_barrier->flags.use_def_invalid); 580 mem_barrier->u.m.def_mask = &kEncodeAll; 581 } 582 return ret; 583#else 584 return false; 585#endif 586} 587 588void X86Mir2Lir::CompilerInitializeRegAlloc() { 589 if (cu_->target64) { 590 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_64, core_regs_64q, sp_regs_64, 591 dp_regs_64, reserved_regs_64, reserved_regs_64q, 592 core_temps_64, core_temps_64q, sp_temps_64, dp_temps_64); 593 } else { 594 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_32, empty_pool, sp_regs_32, 595 dp_regs_32, reserved_regs_32, empty_pool, 596 core_temps_32, empty_pool, sp_temps_32, dp_temps_32); 597 } 598 599 // Target-specific adjustments. 600 601 // Add in XMM registers. 602 const ArrayRef<const RegStorage> *xp_temps = cu_->target64 ? &xp_temps_64 : &xp_temps_32; 603 for (RegStorage reg : *xp_temps) { 604 RegisterInfo* info = new (arena_) RegisterInfo(reg, GetRegMaskCommon(reg)); 605 reginfo_map_.Put(reg.GetReg(), info); 606 info->SetIsTemp(true); 607 } 608 609 // Alias single precision xmm to double xmms. 610 // TODO: as needed, add larger vector sizes - alias all to the largest. 611 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); 612 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 613 int sp_reg_num = info->GetReg().GetRegNum(); 614 RegStorage xp_reg = RegStorage::Solo128(sp_reg_num); 615 RegisterInfo* xp_reg_info = GetRegInfo(xp_reg); 616 // 128-bit xmm vector register's master storage should refer to itself. 617 DCHECK_EQ(xp_reg_info, xp_reg_info->Master()); 618 619 // Redirect 32-bit vector's master storage to 128-bit vector. 620 info->SetMaster(xp_reg_info); 621 622 RegStorage dp_reg = RegStorage::FloatSolo64(sp_reg_num); 623 RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); 624 // Redirect 64-bit vector's master storage to 128-bit vector. 625 dp_reg_info->SetMaster(xp_reg_info); 626 // Singles should show a single 32-bit mask bit, at first referring to the low half. 627 DCHECK_EQ(info->StorageMask(), 0x1U); 628 } 629 630 if (cu_->target64) { 631 // Alias 32bit W registers to corresponding 64bit X registers. 632 GrowableArray<RegisterInfo*>::Iterator w_it(®_pool_->core_regs_); 633 for (RegisterInfo* info = w_it.Next(); info != nullptr; info = w_it.Next()) { 634 int x_reg_num = info->GetReg().GetRegNum(); 635 RegStorage x_reg = RegStorage::Solo64(x_reg_num); 636 RegisterInfo* x_reg_info = GetRegInfo(x_reg); 637 // 64bit X register's master storage should refer to itself. 638 DCHECK_EQ(x_reg_info, x_reg_info->Master()); 639 // Redirect 32bit W master storage to 64bit X. 640 info->SetMaster(x_reg_info); 641 // 32bit W should show a single 32-bit mask bit, at first referring to the low half. 642 DCHECK_EQ(info->StorageMask(), 0x1U); 643 } 644 } 645 646 // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. 647 // TODO: adjust for x86/hard float calling convention. 648 reg_pool_->next_core_reg_ = 2; 649 reg_pool_->next_sp_reg_ = 2; 650 reg_pool_->next_dp_reg_ = 1; 651} 652 653int X86Mir2Lir::VectorRegisterSize() { 654 return 128; 655} 656 657int X86Mir2Lir::NumReservableVectorRegisters(bool fp_used) { 658 return fp_used ? 5 : 7; 659} 660 661void X86Mir2Lir::SpillCoreRegs() { 662 if (num_core_spills_ == 0) { 663 return; 664 } 665 // Spill mask not including fake return address register 666 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); 667 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); 668 for (int reg = 0; mask; mask >>= 1, reg++) { 669 if (mask & 0x1) { 670 StoreWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg)); 671 offset += GetInstructionSetPointerSize(cu_->instruction_set); 672 } 673 } 674} 675 676void X86Mir2Lir::UnSpillCoreRegs() { 677 if (num_core_spills_ == 0) { 678 return; 679 } 680 // Spill mask not including fake return address register 681 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); 682 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); 683 for (int reg = 0; mask; mask >>= 1, reg++) { 684 if (mask & 0x1) { 685 LoadWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg)); 686 offset += GetInstructionSetPointerSize(cu_->instruction_set); 687 } 688 } 689} 690 691bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 692 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 693} 694 695bool X86Mir2Lir::SupportsVolatileLoadStore(OpSize size) { 696 return true; 697} 698 699RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { 700 // X86_64 can handle any size. 701 if (cu_->target64) { 702 if (size == kReference) { 703 return kRefReg; 704 } 705 return kCoreReg; 706 } 707 708 if (UNLIKELY(is_volatile)) { 709 // On x86, atomic 64-bit load/store requires an fp register. 710 // Smaller aligned load/store is atomic for both core and fp registers. 711 if (size == k64 || size == kDouble) { 712 return kFPReg; 713 } 714 } 715 return RegClassBySize(size); 716} 717 718X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 719 : Mir2Lir(cu, mir_graph, arena), 720 base_of_code_(nullptr), store_method_addr_(false), store_method_addr_used_(false), 721 method_address_insns_(arena, 100, kGrowableArrayMisc), 722 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 723 call_method_insns_(arena, 100, kGrowableArrayMisc), 724 stack_decrement_(nullptr), stack_increment_(nullptr), 725 const_vectors_(nullptr) { 726 store_method_addr_used_ = false; 727 if (kIsDebugBuild) { 728 for (int i = 0; i < kX86Last; i++) { 729 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 730 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 731 << " is wrong: expecting " << i << ", seeing " 732 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 733 } 734 } 735 } 736 if (cu_->target64) { 737 rs_rX86_SP = rs_rX86_SP_64; 738 739 rs_rX86_ARG0 = rs_rDI; 740 rs_rX86_ARG1 = rs_rSI; 741 rs_rX86_ARG2 = rs_rDX; 742 rs_rX86_ARG3 = rs_rCX; 743 rs_rX86_ARG4 = rs_r8; 744 rs_rX86_ARG5 = rs_r9; 745 rs_rX86_FARG0 = rs_fr0; 746 rs_rX86_FARG1 = rs_fr1; 747 rs_rX86_FARG2 = rs_fr2; 748 rs_rX86_FARG3 = rs_fr3; 749 rs_rX86_FARG4 = rs_fr4; 750 rs_rX86_FARG5 = rs_fr5; 751 rs_rX86_FARG6 = rs_fr6; 752 rs_rX86_FARG7 = rs_fr7; 753 rX86_ARG0 = rDI; 754 rX86_ARG1 = rSI; 755 rX86_ARG2 = rDX; 756 rX86_ARG3 = rCX; 757 rX86_ARG4 = r8; 758 rX86_ARG5 = r9; 759 rX86_FARG0 = fr0; 760 rX86_FARG1 = fr1; 761 rX86_FARG2 = fr2; 762 rX86_FARG3 = fr3; 763 rX86_FARG4 = fr4; 764 rX86_FARG5 = fr5; 765 rX86_FARG6 = fr6; 766 rX86_FARG7 = fr7; 767 rs_rX86_INVOKE_TGT = rs_rDI; 768 } else { 769 rs_rX86_SP = rs_rX86_SP_32; 770 771 rs_rX86_ARG0 = rs_rAX; 772 rs_rX86_ARG1 = rs_rCX; 773 rs_rX86_ARG2 = rs_rDX; 774 rs_rX86_ARG3 = rs_rBX; 775 rs_rX86_ARG4 = RegStorage::InvalidReg(); 776 rs_rX86_ARG5 = RegStorage::InvalidReg(); 777 rs_rX86_FARG0 = rs_rAX; 778 rs_rX86_FARG1 = rs_rCX; 779 rs_rX86_FARG2 = rs_rDX; 780 rs_rX86_FARG3 = rs_rBX; 781 rs_rX86_FARG4 = RegStorage::InvalidReg(); 782 rs_rX86_FARG5 = RegStorage::InvalidReg(); 783 rs_rX86_FARG6 = RegStorage::InvalidReg(); 784 rs_rX86_FARG7 = RegStorage::InvalidReg(); 785 rX86_ARG0 = rAX; 786 rX86_ARG1 = rCX; 787 rX86_ARG2 = rDX; 788 rX86_ARG3 = rBX; 789 rX86_FARG0 = rAX; 790 rX86_FARG1 = rCX; 791 rX86_FARG2 = rDX; 792 rX86_FARG3 = rBX; 793 rs_rX86_INVOKE_TGT = rs_rAX; 794 // TODO(64): Initialize with invalid reg 795// rX86_ARG4 = RegStorage::InvalidReg(); 796// rX86_ARG5 = RegStorage::InvalidReg(); 797 } 798 rs_rX86_RET0 = rs_rAX; 799 rs_rX86_RET1 = rs_rDX; 800 rs_rX86_COUNT = rs_rCX; 801 rX86_RET0 = rAX; 802 rX86_RET1 = rDX; 803 rX86_INVOKE_TGT = rAX; 804 rX86_COUNT = rCX; 805 806 // Initialize the number of reserved vector registers 807 num_reserved_vector_regs_ = -1; 808} 809 810Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 811 ArenaAllocator* const arena) { 812 return new X86Mir2Lir(cu, mir_graph, arena); 813} 814 815// Not used in x86 816RegStorage X86Mir2Lir::LoadHelper(ThreadOffset<4> offset) { 817 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 818 return RegStorage::InvalidReg(); 819} 820 821// Not used in x86 822RegStorage X86Mir2Lir::LoadHelper(ThreadOffset<8> offset) { 823 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 824 return RegStorage::InvalidReg(); 825} 826 827LIR* X86Mir2Lir::CheckSuspendUsingLoad() { 828 LOG(FATAL) << "Unexpected use of CheckSuspendUsingLoad in x86"; 829 return nullptr; 830} 831 832uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 833 DCHECK(!IsPseudoLirOp(opcode)); 834 return X86Mir2Lir::EncodingMap[opcode].flags; 835} 836 837const char* X86Mir2Lir::GetTargetInstName(int opcode) { 838 DCHECK(!IsPseudoLirOp(opcode)); 839 return X86Mir2Lir::EncodingMap[opcode].name; 840} 841 842const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 843 DCHECK(!IsPseudoLirOp(opcode)); 844 return X86Mir2Lir::EncodingMap[opcode].fmt; 845} 846 847void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 848 // Can we do this directly to memory? 849 rl_dest = UpdateLocWide(rl_dest); 850 if ((rl_dest.location == kLocDalvikFrame) || 851 (rl_dest.location == kLocCompilerTemp)) { 852 int32_t val_lo = Low32Bits(value); 853 int32_t val_hi = High32Bits(value); 854 int r_base = rs_rX86_SP.GetReg(); 855 int displacement = SRegOffset(rl_dest.s_reg_low); 856 857 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 858 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); 859 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 860 false /* is_load */, true /* is64bit */); 861 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); 862 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 863 false /* is_load */, true /* is64bit */); 864 return; 865 } 866 867 // Just use the standard code to do the generation. 868 Mir2Lir::GenConstWide(rl_dest, value); 869} 870 871// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 872void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 873 LOG(INFO) << "location: " << loc.location << ',' 874 << (loc.wide ? " w" : " ") 875 << (loc.defined ? " D" : " ") 876 << (loc.is_const ? " c" : " ") 877 << (loc.fp ? " F" : " ") 878 << (loc.core ? " C" : " ") 879 << (loc.ref ? " r" : " ") 880 << (loc.high_word ? " h" : " ") 881 << (loc.home ? " H" : " ") 882 << ", low: " << static_cast<int>(loc.reg.GetLowReg()) 883 << ", high: " << static_cast<int>(loc.reg.GetHighReg()) 884 << ", s_reg: " << loc.s_reg_low 885 << ", orig: " << loc.orig_sreg; 886} 887 888void X86Mir2Lir::Materialize() { 889 // A good place to put the analysis before starting. 890 AnalyzeMIR(); 891 892 // Now continue with regular code generation. 893 Mir2Lir::Materialize(); 894} 895 896void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, 897 SpecialTargetRegister symbolic_reg) { 898 /* 899 * For x86, just generate a 32 bit move immediate instruction, that will be filled 900 * in at 'link time'. For now, put a unique value based on target to ensure that 901 * code deduplication works. 902 */ 903 int target_method_idx = target_method.dex_method_index; 904 const DexFile* target_dex_file = target_method.dex_file; 905 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 906 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 907 908 // Generate the move instruction with the unique pointer and save index, dex_file, and type. 909 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg, false).GetReg(), 910 static_cast<int>(target_method_id_ptr), target_method_idx, 911 WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 912 AppendLIR(move); 913 method_address_insns_.Insert(move); 914} 915 916void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 917 /* 918 * For x86, just generate a 32 bit move immediate instruction, that will be filled 919 * in at 'link time'. For now, put a unique value based on target to ensure that 920 * code deduplication works. 921 */ 922 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 923 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 924 925 // Generate the move instruction with the unique pointer and save index and type. 926 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg, false).GetReg(), 927 static_cast<int>(ptr), type_idx); 928 AppendLIR(move); 929 class_type_address_insns_.Insert(move); 930} 931 932LIR *X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { 933 /* 934 * For x86, just generate a 32 bit call relative instruction, that will be filled 935 * in at 'link time'. For now, put a unique value based on target to ensure that 936 * code deduplication works. 937 */ 938 int target_method_idx = target_method.dex_method_index; 939 const DexFile* target_dex_file = target_method.dex_file; 940 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 941 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 942 943 // Generate the call instruction with the unique pointer and save index, dex_file, and type. 944 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(target_method_id_ptr), 945 target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 946 AppendLIR(call); 947 call_method_insns_.Insert(call); 948 return call; 949} 950 951/* 952 * @brief Enter a 32 bit quantity into a buffer 953 * @param buf buffer. 954 * @param data Data value. 955 */ 956 957static void PushWord(std::vector<uint8_t>&buf, int32_t data) { 958 buf.push_back(data & 0xff); 959 buf.push_back((data >> 8) & 0xff); 960 buf.push_back((data >> 16) & 0xff); 961 buf.push_back((data >> 24) & 0xff); 962} 963 964void X86Mir2Lir::InstallLiteralPools() { 965 // These are handled differently for x86. 966 DCHECK(code_literal_list_ == nullptr); 967 DCHECK(method_literal_list_ == nullptr); 968 DCHECK(class_literal_list_ == nullptr); 969 970 // Align to 16 byte boundary. We have implicit knowledge that the start of the method is 971 // on a 4 byte boundary. How can I check this if it changes (other than aligned loads 972 // will fail at runtime)? 973 if (const_vectors_ != nullptr) { 974 int align_size = (16-4) - (code_buffer_.size() & 0xF); 975 if (align_size < 0) { 976 align_size += 16; 977 } 978 979 while (align_size > 0) { 980 code_buffer_.push_back(0); 981 align_size--; 982 } 983 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 984 PushWord(code_buffer_, p->operands[0]); 985 PushWord(code_buffer_, p->operands[1]); 986 PushWord(code_buffer_, p->operands[2]); 987 PushWord(code_buffer_, p->operands[3]); 988 } 989 } 990 991 // Handle the fixups for methods. 992 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 993 LIR* p = method_address_insns_.Get(i); 994 DCHECK_EQ(p->opcode, kX86Mov32RI); 995 uint32_t target_method_idx = p->operands[2]; 996 const DexFile* target_dex_file = 997 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); 998 999 // The offset to patch is the last 4 bytes of the instruction. 1000 int patch_offset = p->offset + p->flags.size - 4; 1001 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 1002 cu_->method_idx, cu_->invoke_type, 1003 target_method_idx, target_dex_file, 1004 static_cast<InvokeType>(p->operands[4]), 1005 patch_offset); 1006 } 1007 1008 // Handle the fixups for class types. 1009 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 1010 LIR* p = class_type_address_insns_.Get(i); 1011 DCHECK_EQ(p->opcode, kX86Mov32RI); 1012 uint32_t target_method_idx = p->operands[2]; 1013 1014 // The offset to patch is the last 4 bytes of the instruction. 1015 int patch_offset = p->offset + p->flags.size - 4; 1016 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 1017 cu_->method_idx, target_method_idx, patch_offset); 1018 } 1019 1020 // And now the PC-relative calls to methods. 1021 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 1022 LIR* p = call_method_insns_.Get(i); 1023 DCHECK_EQ(p->opcode, kX86CallI); 1024 uint32_t target_method_idx = p->operands[1]; 1025 const DexFile* target_dex_file = 1026 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); 1027 1028 // The offset to patch is the last 4 bytes of the instruction. 1029 int patch_offset = p->offset + p->flags.size - 4; 1030 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 1031 cu_->method_idx, cu_->invoke_type, 1032 target_method_idx, target_dex_file, 1033 static_cast<InvokeType>(p->operands[3]), 1034 patch_offset, -4 /* offset */); 1035 } 1036 1037 // And do the normal processing. 1038 Mir2Lir::InstallLiteralPools(); 1039} 1040 1041/* 1042 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 1043 * otherwise bails to standard library code. 1044 */ 1045bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 1046 ClobberCallerSave(); 1047 LockCallTemps(); // Using fixed registers 1048 1049 // EAX: 16 bit character being searched. 1050 // ECX: count: number of words to be searched. 1051 // EDI: String being searched. 1052 // EDX: temporary during execution. 1053 // EBX or R11: temporary during execution (depending on mode). 1054 1055 RegLocation rl_obj = info->args[0]; 1056 RegLocation rl_char = info->args[1]; 1057 RegLocation rl_start; // Note: only present in III flavor or IndexOf. 1058 RegStorage tmpReg = cu_->target64 ? rs_r11 : rs_rBX; 1059 1060 uint32_t char_value = 1061 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 1062 1063 if (char_value > 0xFFFF) { 1064 // We have to punt to the real String.indexOf. 1065 return false; 1066 } 1067 1068 // Okay, we are commited to inlining this. 1069 RegLocation rl_return = GetReturn(kCoreReg); 1070 RegLocation rl_dest = InlineTarget(info); 1071 1072 // Is the string non-NULL? 1073 LoadValueDirectFixed(rl_obj, rs_rDX); 1074 GenNullCheck(rs_rDX, info->opt_flags); 1075 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 1076 1077 // Does the character fit in 16 bits? 1078 LIR* slowpath_branch = nullptr; 1079 if (rl_char.is_const) { 1080 // We need the value in EAX. 1081 LoadConstantNoClobber(rs_rAX, char_value); 1082 } else { 1083 // Character is not a constant; compare at runtime. 1084 LoadValueDirectFixed(rl_char, rs_rAX); 1085 slowpath_branch = OpCmpImmBranch(kCondGt, rs_rAX, 0xFFFF, nullptr); 1086 } 1087 1088 // From here down, we know that we are looking for a char that fits in 16 bits. 1089 // Location of reference to data array within the String object. 1090 int value_offset = mirror::String::ValueOffset().Int32Value(); 1091 // Location of count within the String object. 1092 int count_offset = mirror::String::CountOffset().Int32Value(); 1093 // Starting offset within data array. 1094 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1095 // Start of char data with array_. 1096 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1097 1098 // Character is in EAX. 1099 // Object pointer is in EDX. 1100 1101 // We need to preserve EDI, but have no spare registers, so push it on the stack. 1102 // We have to remember that all stack addresses after this are offset by sizeof(EDI). 1103 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 1104 1105 // Compute the number of words to search in to rCX. 1106 Load32Disp(rs_rDX, count_offset, rs_rCX); 1107 LIR *length_compare = nullptr; 1108 int start_value = 0; 1109 bool is_index_on_stack = false; 1110 if (zero_based) { 1111 // We have to handle an empty string. Use special instruction JECXZ. 1112 length_compare = NewLIR0(kX86Jecxz8); 1113 } else { 1114 rl_start = info->args[2]; 1115 // We have to offset by the start index. 1116 if (rl_start.is_const) { 1117 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1118 start_value = std::max(start_value, 0); 1119 1120 // Is the start > count? 1121 length_compare = OpCmpImmBranch(kCondLe, rs_rCX, start_value, nullptr); 1122 1123 if (start_value != 0) { 1124 OpRegImm(kOpSub, rs_rCX, start_value); 1125 } 1126 } else { 1127 // Runtime start index. 1128 rl_start = UpdateLocTyped(rl_start, kCoreReg); 1129 if (rl_start.location == kLocPhysReg) { 1130 // Handle "start index < 0" case. 1131 OpRegReg(kOpXor, tmpReg, tmpReg); 1132 OpRegReg(kOpCmp, rl_start.reg, tmpReg); 1133 OpCondRegReg(kOpCmov, kCondLt, rl_start.reg, tmpReg); 1134 1135 // The length of the string should be greater than the start index. 1136 length_compare = OpCmpBranch(kCondLe, rs_rCX, rl_start.reg, nullptr); 1137 OpRegReg(kOpSub, rs_rCX, rl_start.reg); 1138 if (rl_start.reg == rs_rDI) { 1139 // The special case. We will use EDI further, so lets put start index to stack. 1140 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 1141 is_index_on_stack = true; 1142 } 1143 } else { 1144 // Load the start index from stack, remembering that we pushed EDI. 1145 int displacement = SRegOffset(rl_start.s_reg_low) + (cu_->target64 ? 2 : 1) * sizeof(uint32_t); 1146 { 1147 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1148 Load32Disp(rs_rX86_SP, displacement, tmpReg); 1149 } 1150 OpRegReg(kOpXor, rs_rDI, rs_rDI); 1151 OpRegReg(kOpCmp, tmpReg, rs_rDI); 1152 OpCondRegReg(kOpCmov, kCondLt, tmpReg, rs_rDI); 1153 1154 length_compare = OpCmpBranch(kCondLe, rs_rCX, tmpReg, nullptr); 1155 OpRegReg(kOpSub, rs_rCX, tmpReg); 1156 // Put the start index to stack. 1157 NewLIR1(kX86Push32R, tmpReg.GetReg()); 1158 is_index_on_stack = true; 1159 } 1160 } 1161 } 1162 DCHECK(length_compare != nullptr); 1163 1164 // ECX now contains the count in words to be searched. 1165 1166 // Load the address of the string into R11 or EBX (depending on mode). 1167 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1168 Load32Disp(rs_rDX, value_offset, rs_rDI); 1169 Load32Disp(rs_rDX, offset_offset, tmpReg); 1170 OpLea(tmpReg, rs_rDI, tmpReg, 1, data_offset); 1171 1172 // Now compute into EDI where the search will start. 1173 if (zero_based || rl_start.is_const) { 1174 if (start_value == 0) { 1175 OpRegCopy(rs_rDI, tmpReg); 1176 } else { 1177 NewLIR3(kX86Lea32RM, rs_rDI.GetReg(), tmpReg.GetReg(), 2 * start_value); 1178 } 1179 } else { 1180 if (is_index_on_stack == true) { 1181 // Load the start index from stack. 1182 NewLIR1(kX86Pop32R, rs_rDX.GetReg()); 1183 OpLea(rs_rDI, tmpReg, rs_rDX, 1, 0); 1184 } else { 1185 OpLea(rs_rDI, tmpReg, rl_start.reg, 1, 0); 1186 } 1187 } 1188 1189 // EDI now contains the start of the string to be searched. 1190 // We are all prepared to do the search for the character. 1191 NewLIR0(kX86RepneScasw); 1192 1193 // Did we find a match? 1194 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1195 1196 // yes, we matched. Compute the index of the result. 1197 // index = ((curr_ptr - orig_ptr) / 2) - 1. 1198 OpRegReg(kOpSub, rs_rDI, tmpReg); 1199 OpRegImm(kOpAsr, rs_rDI, 1); 1200 NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rs_rDI.GetReg(), -1); 1201 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1202 1203 // Failed to match; return -1. 1204 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1205 length_compare->target = not_found; 1206 failed_branch->target = not_found; 1207 LoadConstantNoClobber(rl_return.reg, -1); 1208 1209 // And join up at the end. 1210 all_done->target = NewLIR0(kPseudoTargetLabel); 1211 // Restore EDI from the stack. 1212 NewLIR1(kX86Pop32R, rs_rDI.GetReg()); 1213 1214 // Out of line code returns here. 1215 if (slowpath_branch != nullptr) { 1216 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1217 AddIntrinsicSlowPath(info, slowpath_branch, return_point); 1218 } 1219 1220 StoreValue(rl_dest, rl_return); 1221 return true; 1222} 1223 1224/* 1225 * @brief Enter an 'advance LOC' into the FDE buffer 1226 * @param buf FDE buffer. 1227 * @param increment Amount by which to increase the current location. 1228 */ 1229static void AdvanceLoc(std::vector<uint8_t>&buf, uint32_t increment) { 1230 if (increment < 64) { 1231 // Encoding in opcode. 1232 buf.push_back(0x1 << 6 | increment); 1233 } else if (increment < 256) { 1234 // Single byte delta. 1235 buf.push_back(0x02); 1236 buf.push_back(increment); 1237 } else if (increment < 256 * 256) { 1238 // Two byte delta. 1239 buf.push_back(0x03); 1240 buf.push_back(increment & 0xff); 1241 buf.push_back((increment >> 8) & 0xff); 1242 } else { 1243 // Four byte delta. 1244 buf.push_back(0x04); 1245 PushWord(buf, increment); 1246 } 1247} 1248 1249 1250std::vector<uint8_t>* X86CFIInitialization() { 1251 return X86Mir2Lir::ReturnCommonCallFrameInformation(); 1252} 1253 1254std::vector<uint8_t>* X86Mir2Lir::ReturnCommonCallFrameInformation() { 1255 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1256 1257 // Length of the CIE (except for this field). 1258 PushWord(*cfi_info, 16); 1259 1260 // CIE id. 1261 PushWord(*cfi_info, 0xFFFFFFFFU); 1262 1263 // Version: 3. 1264 cfi_info->push_back(0x03); 1265 1266 // Augmentation: empty string. 1267 cfi_info->push_back(0x0); 1268 1269 // Code alignment: 1. 1270 cfi_info->push_back(0x01); 1271 1272 // Data alignment: -4. 1273 cfi_info->push_back(0x7C); 1274 1275 // Return address register (R8). 1276 cfi_info->push_back(0x08); 1277 1278 // Initial return PC is 4(ESP): DW_CFA_def_cfa R4 4. 1279 cfi_info->push_back(0x0C); 1280 cfi_info->push_back(0x04); 1281 cfi_info->push_back(0x04); 1282 1283 // Return address location: 0(SP): DW_CFA_offset R8 1 (* -4);. 1284 cfi_info->push_back(0x2 << 6 | 0x08); 1285 cfi_info->push_back(0x01); 1286 1287 // And 2 Noops to align to 4 byte boundary. 1288 cfi_info->push_back(0x0); 1289 cfi_info->push_back(0x0); 1290 1291 DCHECK_EQ(cfi_info->size() & 3, 0U); 1292 return cfi_info; 1293} 1294 1295static void EncodeUnsignedLeb128(std::vector<uint8_t>& buf, uint32_t value) { 1296 uint8_t buffer[12]; 1297 uint8_t *ptr = EncodeUnsignedLeb128(buffer, value); 1298 for (uint8_t *p = buffer; p < ptr; p++) { 1299 buf.push_back(*p); 1300 } 1301} 1302 1303std::vector<uint8_t>* X86Mir2Lir::ReturnCallFrameInformation() { 1304 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1305 1306 // Generate the FDE for the method. 1307 DCHECK_NE(data_offset_, 0U); 1308 1309 // Length (will be filled in later in this routine). 1310 PushWord(*cfi_info, 0); 1311 1312 // CIE_pointer (can be filled in by linker); might be left at 0 if there is only 1313 // one CIE for the whole debug_frame section. 1314 PushWord(*cfi_info, 0); 1315 1316 // 'initial_location' (filled in by linker). 1317 PushWord(*cfi_info, 0); 1318 1319 // 'address_range' (number of bytes in the method). 1320 PushWord(*cfi_info, data_offset_); 1321 1322 // The instructions in the FDE. 1323 if (stack_decrement_ != nullptr) { 1324 // Advance LOC to just past the stack decrement. 1325 uint32_t pc = NEXT_LIR(stack_decrement_)->offset; 1326 AdvanceLoc(*cfi_info, pc); 1327 1328 // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. 1329 cfi_info->push_back(0x0e); 1330 EncodeUnsignedLeb128(*cfi_info, frame_size_); 1331 1332 // We continue with that stack until the epilogue. 1333 if (stack_increment_ != nullptr) { 1334 uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; 1335 AdvanceLoc(*cfi_info, new_pc - pc); 1336 1337 // We probably have code snippets after the epilogue, so save the 1338 // current state: DW_CFA_remember_state. 1339 cfi_info->push_back(0x0a); 1340 1341 // We have now popped the stack: DW_CFA_def_cfa_offset 4. There is only the return 1342 // PC on the stack now. 1343 cfi_info->push_back(0x0e); 1344 EncodeUnsignedLeb128(*cfi_info, 4); 1345 1346 // Everything after that is the same as before the epilogue. 1347 // Stack bump was followed by RET instruction. 1348 LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); 1349 if (post_ret_insn != nullptr) { 1350 pc = new_pc; 1351 new_pc = post_ret_insn->offset; 1352 AdvanceLoc(*cfi_info, new_pc - pc); 1353 // Restore the state: DW_CFA_restore_state. 1354 cfi_info->push_back(0x0b); 1355 } 1356 } 1357 } 1358 1359 // Padding to a multiple of 4 1360 while ((cfi_info->size() & 3) != 0) { 1361 // DW_CFA_nop is encoded as 0. 1362 cfi_info->push_back(0); 1363 } 1364 1365 // Set the length of the FDE inside the generated bytes. 1366 uint32_t length = cfi_info->size() - 4; 1367 (*cfi_info)[0] = length; 1368 (*cfi_info)[1] = length >> 8; 1369 (*cfi_info)[2] = length >> 16; 1370 (*cfi_info)[3] = length >> 24; 1371 return cfi_info; 1372} 1373 1374void X86Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { 1375 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { 1376 case kMirOpReserveVectorRegisters: 1377 ReserveVectorRegisters(mir); 1378 break; 1379 case kMirOpReturnVectorRegisters: 1380 ReturnVectorRegisters(); 1381 break; 1382 case kMirOpConstVector: 1383 GenConst128(bb, mir); 1384 break; 1385 case kMirOpMoveVector: 1386 GenMoveVector(bb, mir); 1387 break; 1388 case kMirOpPackedMultiply: 1389 GenMultiplyVector(bb, mir); 1390 break; 1391 case kMirOpPackedAddition: 1392 GenAddVector(bb, mir); 1393 break; 1394 case kMirOpPackedSubtract: 1395 GenSubtractVector(bb, mir); 1396 break; 1397 case kMirOpPackedShiftLeft: 1398 GenShiftLeftVector(bb, mir); 1399 break; 1400 case kMirOpPackedSignedShiftRight: 1401 GenSignedShiftRightVector(bb, mir); 1402 break; 1403 case kMirOpPackedUnsignedShiftRight: 1404 GenUnsignedShiftRightVector(bb, mir); 1405 break; 1406 case kMirOpPackedAnd: 1407 GenAndVector(bb, mir); 1408 break; 1409 case kMirOpPackedOr: 1410 GenOrVector(bb, mir); 1411 break; 1412 case kMirOpPackedXor: 1413 GenXorVector(bb, mir); 1414 break; 1415 case kMirOpPackedAddReduce: 1416 GenAddReduceVector(bb, mir); 1417 break; 1418 case kMirOpPackedReduce: 1419 GenReduceVector(bb, mir); 1420 break; 1421 case kMirOpPackedSet: 1422 GenSetVector(bb, mir); 1423 break; 1424 default: 1425 break; 1426 } 1427} 1428 1429void X86Mir2Lir::ReserveVectorRegisters(MIR* mir) { 1430 // We should not try to reserve twice without returning the registers 1431 DCHECK_NE(num_reserved_vector_regs_, -1); 1432 1433 int num_vector_reg = mir->dalvikInsn.vA; 1434 for (int i = 0; i < num_vector_reg; i++) { 1435 RegStorage xp_reg = RegStorage::Solo128(i); 1436 RegisterInfo *xp_reg_info = GetRegInfo(xp_reg); 1437 Clobber(xp_reg); 1438 1439 for (RegisterInfo *info = xp_reg_info->GetAliasChain(); 1440 info != nullptr; 1441 info = info->GetAliasChain()) { 1442 if (info->GetReg().IsSingle()) { 1443 reg_pool_->sp_regs_.Delete(info); 1444 } else { 1445 reg_pool_->dp_regs_.Delete(info); 1446 } 1447 } 1448 } 1449 1450 num_reserved_vector_regs_ = num_vector_reg; 1451} 1452 1453void X86Mir2Lir::ReturnVectorRegisters() { 1454 // Return all the reserved registers 1455 for (int i = 0; i < num_reserved_vector_regs_; i++) { 1456 RegStorage xp_reg = RegStorage::Solo128(i); 1457 RegisterInfo *xp_reg_info = GetRegInfo(xp_reg); 1458 1459 for (RegisterInfo *info = xp_reg_info->GetAliasChain(); 1460 info != nullptr; 1461 info = info->GetAliasChain()) { 1462 if (info->GetReg().IsSingle()) { 1463 reg_pool_->sp_regs_.Insert(info); 1464 } else { 1465 reg_pool_->dp_regs_.Insert(info); 1466 } 1467 } 1468 } 1469 1470 // We don't have anymore reserved vector registers 1471 num_reserved_vector_regs_ = -1; 1472} 1473 1474void X86Mir2Lir::GenConst128(BasicBlock* bb, MIR* mir) { 1475 store_method_addr_used_ = true; 1476 int type_size = mir->dalvikInsn.vB; 1477 // We support 128 bit vectors. 1478 DCHECK_EQ(type_size & 0xFFFF, 128); 1479 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); 1480 uint32_t *args = mir->dalvikInsn.arg; 1481 int reg = rs_dest.GetReg(); 1482 // Check for all 0 case. 1483 if (args[0] == 0 && args[1] == 0 && args[2] == 0 && args[3] == 0) { 1484 NewLIR2(kX86XorpsRR, reg, reg); 1485 return; 1486 } 1487 1488 // Append the mov const vector to reg opcode. 1489 AppendOpcodeWithConst(kX86MovupsRM, reg, mir); 1490} 1491 1492void X86Mir2Lir::AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) { 1493 // Okay, load it from the constant vector area. 1494 LIR *data_target = ScanVectorLiteral(mir); 1495 if (data_target == nullptr) { 1496 data_target = AddVectorLiteral(mir); 1497 } 1498 1499 // Address the start of the method. 1500 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 1501 if (rl_method.wide) { 1502 rl_method = LoadValueWide(rl_method, kCoreReg); 1503 } else { 1504 rl_method = LoadValue(rl_method, kCoreReg); 1505 } 1506 1507 // Load the proper value from the literal area. 1508 // We don't know the proper offset for the value, so pick one that will force 1509 // 4 byte offset. We will fix this up in the assembler later to have the right 1510 // value. 1511 ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); 1512 LIR *load = NewLIR2(opcode, reg, rl_method.reg.GetReg()); 1513 load->flags.fixup = kFixupLoad; 1514 load->target = data_target; 1515} 1516 1517void X86Mir2Lir::GenMoveVector(BasicBlock *bb, MIR *mir) { 1518 // We only support 128 bit registers. 1519 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1520 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); 1521 RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB); 1522 NewLIR2(kX86Mova128RR, rs_dest.GetReg(), rs_src.GetReg()); 1523} 1524 1525void X86Mir2Lir::GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir) { 1526 const int BYTE_SIZE = 8; 1527 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1528 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1529 RegStorage rs_src1_high_tmp = Get128BitRegister(AllocTempWide()); 1530 1531 /* 1532 * Emulate the behavior of a kSignedByte by separating out the 16 values in the two XMM 1533 * and multiplying 8 at a time before recombining back into one XMM register. 1534 * 1535 * let xmm1, xmm2 be real srcs (keep low bits of 16bit lanes) 1536 * xmm3 is tmp (operate on high bits of 16bit lanes) 1537 * 1538 * xmm3 = xmm1 1539 * xmm1 = xmm1 .* xmm2 1540 * xmm1 = xmm1 & 0x00ff00ff00ff00ff00ff00ff00ff00ff // xmm1 now has low bits 1541 * xmm3 = xmm3 .>> 8 1542 * xmm2 = xmm2 & 0xff00ff00ff00ff00ff00ff00ff00ff00 1543 * xmm2 = xmm2 .* xmm3 // xmm2 now has high bits 1544 * xmm1 = xmm1 | xmm2 // combine results 1545 */ 1546 1547 // Copy xmm1. 1548 NewLIR2(kX86Mova128RR, rs_src1_high_tmp.GetReg(), rs_dest_src1.GetReg()); 1549 1550 // Multiply low bits. 1551 NewLIR2(kX86PmullwRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1552 1553 // xmm1 now has low bits. 1554 AndMaskVectorRegister(rs_dest_src1, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF); 1555 1556 // Prepare high bits for multiplication. 1557 NewLIR2(kX86PsrlwRI, rs_src1_high_tmp.GetReg(), BYTE_SIZE); 1558 AndMaskVectorRegister(rs_src2, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00); 1559 1560 // Multiply high bits and xmm2 now has high bits. 1561 NewLIR2(kX86PmullwRR, rs_src2.GetReg(), rs_src1_high_tmp.GetReg()); 1562 1563 // Combine back into dest XMM register. 1564 NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1565} 1566 1567void X86Mir2Lir::GenMultiplyVector(BasicBlock *bb, MIR *mir) { 1568 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1569 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1570 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1571 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1572 int opcode = 0; 1573 switch (opsize) { 1574 case k32: 1575 opcode = kX86PmulldRR; 1576 break; 1577 case kSignedHalf: 1578 opcode = kX86PmullwRR; 1579 break; 1580 case kSingle: 1581 opcode = kX86MulpsRR; 1582 break; 1583 case kDouble: 1584 opcode = kX86MulpdRR; 1585 break; 1586 case kSignedByte: 1587 // HW doesn't support 16x16 byte multiplication so emulate it. 1588 GenMultiplyVectorSignedByte(bb, mir); 1589 return; 1590 default: 1591 LOG(FATAL) << "Unsupported vector multiply " << opsize; 1592 break; 1593 } 1594 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1595} 1596 1597void X86Mir2Lir::GenAddVector(BasicBlock *bb, MIR *mir) { 1598 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1599 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1600 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1601 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1602 int opcode = 0; 1603 switch (opsize) { 1604 case k32: 1605 opcode = kX86PadddRR; 1606 break; 1607 case kSignedHalf: 1608 case kUnsignedHalf: 1609 opcode = kX86PaddwRR; 1610 break; 1611 case kUnsignedByte: 1612 case kSignedByte: 1613 opcode = kX86PaddbRR; 1614 break; 1615 case kSingle: 1616 opcode = kX86AddpsRR; 1617 break; 1618 case kDouble: 1619 opcode = kX86AddpdRR; 1620 break; 1621 default: 1622 LOG(FATAL) << "Unsupported vector addition " << opsize; 1623 break; 1624 } 1625 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1626} 1627 1628void X86Mir2Lir::GenSubtractVector(BasicBlock *bb, MIR *mir) { 1629 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1630 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1631 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1632 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1633 int opcode = 0; 1634 switch (opsize) { 1635 case k32: 1636 opcode = kX86PsubdRR; 1637 break; 1638 case kSignedHalf: 1639 case kUnsignedHalf: 1640 opcode = kX86PsubwRR; 1641 break; 1642 case kUnsignedByte: 1643 case kSignedByte: 1644 opcode = kX86PsubbRR; 1645 break; 1646 case kSingle: 1647 opcode = kX86SubpsRR; 1648 break; 1649 case kDouble: 1650 opcode = kX86SubpdRR; 1651 break; 1652 default: 1653 LOG(FATAL) << "Unsupported vector subtraction " << opsize; 1654 break; 1655 } 1656 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1657} 1658 1659void X86Mir2Lir::GenShiftByteVector(BasicBlock *bb, MIR *mir) { 1660 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1661 RegStorage rs_tmp = Get128BitRegister(AllocTempWide()); 1662 1663 int opcode = 0; 1664 int imm = mir->dalvikInsn.vB; 1665 1666 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { 1667 case kMirOpPackedShiftLeft: 1668 opcode = kX86PsllwRI; 1669 break; 1670 case kMirOpPackedSignedShiftRight: 1671 opcode = kX86PsrawRI; 1672 break; 1673 case kMirOpPackedUnsignedShiftRight: 1674 opcode = kX86PsrlwRI; 1675 break; 1676 default: 1677 LOG(FATAL) << "Unsupported shift operation on byte vector " << opcode; 1678 break; 1679 } 1680 1681 /* 1682 * xmm1 will have low bits 1683 * xmm2 will have high bits 1684 * 1685 * xmm2 = xmm1 1686 * xmm1 = xmm1 .<< N 1687 * xmm2 = xmm2 && 0xFF00FF00FF00FF00FF00FF00FF00FF00 1688 * xmm2 = xmm2 .<< N 1689 * xmm1 = xmm1 | xmm2 1690 */ 1691 1692 // Copy xmm1. 1693 NewLIR2(kX86Mova128RR, rs_tmp.GetReg(), rs_dest_src1.GetReg()); 1694 1695 // Shift lower values. 1696 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1697 1698 // Mask bottom bits. 1699 AndMaskVectorRegister(rs_tmp, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00); 1700 1701 // Shift higher values. 1702 NewLIR2(opcode, rs_tmp.GetReg(), imm); 1703 1704 // Combine back into dest XMM register. 1705 NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_tmp.GetReg()); 1706} 1707 1708void X86Mir2Lir::GenShiftLeftVector(BasicBlock *bb, MIR *mir) { 1709 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1710 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1711 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1712 int imm = mir->dalvikInsn.vB; 1713 int opcode = 0; 1714 switch (opsize) { 1715 case k32: 1716 opcode = kX86PslldRI; 1717 break; 1718 case k64: 1719 opcode = kX86PsllqRI; 1720 break; 1721 case kSignedHalf: 1722 case kUnsignedHalf: 1723 opcode = kX86PsllwRI; 1724 break; 1725 case kSignedByte: 1726 case kUnsignedByte: 1727 GenShiftByteVector(bb, mir); 1728 return; 1729 default: 1730 LOG(FATAL) << "Unsupported vector shift left " << opsize; 1731 break; 1732 } 1733 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1734} 1735 1736void X86Mir2Lir::GenSignedShiftRightVector(BasicBlock *bb, MIR *mir) { 1737 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1738 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1739 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1740 int imm = mir->dalvikInsn.vB; 1741 int opcode = 0; 1742 switch (opsize) { 1743 case k32: 1744 opcode = kX86PsradRI; 1745 break; 1746 case kSignedHalf: 1747 case kUnsignedHalf: 1748 opcode = kX86PsrawRI; 1749 break; 1750 case kSignedByte: 1751 case kUnsignedByte: 1752 GenShiftByteVector(bb, mir); 1753 return; 1754 default: 1755 LOG(FATAL) << "Unsupported vector signed shift right " << opsize; 1756 break; 1757 } 1758 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1759} 1760 1761void X86Mir2Lir::GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir) { 1762 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1763 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1764 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1765 int imm = mir->dalvikInsn.vB; 1766 int opcode = 0; 1767 switch (opsize) { 1768 case k32: 1769 opcode = kX86PsrldRI; 1770 break; 1771 case k64: 1772 opcode = kX86PsrlqRI; 1773 break; 1774 case kSignedHalf: 1775 case kUnsignedHalf: 1776 opcode = kX86PsrlwRI; 1777 break; 1778 case kSignedByte: 1779 case kUnsignedByte: 1780 GenShiftByteVector(bb, mir); 1781 return; 1782 default: 1783 LOG(FATAL) << "Unsupported vector unsigned shift right " << opsize; 1784 break; 1785 } 1786 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1787} 1788 1789void X86Mir2Lir::GenAndVector(BasicBlock *bb, MIR *mir) { 1790 // We only support 128 bit registers. 1791 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1792 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1793 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1794 NewLIR2(kX86PandRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1795} 1796 1797void X86Mir2Lir::GenOrVector(BasicBlock *bb, MIR *mir) { 1798 // We only support 128 bit registers. 1799 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1800 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1801 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1802 NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1803} 1804 1805void X86Mir2Lir::GenXorVector(BasicBlock *bb, MIR *mir) { 1806 // We only support 128 bit registers. 1807 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1808 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); 1809 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); 1810 NewLIR2(kX86PxorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1811} 1812 1813void X86Mir2Lir::AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4) { 1814 MaskVectorRegister(kX86PandRM, rs_src1, m1, m2, m3, m4); 1815} 1816 1817void X86Mir2Lir::MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m0, uint32_t m1, uint32_t m2, uint32_t m3) { 1818 // Create temporary MIR as container for 128-bit binary mask. 1819 MIR const_mir; 1820 MIR* const_mirp = &const_mir; 1821 const_mirp->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpConstVector); 1822 const_mirp->dalvikInsn.arg[0] = m0; 1823 const_mirp->dalvikInsn.arg[1] = m1; 1824 const_mirp->dalvikInsn.arg[2] = m2; 1825 const_mirp->dalvikInsn.arg[3] = m3; 1826 1827 // Mask vector with const from literal pool. 1828 AppendOpcodeWithConst(opcode, rs_src1.GetReg(), const_mirp); 1829} 1830 1831void X86Mir2Lir::GenAddReduceVector(BasicBlock *bb, MIR *mir) { 1832 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1833 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1834 RegLocation rl_dest = mir_graph_->GetDest(mir); 1835 RegStorage rs_tmp; 1836 1837 int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8; 1838 int vec_unit_size = 0; 1839 int opcode = 0; 1840 int extr_opcode = 0; 1841 RegLocation rl_result; 1842 1843 switch (opsize) { 1844 case k32: 1845 extr_opcode = kX86PextrdRRI; 1846 opcode = kX86PhadddRR; 1847 vec_unit_size = 4; 1848 break; 1849 case kSignedByte: 1850 case kUnsignedByte: 1851 extr_opcode = kX86PextrbRRI; 1852 opcode = kX86PhaddwRR; 1853 vec_unit_size = 2; 1854 break; 1855 case kSignedHalf: 1856 case kUnsignedHalf: 1857 extr_opcode = kX86PextrwRRI; 1858 opcode = kX86PhaddwRR; 1859 vec_unit_size = 2; 1860 break; 1861 case kSingle: 1862 rl_result = EvalLoc(rl_dest, kFPReg, true); 1863 vec_unit_size = 4; 1864 for (int i = 0; i < 3; i++) { 1865 NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), rs_src1.GetReg()); 1866 NewLIR3(kX86ShufpsRRI, rs_src1.GetReg(), rs_src1.GetReg(), 0x39); 1867 } 1868 NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), rs_src1.GetReg()); 1869 StoreValue(rl_dest, rl_result); 1870 1871 // For single-precision floats, we are done here 1872 return; 1873 default: 1874 LOG(FATAL) << "Unsupported vector add reduce " << opsize; 1875 break; 1876 } 1877 1878 int elems = vec_bytes / vec_unit_size; 1879 1880 // Emulate horizontal add instruction by reducing 2 vectors with 8 values before adding them again 1881 // TODO is overflow handled correctly? 1882 if (opsize == kSignedByte || opsize == kUnsignedByte) { 1883 rs_tmp = Get128BitRegister(AllocTempWide()); 1884 1885 // tmp = xmm1 .>> 8. 1886 NewLIR2(kX86Mova128RR, rs_tmp.GetReg(), rs_src1.GetReg()); 1887 NewLIR2(kX86PsrlwRI, rs_tmp.GetReg(), 8); 1888 1889 // Zero extend low bits in xmm1. 1890 AndMaskVectorRegister(rs_src1, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF); 1891 } 1892 1893 while (elems > 1) { 1894 if (opsize == kSignedByte || opsize == kUnsignedByte) { 1895 NewLIR2(opcode, rs_tmp.GetReg(), rs_tmp.GetReg()); 1896 } 1897 NewLIR2(opcode, rs_src1.GetReg(), rs_src1.GetReg()); 1898 elems >>= 1; 1899 } 1900 1901 // Combine the results if we separated them. 1902 if (opsize == kSignedByte || opsize == kUnsignedByte) { 1903 NewLIR2(kX86PaddbRR, rs_src1.GetReg(), rs_tmp.GetReg()); 1904 } 1905 1906 // We need to extract to a GPR. 1907 RegStorage temp = AllocTemp(); 1908 NewLIR3(extr_opcode, temp.GetReg(), rs_src1.GetReg(), 0); 1909 1910 // Can we do this directly into memory? 1911 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 1912 if (rl_result.location == kLocPhysReg) { 1913 // Ensure res is in a core reg 1914 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1915 OpRegReg(kOpAdd, rl_result.reg, temp); 1916 StoreFinalValue(rl_dest, rl_result); 1917 } else { 1918 OpMemReg(kOpAdd, rl_result, temp.GetReg()); 1919 } 1920 1921 FreeTemp(temp); 1922} 1923 1924void X86Mir2Lir::GenReduceVector(BasicBlock *bb, MIR *mir) { 1925 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1926 RegLocation rl_dest = mir_graph_->GetDest(mir); 1927 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1928 int extract_index = mir->dalvikInsn.arg[0]; 1929 int extr_opcode = 0; 1930 RegLocation rl_result; 1931 bool is_wide = false; 1932 1933 switch (opsize) { 1934 case k32: 1935 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 1936 extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrdMRI : kX86PextrdRRI; 1937 break; 1938 case kSignedHalf: 1939 case kUnsignedHalf: 1940 rl_result= UpdateLocTyped(rl_dest, kCoreReg); 1941 extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrwMRI : kX86PextrwRRI; 1942 break; 1943 default: 1944 LOG(FATAL) << "Unsupported vector add reduce " << opsize; 1945 return; 1946 break; 1947 } 1948 1949 if (rl_result.location == kLocPhysReg) { 1950 NewLIR3(extr_opcode, rl_result.reg.GetReg(), rs_src1.GetReg(), extract_index); 1951 if (is_wide == true) { 1952 StoreFinalValue(rl_dest, rl_result); 1953 } else { 1954 StoreFinalValueWide(rl_dest, rl_result); 1955 } 1956 } else { 1957 int displacement = SRegOffset(rl_result.s_reg_low); 1958 LIR *l = NewLIR3(extr_opcode, rs_rX86_SP.GetReg(), displacement, rs_src1.GetReg()); 1959 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is_wide /* is_64bit */); 1960 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is_wide /* is_64bit */); 1961 } 1962} 1963 1964void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) { 1965 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); 1966 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); 1967 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); 1968 int op_low = 0, op_high = 0, imm = 0, op_mov = kX86MovdxrRR; 1969 RegisterClass reg_type = kCoreReg; 1970 1971 switch (opsize) { 1972 case k32: 1973 op_low = kX86PshufdRRI; 1974 break; 1975 case kSingle: 1976 op_low = kX86PshufdRRI; 1977 op_mov = kX86Mova128RR; 1978 reg_type = kFPReg; 1979 break; 1980 case k64: 1981 op_low = kX86PshufdRRI; 1982 imm = 0x44; 1983 break; 1984 case kDouble: 1985 op_low = kX86PshufdRRI; 1986 op_mov = kX86Mova128RR; 1987 reg_type = kFPReg; 1988 imm = 0x44; 1989 break; 1990 case kSignedByte: 1991 case kUnsignedByte: 1992 // Shuffle 8 bit value into 16 bit word. 1993 // We set val = val + (val << 8) below and use 16 bit shuffle. 1994 case kSignedHalf: 1995 case kUnsignedHalf: 1996 // Handles low quadword. 1997 op_low = kX86PshuflwRRI; 1998 // Handles upper quadword. 1999 op_high = kX86PshufdRRI; 2000 break; 2001 default: 2002 LOG(FATAL) << "Unsupported vector set " << opsize; 2003 break; 2004 } 2005 2006 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 2007 2008 // Load the value from the VR into the reg. 2009 if (rl_src.wide == 0) { 2010 rl_src = LoadValue(rl_src, reg_type); 2011 } else { 2012 rl_src = LoadValueWide(rl_src, reg_type); 2013 } 2014 2015 // If opsize is 8 bits wide then double value and use 16 bit shuffle instead. 2016 if (opsize == kSignedByte || opsize == kUnsignedByte) { 2017 RegStorage temp = AllocTemp(); 2018 // val = val + (val << 8). 2019 NewLIR2(kX86Mov32RR, temp.GetReg(), rl_src.reg.GetReg()); 2020 NewLIR2(kX86Sal32RI, temp.GetReg(), 8); 2021 NewLIR2(kX86Or32RR, rl_src.reg.GetReg(), temp.GetReg()); 2022 FreeTemp(temp); 2023 } 2024 2025 // Load the value into the XMM register. 2026 NewLIR2(op_mov, rs_dest.GetReg(), rl_src.reg.GetReg()); 2027 2028 // Now shuffle the value across the destination. 2029 NewLIR3(op_low, rs_dest.GetReg(), rs_dest.GetReg(), imm); 2030 2031 // And then repeat as needed. 2032 if (op_high != 0) { 2033 NewLIR3(op_high, rs_dest.GetReg(), rs_dest.GetReg(), imm); 2034 } 2035} 2036 2037LIR *X86Mir2Lir::ScanVectorLiteral(MIR *mir) { 2038 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); 2039 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 2040 if (args[0] == p->operands[0] && args[1] == p->operands[1] && 2041 args[2] == p->operands[2] && args[3] == p->operands[3]) { 2042 return p; 2043 } 2044 } 2045 return nullptr; 2046} 2047 2048LIR *X86Mir2Lir::AddVectorLiteral(MIR *mir) { 2049 LIR* new_value = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocData)); 2050 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); 2051 new_value->operands[0] = args[0]; 2052 new_value->operands[1] = args[1]; 2053 new_value->operands[2] = args[2]; 2054 new_value->operands[3] = args[3]; 2055 new_value->next = const_vectors_; 2056 if (const_vectors_ == nullptr) { 2057 estimated_native_code_size_ += 12; // Amount needed to align to 16 byte boundary. 2058 } 2059 estimated_native_code_size_ += 16; // Space for one vector. 2060 const_vectors_ = new_value; 2061 return new_value; 2062} 2063 2064// ------------ ABI support: mapping of args to physical registers ------------- 2065RegStorage X86Mir2Lir::InToRegStorageX86_64Mapper::GetNextReg(bool is_double_or_float, bool is_wide) { 2066 const SpecialTargetRegister coreArgMappingToPhysicalReg[] = {kArg1, kArg2, kArg3, kArg4, kArg5}; 2067 const int coreArgMappingToPhysicalRegSize = sizeof(coreArgMappingToPhysicalReg) / sizeof(SpecialTargetRegister); 2068 const SpecialTargetRegister fpArgMappingToPhysicalReg[] = {kFArg0, kFArg1, kFArg2, kFArg3, 2069 kFArg4, kFArg5, kFArg6, kFArg7}; 2070 const int fpArgMappingToPhysicalRegSize = sizeof(fpArgMappingToPhysicalReg) / sizeof(SpecialTargetRegister); 2071 2072 if (is_double_or_float) { 2073 if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { 2074 return ml_->TargetReg(fpArgMappingToPhysicalReg[cur_fp_reg_++], is_wide); 2075 } 2076 } else { 2077 if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { 2078 return ml_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++], is_wide); 2079 } 2080 } 2081 return RegStorage::InvalidReg(); 2082} 2083 2084RegStorage X86Mir2Lir::InToRegStorageMapping::Get(int in_position) { 2085 DCHECK(IsInitialized()); 2086 auto res = mapping_.find(in_position); 2087 return res != mapping_.end() ? res->second : RegStorage::InvalidReg(); 2088} 2089 2090void X86Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper) { 2091 DCHECK(mapper != nullptr); 2092 max_mapped_in_ = -1; 2093 is_there_stack_mapped_ = false; 2094 for (int in_position = 0; in_position < count; in_position++) { 2095 RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp, arg_locs[in_position].wide); 2096 if (reg.Valid()) { 2097 mapping_[in_position] = reg; 2098 max_mapped_in_ = std::max(max_mapped_in_, in_position); 2099 if (reg.Is64BitSolo()) { 2100 // We covered 2 args, so skip the next one 2101 in_position++; 2102 } 2103 } else { 2104 is_there_stack_mapped_ = true; 2105 } 2106 } 2107 initialized_ = true; 2108} 2109 2110RegStorage X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 2111 if (!cu_->target64) { 2112 return GetCoreArgMappingToPhysicalReg(arg_num); 2113 } 2114 2115 if (!in_to_reg_storage_mapping_.IsInitialized()) { 2116 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 2117 RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg]; 2118 2119 InToRegStorageX86_64Mapper mapper(this); 2120 in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper); 2121 } 2122 return in_to_reg_storage_mapping_.Get(arg_num); 2123} 2124 2125RegStorage X86Mir2Lir::GetCoreArgMappingToPhysicalReg(int core_arg_num) { 2126 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 2127 // Not used for 64-bit, TODO: Move X86_32 to the same framework 2128 switch (core_arg_num) { 2129 case 0: 2130 return rs_rX86_ARG1; 2131 case 1: 2132 return rs_rX86_ARG2; 2133 case 2: 2134 return rs_rX86_ARG3; 2135 default: 2136 return RegStorage::InvalidReg(); 2137 } 2138} 2139 2140// ---------End of ABI support: mapping of args to physical registers ------------- 2141 2142/* 2143 * If there are any ins passed in registers that have not been promoted 2144 * to a callee-save register, flush them to the frame. Perform initial 2145 * assignment of promoted arguments. 2146 * 2147 * ArgLocs is an array of location records describing the incoming arguments 2148 * with one location record per word of argument. 2149 */ 2150void X86Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 2151 if (!cu_->target64) return Mir2Lir::FlushIns(ArgLocs, rl_method); 2152 /* 2153 * Dummy up a RegLocation for the incoming Method* 2154 * It will attempt to keep kArg0 live (or copy it to home location 2155 * if promoted). 2156 */ 2157 2158 RegLocation rl_src = rl_method; 2159 rl_src.location = kLocPhysReg; 2160 rl_src.reg = TargetRefReg(kArg0); 2161 rl_src.home = false; 2162 MarkLive(rl_src); 2163 StoreValue(rl_method, rl_src); 2164 // If Method* has been promoted, explicitly flush 2165 if (rl_method.location == kLocPhysReg) { 2166 StoreRefDisp(rs_rX86_SP, 0, As32BitReg(TargetRefReg(kArg0)), kNotVolatile); 2167 } 2168 2169 if (cu_->num_ins == 0) { 2170 return; 2171 } 2172 2173 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 2174 /* 2175 * Copy incoming arguments to their proper home locations. 2176 * NOTE: an older version of dx had an issue in which 2177 * it would reuse static method argument registers. 2178 * This could result in the same Dalvik virtual register 2179 * being promoted to both core and fp regs. To account for this, 2180 * we only copy to the corresponding promoted physical register 2181 * if it matches the type of the SSA name for the incoming 2182 * argument. It is also possible that long and double arguments 2183 * end up half-promoted. In those cases, we must flush the promoted 2184 * half to memory as well. 2185 */ 2186 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2187 for (int i = 0; i < cu_->num_ins; i++) { 2188 // get reg corresponding to input 2189 RegStorage reg = GetArgMappingToPhysicalReg(i); 2190 2191 RegLocation* t_loc = &ArgLocs[i]; 2192 if (reg.Valid()) { 2193 // If arriving in register. 2194 2195 // We have already updated the arg location with promoted info 2196 // so we can be based on it. 2197 if (t_loc->location == kLocPhysReg) { 2198 // Just copy it. 2199 OpRegCopy(t_loc->reg, reg); 2200 } else { 2201 // Needs flush. 2202 if (t_loc->ref) { 2203 StoreRefDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, kNotVolatile); 2204 } else { 2205 StoreBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, 2206 kNotVolatile); 2207 } 2208 } 2209 } else { 2210 // If arriving in frame & promoted. 2211 if (t_loc->location == kLocPhysReg) { 2212 if (t_loc->ref) { 2213 LoadRefDisp(rs_rX86_SP, SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile); 2214 } else { 2215 LoadBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), t_loc->reg, 2216 t_loc->wide ? k64 : k32, kNotVolatile); 2217 } 2218 } 2219 } 2220 if (t_loc->wide) { 2221 // Increment i to skip the next one. 2222 i++; 2223 } 2224 } 2225} 2226 2227/* 2228 * Load up to 5 arguments, the first three of which will be in 2229 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 2230 * and as part of the load sequence, it must be replaced with 2231 * the target method pointer. Note, this may also be called 2232 * for "range" variants if the number of arguments is 5 or fewer. 2233 */ 2234int X86Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 2235 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 2236 const MethodReference& target_method, 2237 uint32_t vtable_idx, uintptr_t direct_code, 2238 uintptr_t direct_method, InvokeType type, bool skip_this) { 2239 if (!cu_->target64) { 2240 return Mir2Lir::GenDalvikArgsNoRange(info, 2241 call_state, pcrLabel, next_call_insn, 2242 target_method, 2243 vtable_idx, direct_code, 2244 direct_method, type, skip_this); 2245 } 2246 return GenDalvikArgsRange(info, 2247 call_state, pcrLabel, next_call_insn, 2248 target_method, 2249 vtable_idx, direct_code, 2250 direct_method, type, skip_this); 2251} 2252 2253/* 2254 * May have 0+ arguments (also used for jumbo). Note that 2255 * source virtual registers may be in physical registers, so may 2256 * need to be flushed to home location before copying. This 2257 * applies to arg3 and above (see below). 2258 * 2259 * Two general strategies: 2260 * If < 20 arguments 2261 * Pass args 3-18 using vldm/vstm block copy 2262 * Pass arg0, arg1 & arg2 in kArg1-kArg3 2263 * If 20+ arguments 2264 * Pass args arg19+ using memcpy block copy 2265 * Pass arg0, arg1 & arg2 in kArg1-kArg3 2266 * 2267 */ 2268int X86Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 2269 LIR** pcrLabel, NextCallInsn next_call_insn, 2270 const MethodReference& target_method, 2271 uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method, 2272 InvokeType type, bool skip_this) { 2273 if (!cu_->target64) { 2274 return Mir2Lir::GenDalvikArgsRange(info, call_state, 2275 pcrLabel, next_call_insn, 2276 target_method, 2277 vtable_idx, direct_code, direct_method, 2278 type, skip_this); 2279 } 2280 2281 /* If no arguments, just return */ 2282 if (info->num_arg_words == 0) 2283 return call_state; 2284 2285 const int start_index = skip_this ? 1 : 0; 2286 2287 InToRegStorageX86_64Mapper mapper(this); 2288 InToRegStorageMapping in_to_reg_storage_mapping; 2289 in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper); 2290 const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn(); 2291 const int size_of_the_last_mapped = last_mapped_in == -1 ? 1 : 2292 in_to_reg_storage_mapping.Get(last_mapped_in).Is64BitSolo() ? 2 : 1; 2293 int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + size_of_the_last_mapped); 2294 2295 // Fisrt of all, check whether it make sense to use bulk copying 2296 // Optimization is aplicable only for range case 2297 // TODO: make a constant instead of 2 2298 if (info->is_range && regs_left_to_pass_via_stack >= 2) { 2299 // Scan the rest of the args - if in phys_reg flush to memory 2300 for (int next_arg = last_mapped_in + size_of_the_last_mapped; next_arg < info->num_arg_words;) { 2301 RegLocation loc = info->args[next_arg]; 2302 if (loc.wide) { 2303 loc = UpdateLocWide(loc); 2304 if (loc.location == kLocPhysReg) { 2305 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2306 StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); 2307 } 2308 next_arg += 2; 2309 } else { 2310 loc = UpdateLoc(loc); 2311 if (loc.location == kLocPhysReg) { 2312 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2313 StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k32, kNotVolatile); 2314 } 2315 next_arg++; 2316 } 2317 } 2318 2319 // Logic below assumes that Method pointer is at offset zero from SP. 2320 DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0); 2321 2322 // The rest can be copied together 2323 int start_offset = SRegOffset(info->args[last_mapped_in + size_of_the_last_mapped].s_reg_low); 2324 int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + size_of_the_last_mapped, cu_->instruction_set); 2325 2326 int current_src_offset = start_offset; 2327 int current_dest_offset = outs_offset; 2328 2329 // Only davik regs are accessed in this loop; no next_call_insn() calls. 2330 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2331 while (regs_left_to_pass_via_stack > 0) { 2332 // This is based on the knowledge that the stack itself is 16-byte aligned. 2333 bool src_is_16b_aligned = (current_src_offset & 0xF) == 0; 2334 bool dest_is_16b_aligned = (current_dest_offset & 0xF) == 0; 2335 size_t bytes_to_move; 2336 2337 /* 2338 * The amount to move defaults to 32-bit. If there are 4 registers left to move, then do a 2339 * a 128-bit move because we won't get the chance to try to aligned. If there are more than 2340 * 4 registers left to move, consider doing a 128-bit only if either src or dest are aligned. 2341 * We do this because we could potentially do a smaller move to align. 2342 */ 2343 if (regs_left_to_pass_via_stack == 4 || 2344 (regs_left_to_pass_via_stack > 4 && (src_is_16b_aligned || dest_is_16b_aligned))) { 2345 // Moving 128-bits via xmm register. 2346 bytes_to_move = sizeof(uint32_t) * 4; 2347 2348 // Allocate a free xmm temp. Since we are working through the calling sequence, 2349 // we expect to have an xmm temporary available. AllocTempDouble will abort if 2350 // there are no free registers. 2351 RegStorage temp = AllocTempDouble(); 2352 2353 LIR* ld1 = nullptr; 2354 LIR* ld2 = nullptr; 2355 LIR* st1 = nullptr; 2356 LIR* st2 = nullptr; 2357 2358 /* 2359 * The logic is similar for both loads and stores. If we have 16-byte alignment, 2360 * do an aligned move. If we have 8-byte alignment, then do the move in two 2361 * parts. This approach prevents possible cache line splits. Finally, fall back 2362 * to doing an unaligned move. In most cases we likely won't split the cache 2363 * line but we cannot prove it and thus take a conservative approach. 2364 */ 2365 bool src_is_8b_aligned = (current_src_offset & 0x7) == 0; 2366 bool dest_is_8b_aligned = (current_dest_offset & 0x7) == 0; 2367 2368 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2369 if (src_is_16b_aligned) { 2370 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovA128FP); 2371 } else if (src_is_8b_aligned) { 2372 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovLo128FP); 2373 ld2 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset + (bytes_to_move >> 1), 2374 kMovHi128FP); 2375 } else { 2376 ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovU128FP); 2377 } 2378 2379 if (dest_is_16b_aligned) { 2380 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovA128FP); 2381 } else if (dest_is_8b_aligned) { 2382 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovLo128FP); 2383 st2 = OpMovMemReg(rs_rX86_SP, current_dest_offset + (bytes_to_move >> 1), 2384 temp, kMovHi128FP); 2385 } else { 2386 st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovU128FP); 2387 } 2388 2389 // TODO If we could keep track of aliasing information for memory accesses that are wider 2390 // than 64-bit, we wouldn't need to set up a barrier. 2391 if (ld1 != nullptr) { 2392 if (ld2 != nullptr) { 2393 // For 64-bit load we can actually set up the aliasing information. 2394 AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); 2395 AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, true); 2396 } else { 2397 // Set barrier for 128-bit load. 2398 ld1->u.m.def_mask = &kEncodeAll; 2399 } 2400 } 2401 if (st1 != nullptr) { 2402 if (st2 != nullptr) { 2403 // For 64-bit store we can actually set up the aliasing information. 2404 AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); 2405 AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, true); 2406 } else { 2407 // Set barrier for 128-bit store. 2408 st1->u.m.def_mask = &kEncodeAll; 2409 } 2410 } 2411 2412 // Free the temporary used for the data movement. 2413 FreeTemp(temp); 2414 } else { 2415 // Moving 32-bits via general purpose register. 2416 bytes_to_move = sizeof(uint32_t); 2417 2418 // Instead of allocating a new temp, simply reuse one of the registers being used 2419 // for argument passing. 2420 RegStorage temp = TargetReg(kArg3, false); 2421 2422 // Now load the argument VR and store to the outs. 2423 Load32Disp(rs_rX86_SP, current_src_offset, temp); 2424 Store32Disp(rs_rX86_SP, current_dest_offset, temp); 2425 } 2426 2427 current_src_offset += bytes_to_move; 2428 current_dest_offset += bytes_to_move; 2429 regs_left_to_pass_via_stack -= (bytes_to_move >> 2); 2430 } 2431 DCHECK_EQ(regs_left_to_pass_via_stack, 0); 2432 } 2433 2434 // Now handle rest not registers if they are 2435 if (in_to_reg_storage_mapping.IsThereStackMapped()) { 2436 RegStorage regSingle = TargetReg(kArg2, false); 2437 RegStorage regWide = TargetReg(kArg3, true); 2438 for (int i = start_index; 2439 i < last_mapped_in + size_of_the_last_mapped + regs_left_to_pass_via_stack; i++) { 2440 RegLocation rl_arg = info->args[i]; 2441 rl_arg = UpdateRawLoc(rl_arg); 2442 RegStorage reg = in_to_reg_storage_mapping.Get(i); 2443 if (!reg.Valid()) { 2444 int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set); 2445 2446 { 2447 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2448 if (rl_arg.wide) { 2449 if (rl_arg.location == kLocPhysReg) { 2450 StoreBaseDisp(rs_rX86_SP, out_offset, rl_arg.reg, k64, kNotVolatile); 2451 } else { 2452 LoadValueDirectWideFixed(rl_arg, regWide); 2453 StoreBaseDisp(rs_rX86_SP, out_offset, regWide, k64, kNotVolatile); 2454 } 2455 } else { 2456 if (rl_arg.location == kLocPhysReg) { 2457 StoreBaseDisp(rs_rX86_SP, out_offset, rl_arg.reg, k32, kNotVolatile); 2458 } else { 2459 LoadValueDirectFixed(rl_arg, regSingle); 2460 StoreBaseDisp(rs_rX86_SP, out_offset, regSingle, k32, kNotVolatile); 2461 } 2462 } 2463 } 2464 call_state = next_call_insn(cu_, info, call_state, target_method, 2465 vtable_idx, direct_code, direct_method, type); 2466 } 2467 if (rl_arg.wide) { 2468 i++; 2469 } 2470 } 2471 } 2472 2473 // Finish with mapped registers 2474 for (int i = start_index; i <= last_mapped_in; i++) { 2475 RegLocation rl_arg = info->args[i]; 2476 rl_arg = UpdateRawLoc(rl_arg); 2477 RegStorage reg = in_to_reg_storage_mapping.Get(i); 2478 if (reg.Valid()) { 2479 if (rl_arg.wide) { 2480 LoadValueDirectWideFixed(rl_arg, reg); 2481 } else { 2482 LoadValueDirectFixed(rl_arg, reg); 2483 } 2484 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 2485 direct_code, direct_method, type); 2486 } 2487 if (rl_arg.wide) { 2488 i++; 2489 } 2490 } 2491 2492 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 2493 direct_code, direct_method, type); 2494 if (pcrLabel) { 2495 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 2496 *pcrLabel = GenExplicitNullCheck(TargetRefReg(kArg1), info->opt_flags); 2497 } else { 2498 *pcrLabel = nullptr; 2499 // In lieu of generating a check for kArg1 being null, we need to 2500 // perform a load when doing implicit checks. 2501 RegStorage tmp = AllocTemp(); 2502 Load32Disp(TargetRefReg(kArg1), 0, tmp); 2503 MarkPossibleNullPointerException(info->opt_flags); 2504 FreeTemp(tmp); 2505 } 2506 } 2507 return call_state; 2508} 2509 2510} // namespace art 2511