3d21bdf8894e780d349c481e5c9e29fe1556051c |
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22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move mirror::ArtMethod to native Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 (cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33) Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d Fix some ArtMethod related bugs Added root visiting for runtime methods, not currently required since the GcRoots in these methods are null. Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes --trace run-tests 005, 044. Fixed optimizing compiler bug where we used a normal stack location instead of double on ARM64, this fixes the debuggable tests. TODO: Fix JDWP tests. Bug: 19264997 Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3 ART: Fix casts for 64-bit pointers on 32-bit compiler. Bug: 19264997 Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457 Fix JDWP tests after ArtMethod change Fixes Throwable::GetStackDepth for exception event detection after internal stack trace representation change. Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of proxy method. Bug: 19264997 Change-Id: I363e293796848c3ec491c963813f62d868da44d2 Fix accidental IMT and root marking regression Was always using the conflict trampoline. Also included fix for regression in GC time caused by extra roots. Most of the regression was IMT. Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to detached thread. EvaluateAndApplyChanges: From ~2500 -> ~1980 GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots Bug: 19264997 Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0 Fix bogus image test assert Previously we were comparing the size of the non moving space to size of the image file. Now we properly compare the size of the image space against the size of the image file. Bug: 19264997 Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a [MIPS64] Fix art_quick_invoke_stub argument offsets. ArtMethod reference's size got bigger, so we need to move other args and leave enough space for ArtMethod* and 'this' pointer. This fixes mips64 boot. Bug: 19264997 Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
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ba56d060116d6e145be348fa575314654c6b0572 |
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06-May-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Improve 32 bit long shift by 1. Also change FOO << 1 to FOO+FOO in the instruction simplifier. This is an architecture independent simplification, which helps 'long << 1' for 32 bit architectures. Generate an add/adc for long << 1 in x86, in case something is generated after the simplifier. Add test cases for the simplification. Change-Id: I0d512331ef13cc4ccf10c80f11c370a10ed02294 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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db216f4d49ea1561a74261c29f1264952232728a |
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05-May-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Relax the only one back-edge restriction. The rule is in the way for better register allocation, as it creates an artificial join point between multiple paths. Change-Id: Ia4392890f95bcea56d143138f28ddce6c572ad58
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7394569c9252b277710b2d7d3fc35fb0dd48fc4b |
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29-Apr-2015 |
Mark P Mendell <mark.p.mendell@intel.com> |
Revert "Revert "Revert "Revert "[optimizing] Improve x86 shifts"""" This reverts commit 2a7a1d7808f003bea908023ebd11eb442d2fca39. Fix the problem that a long long >> 63 got the wrong answer. The problem was that a shr was used instead of a sar. Change-Id: I0327f79c718016ddec9272a605fc50ec15ec4566
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2d27c8e338af7262dbd4aaa66127bb8fa1758b86 |
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28-Apr-2015 |
Roland Levillain <rpl@google.com> |
Refactor InvokeDexCallingConventionVisitor in Optimizing. Change-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34
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2a7a1d7808f003bea908023ebd11eb442d2fca39 |
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29-Apr-2015 |
Roland Levillain <rpl@google.com> |
Revert "Revert "Revert "[optimizing] Improve x86 shifts""" This reverts commit 9b95a057ee20e4b1ca2e9c663726482172dc9ba3. Reverting this CL as it breaks libcore tests: org.apache.harmony.tests.java.lang.DoubleTest#test_compare junit.framework.AssertionFailedError: compare() -0.0 should be less 0.0 at junit.framework.Assert.assertTrue(Assert.java:140) at org.apache.harmony.tests.java.lang.DoubleTest.test_compare(DoubleTest.java:258) org.apache.harmony.tests.java.lang.DoubleTest#test_compare FAIL (EXEC_FAILED) org.apache.harmony.tests.java.lang.DoubleTest#test_compareToLjava_lang_Double junit.framework.AssertionFailedError: Assert 2: compare() -0.0 should be less 0.0 at junit.framework.Assert.assertTrue(Assert.java:140) at org.apache.harmony.tests.java.lang.DoubleTest.test_compareToLjava_lang_Double(DoubleTest.java:1320) org.apache.harmony.tests.java.lang.DoubleTest#test_compareToLjava_lang_Double FAIL (EXEC_FAILED) Change-Id: I10f0ec8cc9495cc225fef1940b3f1a9fe87d996f
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9b95a057ee20e4b1ca2e9c663726482172dc9ba3 |
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29-Apr-2015 |
Roland Levillain <rpl@google.com> |
Revert "Revert "[optimizing] Improve x86 shifts"" This reverts commit f9aac1e9f442c2486cd54f045d43e15791601205. Don't use Location::Any() for the first input if the output is Location::SameAsFirstInput(). Change-Id: I400834052b114abf0d616da1b4b6506f7bba10ab
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3e3d73349a2de81d14e2279f60ffbd9ab3f3ac28 |
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28-Apr-2015 |
Roland Levillain <rpl@google.com> |
Have HInvoke instructions know their number of actual arguments. Add an art::HInvoke::GetNumberOfArguments routine so that art::HInvoke and its subclasses can return the number of actual arguments of the called method. Use it in code generators and intrinsics handlers. Consequently, no longer remove a clinit check as last input of a static invoke if it is still present during baseline code generation, but ensure that static invokes have no such check as last input in optimized compilations. Change-Id: Iaf9e07d1057a3b15b83d9638538c02b70211e476
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848f70a3d73833fc1bf3032a9ff6812e429661d9 |
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15-Jan-2014 |
Jeff Hao <jeffhao@google.com> |
Replace String CharArray with internal uint16_t array. Summary of high level changes: - Adds compiler inliner support to identify string init methods - Adds compiler support (quick & optimizing) with new invoke code path that calls method off the thread pointer - Adds thread entrypoints for all string init methods - Adds map to verifier to log when receiver of string init has been copied to other registers. used by compiler and interpreter Change-Id: I797b992a8feb566f9ad73060011ab6f51eb7ce01
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99dbd6883f5dab7743d5fb5d0ad2e82c75a7011e |
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22-Apr-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Handle x86 const length BoundsCheck Allow a constant length for BoundsCheck. Change-Id: I2c7adc6e733cf8ce6997aba76aa763d0835bd2d6 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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0379f82393237798616d485ad99952e73e480e12 |
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25-Apr-2015 |
Roland Levillain <rpl@google.com> |
Fix DCHECKs about clinit checks in Optimizing's code generators. These assertions are not true for the baseline compiler. As a temporary workaround, remove a clinit check as last input of a static invoke if it is still present at the stage of code generation. Change-Id: I5655f4a0873e2e7ee7790b6a341c18b4b7b52af1
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4c0eb42259d790fddcd9978b66328dbb3ab65615 |
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24-Apr-2015 |
Roland Levillain <rpl@google.com> |
Ensure inlined static calls perform clinit checks in Optimizing. Calls to static methods have implicit class initialization (clinit) checks of the method's declaring class in Optimizing. However, when such a static call is inlined, the implicit clinit check vanishes, possibly leading to an incorrect behavior. To ensure that inlining static methods does not change the behavior of a program, add explicit class initialization checks (art::HClinitCheck) as well as load class instructions (art::HLoadClass) as last input of static calls (art::HInvokeStaticOrDirect) in Optimizing' control flow graphs, when the declaring class is reachable and not known to be already initialized. Then when considering the inlining of a static method call, proceed only if the method has no implicit clinit check requirement. The added explicit clinit checks are already removed by the art::PrepareForRegisterAllocation visitor. This CL also extends this visitor to turn explicit clinit checks from static invokes into implicit ones after the inlining step, by removing the added art::HLoadClass nodes mentioned hereinbefore. Change-Id: I9ba452b8bd09ae1fdd9a3797ef556e3e7e19c651
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5ea536aa4a6414db01beaf6f8bd8cb9adc5cfc92 |
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20-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Remove ArtMethod* parameter from dex cache entry points. Load the ArtMethod* using an optimized stack walk instead. This reduces the size of the generated code. Three of the entry points are called only from a slow-path and the fourth (InitializeTypeAndVerifyAccess) is rare and already slow enough that the one or two extra loads (depending on whether we already have the ArtMethod* in a register) are insignificant. And as we're starting to use PC-relative addressing of the dex cache arrays (already done by Quick for the boot image), having the ArtMethod* in a register becomes less likely anyway. Change-Id: Ib19b9d204e355e13bf386662a8b158178bf8ad28
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af88835231c2508509eb19aa2d21b92879351962 |
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20-Apr-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Remove unnecessary null checks in CheckCast and InstanceOf Change-Id: I6fd81cabd8673be360f369e6318df0de8b18b634
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b3306642f42d47ddb4d021a2f48ce9b1bd235857 |
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20-Apr-2015 |
Calin Juravle <calin@google.com> |
[optimzing] Fix codegen bug and improve type propagation - don't bound the type if there are no relevant uses - insert the bound type in the bounded block (this allows for condition materialization without changing the logic there). - add more comments - add tests for BoundType generation - fix GenerateTestAndBranch Change-Id: I5c1fdda104da4a46775d207270220d410234a472
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232ade0b9401404ad4b61b1003551b58b96195a8 |
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20-Apr-2015 |
Roland Levillain <rpl@google.com> |
Revert "Revert "Optimizing: Fix long-to-fp conversion on x86."" This reverts commit 386ce406f150645158d6067c4e0a36565aefc44f. Bug: 20413424 Change-Id: I6e93ff132907f2653f1ae12d6676ff2298f62ca1
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27df758e2e7baebb6e3f393f9732fd0d064420c8 |
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17-Apr-2015 |
Calin Juravle <calin@google.com> |
[optimizing] Add memory barriers in constructors when needed If a class has final fields we must add a memory barrier before returning from constructor. This makes sure the fields are visible to other threads. Bug: 19851497 Change-Id: If8c485092fc512efb9636cd568cb0543fb27688e
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88c13cddc3a4184908662b0f3de796565d348c76 |
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14-Apr-2015 |
Alexandre Rames <alexandre.rames@arm.com> |
Opt compiler: Correctly require register or FPU register. Also add a check that location summary are correctly typed with the HInstruction. Change-Id: I699762ff4e8f4e321c7db01ea005236ea1934af9
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8693fe1eda2e37ad162d792e9e793827bfa1c236 |
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18-Apr-2015 |
Mingyao Yang <mingyao@google.com> |
RecordPcInfo() in GenerateStaticOrDirectCall() is misplaced on x86. GenerateStaticOrDirectCall() is invoked in intrinsics_x86.cc and RecordPcInfo() is already taken care of there. It should be moved to VisitInvokeStaticOrDirect() as done in other archs. Change-Id: Id08d84c9046e55dea9d8a8452c979294c4183150
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13b4718ecd52a674b25eac106e654d8e89872750 |
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15-Apr-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Remove DCHECKs for boolean type Since bool and int are interchangeable types, checking whether an input is kPrimBoolean can fail when replaced with 0/1 constant or a phi. This patch removes the problematic DCHECKs, adds a best-effort verification into SSAChecker but leaves the phi case empty until a suitable analysis is implemented. Change-Id: I31e8daf27dd33d2fd74049b82bed1cb7c240c8c6
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e14590bdfed24df30e6b7545fc819ba03ff8bba1 |
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15-Apr-2015 |
Guillaume Sanchez <guillaumesa@google.com> |
Revert "[optimizing] Improve x86 parallel moves/swaps" This reverts commit a5c19ce8d200d68a528f2ce0ebff989106c4a933. This commit introduces a performance regression on CaffeineLogic of 30%. Change-Id: I917e206e249d44e1748537bc1b2d31054ea4959d
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9021825d1e73998b99c81e89c73796f6f2845471 |
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15-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Type MoveOperands. The ParallelMoveResolver implementation needs to know if a move is for 64bits or not, to handle swaps correctly. Bug found, and test case courtesy of Serguei I. Katkov. Change-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506
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66d126ea06ce3f507d86ca5f0d1f752170ac9be1 |
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03-Apr-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Implement HBooleanNot instruction Optimizations simplifying operations on boolean values (boolean simplifier, instruction simplifier) can benefit from having a special HInstruction for negating booleans in order to perform more transforms and produce faster machine code. This patch implements HBooleanNot as 'x xor 1', assuming that booleans are 1-bit integers and allowing for a single-instruction negation on all supported platforms. Change-Id: I33a2649c1821255b18a86ca68ed16416063c739f
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386ce406f150645158d6067c4e0a36565aefc44f |
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13-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Optimizing: Fix long-to-fp conversion on x86." Test fails on arm. This reverts commit 2d45b4df3838d9c0e5a213305ccd1d7009e01437. Change-Id: Id2864917b52f7ffba459680303a2d15b34f16a4e
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2d45b4df3838d9c0e5a213305ccd1d7009e01437 |
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07-Apr-2015 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Optimizing: Fix long-to-fp conversion on x86. long-to-fp conversion implemented using SSE loses the precision. The test is included. CL uses FPU to provide the correct result. Change-Id: I8eaf3c46819a8cb52642a7e7d7c4e3e0edbc88db Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
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9d8606de5e274c00242ee73ffb693bc34589f184 |
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12-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Whitespace cleanup in DWARFReg helper functions. Change-Id: Iedc05969b05be6d93e40467ff23287faaae08fb3
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c34dc9362b9ec624b3bdd97d36b6b2098814cd73 |
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12-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Move 'ret' instruction generation inside GenerateFrameExit. Change-Id: I0c594d9a2356a006a5ce8dfd41d307cf7c3704ba
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f9aac1e9f442c2486cd54f045d43e15791601205 |
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10-Apr-2015 |
Roland Levillain <rpl@google.com> |
Revert "[optimizing] Improve x86 shifts" This reverts commit 222fcf96c9b73bbb739012575e7e413caf9348ec. Reverting this CL as it is breaking a few tests (see http://build.chromium.org/p/client.art/builders/host-x86/builds/3251/steps/test%20optimizing/logs/stdio). Will investigate ASAP. Change-Id: Iddd8363e83a24aa49fbdf0f0c9dc12e63b4848de
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a5c19ce8d200d68a528f2ce0ebff989106c4a933 |
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01-Apr-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Improve x86 parallel moves/swaps Add a new constructor to ScratchRegisterScope that will supply a register if there is a free one, but not spill to force one. Use this to generated alternate code that doesn't use a temporary, as the spill/restore of a register generates extra instructions that aren't necessary on x86. Here is the benefit for a 32 bit memory-to-memory exchange with no free registers: < 50 push eax < 53 push ebx < 8B44244C mov eax, [esp + 76] < 8B5C246C mov ebx, [esp + 108] < 8944246C mov [esp + 108], eax < 895C244C mov [esp + 76], ebx < 5B pop ebx < 58 pop eax --- > FF742444 push [esp + 68] > FF742468 push [esp + 104] > 8F44244C pop [esp + 72] > 8F442468 pop [esp + 100] Avoid using xchg instruction, as it is slow on smaller processors. Change-Id: Id29ee3abd998577baaee552d55d23e60ae0c7871 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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222fcf96c9b73bbb739012575e7e413caf9348ec |
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30-Mar-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Improve x86 shifts Support memory operands for integer shifts. Generate better code for long shifts by constants. Change-Id: Icc92fa1b59cc280d4894af6f054e19b01977d5ce Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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b19930c5cba3cf662dce5ee057fcc9829b4cbb9c |
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09-Apr-2015 |
Guillaume Sanchez <guillaumesa@google.com> |
Follow up of "div/rem on x86 and x86_64", to tidy up the code a little. Change-Id: Ibf39cbc8ac1d773599d70be2cb1e941674b60f1d
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55501ce0db57bccfa23b0226faffc964203701f9 |
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08-Apr-2015 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Optimizing x86: Fix VisitArraySet for FP value Instruction generator expects to see FP value in XMM register, so update location builder to follow this. Change-Id: Idca4bb5cdb59249c77fcc6f76cdfcaba47222b3d Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
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c6b4dd8980350aaf250f0185f73e9c42ec17cd57 |
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07-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Implement CFI for Optimizing. CFI is necessary for stack unwinding in gdb, lldb, and libunwind. Change-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2
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0f88e87085b7cf6544dadff3f555773966a6853e |
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30-Mar-2015 |
Guillaume Sanchez <guillaumesa@google.com> |
Speedup div/rem by constants on x86 and x86_64 This is done using the algorithms in Hacker's Delight chapter 10. Change-Id: I7bacefe10067569769ed31a1f7834f796fb41119
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65b798ea10dd716c1bb3dda029f9bf255435af72 |
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06-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Enable more Clang warnings Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
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d43b3ac88cd46b8815890188c9c2b9a3f1564648 |
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01-Apr-2015 |
Mingyao Yang <mingyao@google.com> |
Revert "Revert "Deoptimization-based bce."" This reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430. Change-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006
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fb8d279bc011b31d0765dc7ca59afea324fd0d0c |
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01-Apr-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Implement x86/x86_64 math intrinsics Implement floor/ceil/round/RoundFloat on x86 and x86_64. Implement RoundDouble on x86_64. Add support for roundss and roundsd on both architectures. Support them in the disassembler as well. Add the instruction set features for x86, as the 'round' instruction is only supported if SSE4.1 is supported. Fix the tests to handle the addition of passing the instruction set features to x86 and x86_64. Add assembler tests for roundsd and roundss to x86_64 assembler tests. Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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2be48692eaa15c1d9f6ca1b3477bb75429843aff |
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01-Apr-2015 |
Mingyao Yang <mingyao@google.com> |
Clean up some RecordPcInfo in x86 slow paths. Calling codegen->RecordPcInfo() is likely to miss the third argument which is the slow path. And can cause deopt bugs later. The change calls the slow path's version of RecordPcInfo() in slow paths consistently. Change-Id: I41605f1b06ee2c6d3d7ffd5aa0c1366940b5a029
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42514f63aadfa9faec3718874db2108f3e89082d |
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31-Mar-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] trivial x86 explicit null check fix Change a cmp reg,0 to test reg,reg. I don't know that this code is even invoked. Change-Id: Ifddffcb22d8a4060b7abbea17d8e7168535e409b Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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d75948ac93a4a317feaf136cae78823071234ba5 |
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27-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Intrinsify String.compareTo. Change-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57
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09ed1a3125849ec6ac07cb886e3c502e1dcfada2 |
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25-Mar-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Implement X86 intrinsic support Implement the supported intrinsics for X86. Enhance the graph visualizer to print <U> for unallocated locations, to allow calling the graph dumper from within register allocation for debugging purposes. Change-Id: I3b0319eb70a9a4ea228f67065b4c52d13a1ae775 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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b2bd1c5f9171f35fa5b71ada42d1a9e11189428d |
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25-Mar-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Formatting and comments in BooleanSimplifier Change-Id: I9a5aa3f2aa8b0a29d7b0f1e5e247397cf8e9e379
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46e2a3915aa68c77426b71e95b9f3658250646b7 |
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16-Mar-2015 |
David Brazdil <dbrazdil@google.com> |
ART: Boolean simplifier The optimization recognizes the negation pattern generated by 'javac' and replaces it with a single condition. To this end, boolean values are now consistently assumed to be represented by an integer. This is a first optimization which deletes blocks from the HGraph and does so by replacing the corresponding entries with null. Hence, existing code can continue indexing the list of blocks with the block ID, but must check for null when iterating over the list. Change-Id: I7779da69cfa925c6521938ad0bcc11bc52335583
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da4d79bc9a4aeb9da7c6259ce4c9c1c3bf545eb8 |
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24-Mar-2015 |
Roland Levillain <rpl@google.com> |
Unify ART's various implementations of bit_cast. ART had several implementations of art::bit_cast: 1. one in runtime/base/casts.h, declared as: template <class Dest, class Source> inline Dest bit_cast(const Source& source); 2. another one in runtime/utils.h, declared as: template<typename U, typename V> static inline V bit_cast(U in); 3. and a third local version, in runtime/memory_region.h, similar to the previous one: template<typename Source, typename Destination> static Destination MemoryRegion::local_bit_cast(Source in); This CL removes versions 2. and 3. and changes their callers to use 1. instead. That version was chosen over the others as: - it was the oldest one in the code base; and - its syntax was closer to the standard C++ cast operators, as it supports the following use: bit_cast<Destination>(source) since `Source' can be deduced from `source'. Change-Id: I7334fd5d55bf0b8a0c52cb33cfbae6894ff83633
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0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430 |
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24-Mar-2015 |
Andreas Gampe <agampe@google.com> |
Revert "Deoptimization-based bce." This breaks compiling the core image: Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1. This reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129. Change-Id: Ieeb48797d451836ed506ccb940872f1443942e4e
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e295e6ec5beaea31be5d7d3c996cd8cfa2053129 |
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07-Mar-2015 |
Mingyao Yang <mingyao@google.com> |
Deoptimization-based bce. A mechanism is introduced that a runtime method can be called from code compiled with optimizing compiler to deoptimize into interpreter. This can be used to establish invariants in the managed code If the invariant does not hold at runtime, we will deoptimize and continue execution in the interpreter. This allows to optimize the managed code as if the invariant was proven during compile time. However, the exception will be thrown according to the semantics demanded by the spec. The invariant and optimization included in this patch are based on the length of an array. Given a set of array accesses with constant indices {c1, ..., cn}, we can optimize away all bounds checks iff all 0 <= min(ci) and max(ci) < array-length. The first can be proven statically. The second can be established with a deoptimization-based invariant. This replaces n bounds checks with one invariant check (plus slow-path code). Change-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569
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68e15009173f92fe717546a621b56413d5e9fba1 |
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17-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
PREOPT compiles using dex2oatd so don't emit debug instructions. Change-Id: I8d2ab8d956ad0ce313928918c658d49f490ad081
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3f6c7f61855172d3d9b7a9221baba76136088e7c |
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13-Mar-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Improve x86, x86_64 code Tweak the generated code to allow more use of constants and other small changes - Use test vs. compare to 0 - EmitMove of 0.0 should use xorps - VisitCompare kPrimLong can use constants - cmp/add/sub/mul on x86_64 can use constants if in int32_t range - long bit operations on x86 examine long constant high/low to optimize - Use 3 operand imulq if constant is in int32_t range Change-Id: I2dd4010fdffa129fe00905b0020590fe95f3f926 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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a8ac9130b872c080299afacf5dcaab513d13ea87 |
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13-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Refactor code in preparation of correct stack maps in slow path. Move the logic of saving/restoring live registers in slow path in the SlowPathCode method. Also add a RecordPcInfo helper to SlowPathCode, that will act as the placeholder of saving correct stack maps. Change-Id: I25c2bc7a642ef854bbc8a3eb570e5c8c8d2d030c
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234d69d075d1608f80adb647f7935077b62b6376 |
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09-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "[optimizing] Enable x86 long support."" This reverts commit 154552e666347d41d95d7619c6ee56249ff4feca. Change-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13
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154552e666347d41d95d7619c6ee56249ff4feca |
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06-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "[optimizing] Enable x86 long support." Few libcore failures. This reverts commit b4ba354cf8d22b261205494875cc014f18587b50. Change-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63
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2ed20afc6a1032e9e0cf919cb8d1b2b41e147182 |
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06-Mar-2015 |
Alexandre Rames <alexandre.rames@arm.com> |
Opt compiler: Clean the use of `virtual` and `OVERRIDE`. Change-Id: I806ec522b979334cee8f344fc95e8660c019160a
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b4ba354cf8d22b261205494875cc014f18587b50 |
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05-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
[optimizing] Enable x86 long support. Change-Id: I9006972a65a1f191c45691104a960366747f9d16
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5f8741860d465410bfed495dbb5f794590d338da |
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04-Mar-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Use callee-save registers for x86 Add ESI, EDI, EBP to available registers for non-baseline mode. Ensure that they aren't used when byte addressible registers are needed. Change-Id: Ie7130d4084c2ae9cfcd1e47c26eb3e5dcac1ebd6 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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f60c90ba8d1eee6f137a9e1a8a65e4d6bec35d6d |
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04-Mar-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Improve x86/x86_64 bound check code Don't force a constant index into a register just to compare to the array size. Allow a constant, and compare the constant to the size. Change-Id: I1c5732fbd42e63f7eac5c6219a19e9c431c22664 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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8928cab7c1a00f38b9c9a575998093d1b4138805 |
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04-Mar-2015 |
Mingyao Yang <mingyao@google.com> |
Add a change that should be part of "enhance gvn for commutative ops." Change-Id: Id1a30afb095b2c7e27a4ef8a1ef7293022c1aaed
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09b8463493aeb6ea2bce05f67d3457d5fcc8a7d9 |
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13-Feb-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing compiler] x86 goodness Implement the x86 version of https://android-review.googlesource.com/#/c/129560/, which made some enhancements to x86_64 code. - Use leal to implement 3 operand adds - Use testl rather than cmpl to 0 for registers - Use leaq for x86_64 for adds with constant in int32_t range Note: - The range and register allocator tests seem quite fragile. I had to change ADD_INT_LIT8 to XOR_INT_LIT8 for the register allocator test to get the code to run. It seems like this is a bit hard-coded to expected code generation sequences. I also changes BuildTwoAdds to BuildTwoSubs for the same reason. - For the live range test, I just changed the expected output, as the Locations were different. Change-Id: I402f2e95ddc8be4eb0befb3dae1b29feadfa29ab Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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d8ef2e991a1a65f47a26a1eb8c6b34c92b775d6b |
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24-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
not-int can also take non-int (byte and short) instructions. So we should use the result-type instead if the input type for knowning what instruction to use. Bug: 19454010 Change-Id: I88782ad27ae8c8e1b7868afede5057d26f14685a
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3173c8a11f7e23a89526e0ac3b21af5150966d74 |
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23-Feb-2015 |
Calin Juravle <calin@google.com> |
[optimizing] Fix float addition on x86. Change-Id: Ic39aaae89b8e5184b98001ea67221a3564e9334a
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b1498f67b444c897fa8f1530777ef118e05aa631 |
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16-Feb-2015 |
Calin Juravle <calin@google.com> |
Improve type propagation with if-contexts This works by adding a new instruction (HBoundType) after each `if (a instanceof ClassA) {}` to bound the type that `a` can take in the True- dominated blocks. Change-Id: Iae6a150b353486d4509b0d9b092164675732b90c
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d6138ef1ea13d07ae555542f8898b30d89e9ac9a |
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18-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Ensure the graph is correctly typed. We used to be forgiving because of HIntConstant(0) also being used for null. We now create a special HNullConstant for such uses. Also, we need to run the dead phi elimination twice during ssa building to ensure the correctness. Change-Id: If479efa3680d3358800aebb1cca692fa2d94f6e5
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c0572a451944f78397619dec34a38c36c11e9d2a |
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06-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Optimize leaf methods. Avoid suspend checks and stack changes when not needed. Change-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628
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cb1b00aedd94785e7599f18065a0b97b314e64f6 |
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28-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Use the non access check entrypoint when possible. Change-Id: I0b53d63141395e26816d5d2ce3fa6a297bb39b54
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3e6a3bf797e49b7f449256455c7e522e888687d8 |
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19-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Change x86 long param ABI (Quick/JNI/Opt) Ensure that we don't pass a long parameter across the last register and the stack: skip the register and allocate it only on the stack. This was requested to simplify the optimizing compiler code generation for x86. Optimizing (Baseline) compiler support for x86 longs: - Remove QuickParameter from Location, as there are no longer any uses of it. Bump oat.h version because we changed an ABI again. I changed IsParamALong() to return false for argument 0 (this argument). I am not sure why it differed from all other tests. I have not tested on ARM. I followed Nicolas's suggestions for setting the value of kSplitPairAcrossRegisterAndStack for different architectures. Change-Id: I2f16b33c1dac58dd4f4f503e9c2309d845f5fb7a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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1cf95287364948689f6a1a320567acd7728e94a3 |
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12-Dec-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Small optimization for recursive calls: avoid dex cache. Change-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6
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7c8d009552545e6f1fd6036721e4e42e3fd14697 |
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26-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing compiler] Support x86 hard float ABI Add support for the new ABI passing FP parameters in XMM0-XMM3. This allows us to optimize for x86 methods that don't use 'long'. Change-Id: Ic79a24767173451e7d7095ccc2a00b307593a868 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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966c3ae95d3c699ee9fbdbccc1acdaaf02325faf |
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27-Jan-2015 |
Mark P Mendell <mark.p.mendell@intel.com> |
Revert "Revert "ART: Implement X86 hard float (Quick/JNI/Baseline)"" This reverts commit 949c91fb91f40a4a80b2b492913cf8541008975e. This time, don't clobber EBX before saving it. Redo some of the macros to make register usage explicit. Change-Id: I8db8662877cd006816e16a28f42444ab7c36bfef
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949c91fb91f40a4a80b2b492913cf8541008975e |
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27-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "ART: Implement X86 hard float (Quick/JNI/Baseline)" And the 3 Mac build fixes. Fix conflicts in context_x86.* . This reverts commits 3d2c8e74c27efee58e24ec31441124f3f21384b9 , 34eda1dd66b92a361797c63d57fa19e83c08a1b4 , f601d1954348b71186fa160a0ae6a1f4f1c5aee6 , bc503348a1da573488503cc2819c9e30807bea31 . Bug: 19150481 Change-Id: I6650ee30a7d261159380fe2119e14379e4dc9970
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3d2c8e74c27efee58e24ec31441124f3f21384b9 |
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13-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Implement X86 hard float (Quick/JNI/Baseline) Use XMM0-XMM3 as parameter registers for float/double on X86. X86_64 already uses XMM0-XMM7 for parameters. Change the 'hidden' argument register from XMM0 to XMM7 to avoid a conflict. Add support for FPR save/restore in runtime/arch/x86. Minimal support for Optimizing baseline compiler. Bump the version in runtime/oat.h because this is an ABI change. Change-Id: Ia6fe150e8488b9e582b0178c0dda65fc81d5a8ba Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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d97dc40d186aec46bfd318b6a2026a98241d7e9c |
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22-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Support callee save floating point registers on x64. - Share the computation of core_spill_mask and fpu_spill_mask between backends. - Remove explicit stack overflow check support: we need to adjust them and since they are not tested, they will easily bitrot. Change-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a
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988939683c26c0b1c8808fc206add6337319509a |
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21-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Enable core callee-save on x64. Will work on other architectures and FP support in other CLs. Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d
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fa93b504b324784dd9a96e28e6e8f3f1b1ac456a |
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21-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Do not use HNot for creating !bool. HNot folds to ~, not !. Change-Id: I681f968449a2ade7110b2f316146ad16ba5da74c
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77520bca97ec44e3758510cebd0f20e3bb4584ea |
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12-Jan-2015 |
Calin Juravle <calin@google.com> |
Record implicit null checks at the actual invoke time. ImplicitNullChecks are recorded only for instructions directly (see NB below) preceeded by NullChecks in the graph. This way we avoid recording redundant safepoints and minimize the code size increase. NB: ParallalelMoves might be inserted by the register allocator between the NullChecks and their uses. These modify the environment and the correct action would be to reverse their modification. This will be addressed in a follow-up CL. Change-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898
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24f2dfae084b2382c053f5d688fd6bb26cb8a328 |
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15-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing compiler] Implement inline x86 FP '%' Replace the calls to fmod/fmodf by inline code as is done in the Quick compiler. Remove the quick fmod/fmodf runtime entries, as they are no longer in use. 64 bit code generator Move() routine needed to be enhanced to handle constants, as Location::Any() allows them to be generated. Change-Id: I6b6a42f6faeed4b0b3c940453e487daf5b25d184 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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93edf73a5fecd526920fbd870068fa592376ac8a |
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20-Jan-2015 |
Calin Juravle <calin@google.com> |
Use CompilerOptions for implicit stack overflow checks Change-Id: I52744382a7e3d2c6c11a43e027d87bf43ec4e62b
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cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f |
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08-Jan-2015 |
Calin Juravle <calin@google.com> |
Add implicit null checks for the optimizing compiler - for backends: arm, arm64, x86, x86_64 - fixed parameter passing for CodeGenerator - 003-omnibus-opcodes test verifies that NullPointerExceptions work as expected Change-Id: I1b302acd353342504716c9169a80706cf3aba2c8
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42d1f5f006c8bdbcbf855c53036cd50f9c69753e |
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16-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Do not use register pair in a parallel move. The ParallelMoveResolver does not work with pairs. Instead, decompose the pair into two individual moves. Change-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f
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71fb52fee246b7d511f520febbd73dc7a9bbca79 |
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30-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Optimizing compiler intrinsics Add intrinsics infrastructure to the optimizing compiler. Add almost all intrinsics supported by Quick to the x86-64 backend. Further intrinsics require more assembler support. Change-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807
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425f239c291d435f519a1cf4bdd9ccc9a2c0c070 |
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08-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix handling of long argument spanning register/memory. Comment in arm_lir.h says: * If a 64-bit argument would span the register/memory argument * boundary, it will instead be fully passed in the frame. This change implements such logic for all platforms. We still need to pass the low part in register as well because I haven't ported the jni compilers (x86 and mips) to it. Once the jni compilers are updated, we can remove the register assignment. Note that this greatly simplifies optimizing's register allocator by not having to understand a long spanning register and memory. Change-Id: I59706ca5d47269fc46e5489ac99bd6576e87e7f3
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1cc7dbabd03e0a6c09d68161417a21bd6f9df371 |
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18-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Reorder entrypoint argument order Shuffle the ArtMethod* referrer backwards for easier removal. Clean up ARM & MIPS assembly code. Change some macros to make future changes easier. Change-Id: Ie2862b68bd6e519438e83eecd9e1611df51d7945
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52c489645b6e9ae33623f1ec24143cde5444906e |
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16-Dec-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add support for volatile - for backends: arm, x86, x86_64 - added necessary instructions to assemblies - clean up code gen for field set/get - fixed InstructionDataEquals for some instructions - fixed comments in compiler_enums * 003-opcode test verifies basic volatile functionality Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
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5b4b898ed8725242ee6b7229b94467c3ea3054c8 |
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18-Dec-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Don't block quick callee saved registers for optimizing." X64 has one libcore test failing, and codegen_test on arm is failing. This reverts commit 6004796d6c630696127df2494dcd4f30d1367a34. Change-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f
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6004796d6c630696127df2494dcd4f30d1367a34 |
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15-Dec-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Don't block quick callee saved registers for optimizing. This change builds on: https://android-review.googlesource.com/#/c/118983/ - Also fix x86_64 assembler bug triggered by this change. - Fix (and improve) x86's backend byte register usage. - Fix a bug in baseline register allocator: a fixed out register must prevent inputs from allocating it. Change-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad
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4e44c829e282b3979a73bfcba92510e64fbec209 |
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17-Dec-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Small optimization for recursive calls: avoid dex cache." Fails on target. This reverts commit 390f59f9bec64fd81b05e796dfaeb03ab6d4cc81. Change-Id: Ic3865b8897068ba20df0fbc2bcf561faf6c290c1
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390f59f9bec64fd81b05e796dfaeb03ab6d4cc81 |
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12-Dec-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Small optimization for recursive calls: avoid dex cache. Change-Id: Ic4054b6c38f0a2a530ba6ef747647f86cee0b1b8
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e53798a7e3267305f696bf658e418c92e63e0834 |
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01-Dec-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Inlining support in optimizing. Currently only inlines simple things that don't require an environment, such as: - Returning a constant. - Returning a parameter. - Returning an arithmetic operation. Change-Id: Ie844950cb44f69e104774a3cf7a8dea66bc85661
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486cc19e1e2eca4231f760117e95090c03e2d8c6 |
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08-Dec-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Explicitly mask constants in shift operations. The assemblers expect an int8, so we mask ahead of calling them. Change-Id: Id668cda6853fa365ac02531bf7aae288cad20fcd
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d2ec87d84057174d4884ee16f652cbcfd31362e9 |
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08-Dec-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add REM_FLOAT and REM_DOUBLE - for arm, x86, x86_64 backends - reinstated fmod quick entry points for x86. This is a partial revert of bd3682eada753de52975ae2b4a712bd87dc139a6 which added inline assembly for floting point rem on x86. Note that Quick still uses the inline version. - fix rem tests for longs Change-Id: I73be19a9f2f2bcf3f718d9ca636e67bdd72b5440
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4c0b61f506644bb6b647be05d02c5fb45b9ceb48 |
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05-Dec-2014 |
Roland Levillain <rpl@google.com> |
Add support for double-to-int & double-to-long in optimizing. - Add support for the double-to-int and double-to-long Dex instructions in the optimizing compiler. - Add S1 to the list of ARM FPU parameter registers so that a double value can be passed as parameter during a call to the runtime through D0. - Have art::x86_64::X86_64Assembler::cvttsd2si work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for double to int and double to long HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: Ic93b9ec6630c26e940f7966a3346ad3fd5a2ab3a
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8964e2b689d80fe546604ac8c724078645095cf1 |
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04-Dec-2014 |
Roland Levillain <rpl@google.com> |
Add support for float-to-double & double-to-float in optimizing. Change-Id: I41b0fee5a28c83757697c8d000b7e224cf5a4534
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624279f3c70f9904cbaf428078981b05d3b324c0 |
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04-Dec-2014 |
Roland Levillain <rpl@google.com> |
Add support for float-to-long in the optimizing compiler. - Add support for the float-to-long Dex instruction in the optimizing compiler. - Add a Dex PC field to art::HTypeConversion to allow the x86 and ARM code generators to produce runtime calls. - Instruct art::CodeGenerator::RecordPcInfo not to record PC information for HTypeConversion instructions. - Add S0 to the list of ARM FPU parameter registers. - Have art::x86_64::X86_64Assembler::cvttss2si work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for float to long HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I954214f0d537187883f83f7a83a1bb2dd8a21fd4
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3f8f936aff35f29d86183d31c20597ea17e9789d |
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02-Dec-2014 |
Roland Levillain <rpl@google.com> |
Add support for float-to-int in the optimizing compiler. - Add support for the float-to-int Dex instruction in the optimizing compiler. - Factor type conversion related lines in compiler/optimizing/builder.cc. - Generate x86, x86-64 and ARM (but not ARM64) code for float to int HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I2382dfc04bf394ed75f675148cfcf98216d65bc6
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01fcc9ee556f98d0163cc9b524e989760826926f |
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01-Dec-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Remove type conversion nodes converting to the same type. When optimizing, we ensure these conversions do not reach the code generators. When not optimizing, we cannot get such situations. Change-Id: I717247c957667675dc261183019c88efa3a38452
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6d0e483dd2e0b63e952de060738c10e2abd12ff7 |
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27-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for long-to-float in the optimizing compiler. - Add support for the long-to-float Dex instruction in the optimizing compiler. - Have art::x86_64::X86_64Assembler::cvtsi2ss work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for long to float HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: Ic983cbeb1ae2051add40bc519a8f00a6196166c9
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199f336af1fc8212646fda67675df0361ece33d6 |
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27-Nov-2014 |
Roland Levillain <rpl@google.com> |
Wrap long lines in the optimizing compiler. Change-Id: I5dee0c65e6652de574ae952b1f1dfc7355859e45
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32b2a52aa3d6dc25c18422514c7f88757f87d33c |
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27-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix Move64 by using ParallelMoves. Destination and source might overlap in a Move64, so we have to use a parallel move resolver. Change-Id: Ica6c72d91ab8e2e2ee4661b211ac1ee8f054b9ef
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271ab9c916980209fbc6b26e5545d76e58471569 |
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27-Nov-2014 |
Roland Levillain <rpl@google.com> |
Ensure opt. compiler doesn't get core & FP registers mixed up. Replace Location::As<T>() with two method methods (Location::AsRegister<T>() and Location::AsFpuRegister<T>()) checking the kind of the location (register). Change-Id: I22b4abee1a124b684becd2dc1caf33652b911070
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5368c219a462defc90c4b896b34eb7506ba5c142 |
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27-Nov-2014 |
Roland Levillain <rpl@google.com> |
Fix neg-float & neg-double for null values in opt. compiler. - Implement float and double negation as an exclusive or with a bit sign mask in x86 and x86-64 code generators. - Enable requests of temporary FPU (double) registers during register allocation. - Update test cases in test/415-optimizing-arith-neg. Change-Id: I9572c24b27c645ba698825e60cd5b3956b4895fa
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ddb7df25af45d7cd19ed1138e537973735cc78a5 |
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25-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE} Adds: - float comparison for arm, x86, x86_64 backends. - ucomis{s,d} assembly to x86 and x86_64. - vmstat assebmly for thumb2 - new assembly tests Change-Id: Ie3e19d0c08b3b875cd0a4be4ee4e9c8a4a076290
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647b9ed41cdb7cf302fd356627a3ba372419b78c |
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27-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for long-to-double in the optimizing compiler. - Add support for the long-to-double Dex instruction in the optimizing compiler. - Enable requests of temporary FPU (double) registers during code generation. - Fix art::x86::X86Assembler::LoadLongConstant and extend it to int64_t values. - Have art::x86_64::X86_64Assembler::cvtsi2sd work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for long to double HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: Ie73d9e5e25bd2e15f585c371e8fc2dcb83438ccd
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91debbc3da3e3376416e4394155d9f9e355255cb |
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26-Nov-2014 |
Calin Juravle <calin@google.com> |
Revert "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}" Fails on arm due to missing vmrs op after vcmp. I revert this instead of pushing the fix because I don't understand yet why it compiles with run-test but not with dex2oat. This reverts commit fd861249f31ab360c12dd1ffb131d50f02b0bfc6. Change-Id: Idc2d30f6a0f39ddd3596aa18a532ae90f8aaf62f
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fd861249f31ab360c12dd1ffb131d50f02b0bfc6 |
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25-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE} - adds float comparison for arm, x86, x86_64 backends. - adds ucomis{s,d} assembly to x86 and x86_64. Change-Id: I232d2b6e9ecf373beb5cc63698dd97a658ff9c83
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799f506b8d48bcceef5e6cf50f3f5eb6bcea05e1 |
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26-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}" Fails on x86_64 and target. This reverts commit cea28ec4b9e94ec942899acf1dbf20f8999b36b4. Change-Id: I30c1d188c7ecfe765f137a307022ede84f15482c
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cea28ec4b9e94ec942899acf1dbf20f8999b36b4 |
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25-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE} - adds float comparison for arm, x86, x86_64 backends. - adds ucomis{s,d} assembly to x86 and x86_64. Change-Id: Ie91e04bfb402025073054f3803a3a569e4705caa
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eace45873190a27302b3644c32ec82854b59d299 |
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25-Nov-2014 |
Mathieu Chartier <mathieuc@google.com> |
Move dexCacheStrings from ArtMethod to Class Adds one load for const strings which are not direct. Saves >= 60KB of memory avg per app. Image size: -350KB. Bug: 17643507 Change-Id: I2d1a3253d9de09682be9bc6b420a29513d592cc8 (cherry picked from commit f521f423b66e952f746885dd9f6cf8ef2788955d)
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9aec02fc5df5518c16f1e5a9b6cb198a192db973 |
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19-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add shifts Added SHL, SHR, USHR for arm, x86, x86_64. Change-Id: I971f594e270179457e6958acf1401ff7630df07e
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86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6 |
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19-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Consistently use k{InstructionSet}WordSize. These constants were defined prior to k{InstructionSet}PointerSize. So use them consistently in optimizing as a first step. We can discuss whether we should remove them in a second step. Change-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6
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2d7210188805292e463be4bcf7a133b654d7e0ea |
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10-Nov-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change 64 bit ArtMethod fields to be pointer sized Changed the 64 bit entrypoint and gc map fields in ArtMethod to be pointer sized. This saves a large amount of memory on 32 bit systems. Reduces ArtMethod size by 16 bytes on 32 bit. Total number of ArtMethod on low memory mako: 169957 Image size: 49203 methods -> 787248 image size reduction. Zygote space size: 1070 methods -> 17120 size reduction. App methods: ~120k -> 2 MB savings. Savings per app on low memory mako: 125K+ per app (less active apps -> more image methods per app). Savings depend on how often the shared methods are on dirty pages vs shared. TODO in another CL, delete gc map field from ArtMethod since we should be able to get it from the Oat method header. Bug: 17643507 Change-Id: Ie9508f05907a9f693882d4d32a564460bf273ee8 (cherry picked from commit e832e64a7e82d7f72aedbd7d798fb929d458ee8f)
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e832e64a7e82d7f72aedbd7d798fb929d458ee8f |
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10-Nov-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change 64 bit ArtMethod fields to be pointer sized Changed the 64 bit entrypoint and gc map fields in ArtMethod to be pointer sized. This saves a large amount of memory on 32 bit systems. Reduces ArtMethod size by 16 bytes on 32 bit. Total number of ArtMethod on low memory mako: 169957 Image size: 49203 methods -> 787248 image size reduction. Zygote space size: 1070 methods -> 17120 size reduction. App methods: ~120k -> 2 MB savings. Savings per app on low memory mako: 125K+ per app (less active apps -> more image methods per app). Savings depend on how often the shared methods are on dirty pages vs shared. TODO in another CL, delete gc map field from ArtMethod since we should be able to get it from the Oat method header. Bug: 17643507 Change-Id: Ie9508f05907a9f693882d4d32a564460bf273ee8
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cff137481eda0eb8dbdf9d2a303ae2bdac2c7322 |
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17-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-float & int-to-double in optimizing. - Add support for the int-to-float and int-to-double Dex instructions in the optimizing compiler. - Generate x86, x86-64 and ARM (but not ARM64) code for byte to float, short to float, int to float, char to float, byte to double, short to double, int to double and char to double HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I963f9d0184a5d3721af2d8f593f133d5af7aa6a3
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bacfec30ee9f2f6fdfd190f11b105b609938efca |
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14-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add REM_INT, REM_LONG - for arm, x86, x86_64 - minor cleanup/fix in div tests Change-Id: I240874010206a5a9b3aaffbc81a885b94c248f93
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01a8d7135c59b4a664d1e0c0e4d8db343d4118ef |
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14-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-short in the optimizing compiler. - Add support for the int-to-short Dex instruction in the optimizing compiler. - Generate x86, x86-64 and ARM (but not ARM64) code for byte to short, int to short and char to short HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: If1829549708d9c3473efaa641f7f0bcfa6080ae9
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af07bc121121d7bd7e8329c55dfe24782207b561 |
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12-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Minor object store optimizations. - Avoid emitting write barrier when the value is null. - Do not do a typecheck on an arraystore when storing something that was loaded from the same array. Change-Id: I902492928692e4553b5af0fc99cce3c2186c442a
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981e45424f52735b1c61ae0eac7e299ed313f8db |
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14-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-char in the optimizing compiler. - Add support for the int-to-char Dex instruction in the optimizing compiler. - Implement the ARM and Thumb-2 UBFX instructions and add tests for them. - Generate x86, x86-64 and ARM (but not ARM64) code for byte to char, short to char, int to char (and char to char!) HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I5cd4c6d86f0f6a966c059715b98db35cc8f9de76
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51d3fc40637fc73d4156ad617cd451b844cbb75e |
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13-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-byte in the optimizing compiler. - Add support for the int-to-byte Dex instruction in the optimizing compiler. - Implement the ARM and Thumb-2 SBFX instructions. - Generate x86, x86-64 and ARM (but not ARM64) code for char to byte, short to byte and int to byte HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: Ic8b8911b90d4b5281fad15bcee96bc3ee85dc577
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a21f598fd4dfdb95dc8597d3156120cc20d94c02 |
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13-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Fix Move for instruction with constant output Change-Id: I15d89292dc62f8dd8643530f95ace2e8be034411
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d6fb6cfb6f2d0d9595f55e8cc18d2753be5d9a13 |
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11-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add DIV_LONG - for backends: arm, x86, x86_64 - added cqo, idivq, testq assembly for x64_64 - small cleanups Change-Id: I762ef37880749038ed25d6014370be9a61795200
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f97f9fbfdf7f2e23c662f21081fadee6af37809d |
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11-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] add HTemporary support for long and doubles Change-Id: I5247ecd71d0193050484b7632c804c9bfd20f924
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f0e3937b87453234d0d7970b8712082062709b8d |
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12-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Do a parallel move in BoundsCheckSlowPath. The two locations of the index and length could overlap, so we need a parallel move. Also factorize the code for doing a parallel move based on two locations. Change-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4
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9574c4b5f5ef039d694ac12c97e25ca02eca83c0 |
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12-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement and/or/xor in optimizing. Change-Id: I7cf6da1fd334a7177a5580931b8f174dd40b7cec
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b7baf5c58d0e864f8c3f889357c51288aed42e61 |
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11-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement monitorenter/monitorexit. Pretty simple as they just invoke the runtime. Change-Id: I5fcb2c783deac27e55e28d8b3da3e68ea4b77363
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57a88d4ac205874dc85d22f9f6a9ca3c4c373eeb |
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10-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement checkcast for optimizing. - Ended up not using HTypeCheck because of how instanceof and checkcast end up having different logic for code generation. - Fix a x86_64 assembler bug triggered by now enabling more methods to be compiled. Difficult to test today without b/18117217. Change-Id: I3022e7ae03befb1d10bea9637ad21fadc430abe0
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946e143941d456a4ec666f7f54719c65c5aa3f5d |
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11-Nov-2014 |
Roland Levillain <rpl@google.com> |
Revert "Revert "Add support for long-to-int in the optimizing compiler."" This reverts commit 3adfd1b4fb20ac2b0217b5d2737bfe30ad90257a. Change-Id: Iacf0c6492d49267e24f1b727dbf6379b21fd02db
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3adfd1b4fb20ac2b0217b5d2737bfe30ad90257a |
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11-Nov-2014 |
Roland Levillain <rpl@google.com> |
Revert "Add support for long-to-int in the optimizing compiler." This reverts commit 647b96f29cb81832e698f863884fdba06674c9de. Change-Id: I552f23585463c676acbd547521b4d3ee5c0342eb
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647b96f29cb81832e698f863884fdba06674c9de |
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11-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for long-to-int in the optimizing compiler. - Add support for the long-to-int Dex instruction in the optimizing compiler. - Generate x86, x86-64 and ARM (but not ARM64) code for long-to-int HTypeConversion nodes. - Add related tests to test/422-type-conversion. - Also fix comments in test/415-optimizing-arith-neg and in test/416-optimizing-arith-not. Change-Id: I3084af30f2a495d178362ae1154dc7ceb7bf3a58
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666c732cfa211abf44ed90120a87bf8c18138e55 |
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10-Nov-2014 |
Roland Levillain <rpl@google.com> |
Support Java conversions from char to long in opt. compiler. These char to long conversions generate int-to-long Dex instructions. Change-Id: I6a8e71b57870cf5e8d5bc638fabce0fc7593f0b2
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52839d17c06175e19ca4a093fb878450d1c4310d |
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07-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support invoke-interface in optimizing. Change-Id: Ic18d7c3d2810557231caf0571956e0c431f5d384
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6f5c41f9e409bc4da53b5d7c385202255e391e72 |
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06-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement instanceof in optimizing. - Only fast-path for now: null or same class. - Use pQuickInstanceofNonTrivial for slow path. Change-Id: Ic5196b94bef792f081f3cb4d15157058e1381e6b
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f43083d560565aea46c602adb86423daeefe589d |
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07-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Do not update Out after it has a valid location. Slow paths use LocationSummary to know where to move things around, and they are executed at the end of the code generation. This fix is needed for https://android-review.googlesource.com/#/c/113345/. Change-Id: Id336c6409479b1de6dc839b736a7234d08a7774a
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52e832b1278449e62d9eb502d54d5ff18f8606ed |
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06-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support floats and doubles in fields. Change-Id: I19832106633405403f0461b3fe13b268abe39db3
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de58ab2c03ff8112b07ab827c8fa38f670dfc656 |
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05-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement try/catch/throw in optimizing. - We currently don't run optimizations in the presence of a try/catch. - We therefore implement Quick's mapping table. - Also fix a missing null check on array-length. Change-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f
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3dbcb38a8b2237b0da290ae35dc0caab3cb47b3d |
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28-Oct-2014 |
Roland Levillain <rpl@google.com> |
Support float & double negation in the optimizing compiler. - Add support for the neg-float and neg-double Dex instructions in the optimizing compiler. - Generate x86, x86-64 and ARM (but not ARM64) code for float and double HNeg nodes. - Add related tests to test/415-optimizing-arith-neg. Change-Id: I29739a86e13dbe6f64e191641d01637c867cba6c
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d0d4852847432368b090c184d6639e573538dccf |
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04-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add div-int and exception handling. - for backends: arm, x86, x86_64 - fixed a register allocator bug: the request for a fixed register for the first input was ignored if the output was kSameAsFirstInput - added divide by zero exception - more tests - shuffle around some code in the builder to reduce the number of lines of code for a single function. Change-Id: Id3a515e02bfbc66cd9d16cb9746f7551bdab3d42
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dff1f2812ecdaea89978c5351f0c70cdabbc0821 |
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05-Nov-2014 |
Roland Levillain <rpl@google.com> |
Support int-to-long conversions in the optimizing compiler. - Add support for the int-to-float Dex instruction in the optimizing compiler. - Add a HTypeConversion node type for control-flow graphs. - Generate x86, x86-64 and ARM (but not ARM64) code for int-to-float HTypeConversion nodes. - Add a 64-bit "Move doubleword to quadword with sign-extension" (MOVSXD) instruction to the x86-64 assembler. - Add related tests to test/422-type-conversion. Change-Id: Ieb8ec5380f9c411857119c79aa8d0728fd10f780
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277ccbd200ea43590dfc06a93ae184a765327ad0 |
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04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: More warnings Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general, and -Wunused-but-set-parameter for GCC builds. Change-Id: I81bbdd762213444673c65d85edae594a523836e5
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424f676379f2f872acd1478672022f19f3240fc1 |
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03-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement CONST_CLASS in optimizing compiler. Change-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd
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6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
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31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags. Fix associated errors about unused paramenters and implict sign conversions. For sign conversion this was largely in the area of enums, so add ostream operators for the effected enums and fix tools/generate-operator-out.py. Tidy arena allocation code and arena allocated data types, rather than fixing new and delete operators. Remove dead code. Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
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b5f62b3dc5ac2731ba8ad53cdf3d9bdb14fbf86b |
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30-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support for CONST_STRING in optimizing compiler. Change-Id: Iab8517bdadd1d15ffbe570010f093660be7c51aa
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0a6c459f713ff61769a02204cd736167e062bf4c |
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30-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix for long parameter passed both in stack and register. Fix for long parameter passed both in stack and register on 32bits architectures. The move to hard float ABI makes it so that the register index does not necessarily match the stack index anymore. Change-Id: I26b483f68ac86d336b4a37d94c38b04917668659
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19a19cffd197a28ae4c9c3e59eff6352fd392241 |
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22-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for static fields in optimizing compiler. Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
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7c4954d429626a6ceafbf05be41bf5f840894e44 |
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28-Oct-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add division for floats and doubles backends: x86, x86_64, arm. Also: - ordered instructions based on their name. - add missing kNoOutputOverlap to add/sub/mul. Change-Id: Ie47cde3b15ac74e7a1660c67a2eed1d7871f0ad0
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705664321a5cc1418255172f92d7d7195cf60a7b |
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24-Oct-2014 |
Roland Levillain <rpl@google.com> |
Add long bitwise not instruction in the optimizing compiler. - Add support for the not-long (long integer one's complement negation) instruction in the optimizing compiler. - Add a 64-bit NOT instruction (notq) to the x86-64 assembler. - Generate ARM, x86 and x86-64 code for long HNot nodes. - Gather not-related tests in test/416-optimizing-arith-not. Change-Id: I2d5b75e9875664d6032d04f8401b2bbb84506948
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2e07b4f0a84a7968b4690c2b1be2e2f75cc6fa8e |
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23-Oct-2014 |
Roland Levillain <rpl@google.com> |
Revert "Revert "Implement long negate instruction in the optimizing compiler."" This reverts commit 30ca3d847fe72cfa33e1b2473100ea2d8bea4517. Change-Id: I188ca8d460d55d3a9966bcf31e0588575afa77d2
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30ca3d847fe72cfa33e1b2473100ea2d8bea4517 |
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23-Oct-2014 |
Roland Levillain <rpl@google.com> |
Revert "Implement long negate instruction in the optimizing compiler." This reverts commit 66ce173a40eff4392e9949ede169ccf3108be2db.
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66ce173a40eff4392e9949ede169ccf3108be2db |
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23-Oct-2014 |
Roland Levillain <rpl@google.com> |
Implement long negate instruction in the optimizing compiler. - Add support for the neg-long (long integer two's complement negate) instruction in the optimizing compiler. - Add a 64-bit NEG instruction (negq) to the x86-64 assembler. - Generate ARM, x86 and x86-64 code for integer HNeg nodes. - Put neg-related tests into test/415-optimizing-arith-neg. Change-Id: I1fbe9611e134408a6b8745d1df20ab6ffa5e50f2
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1135168a1a9e2a6493657be8c5e91d67e5f224a7 |
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23-Oct-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add float/double subtraction - for arm, x86, x86_64 - add tests - a bit of clean up Change-Id: I3761b0d908aca3e3c5d60da481fafb423ff7c9b9
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1cc5f251df558b0e22cea5000626365eb644c727 |
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22-Oct-2014 |
Roland Levillain <rpl@google.com> |
Implement int bit-wise not operation in the optimizing compiler. - Add support for the not-int (integer one's complement negate) instruction in the optimizing compiler. - Extend the HNot control-flow graph node type and make it inherit from HUnaryOperation. - Generate ARM, x86 and x86-64 code for integer HNeg nodes. - Exercise these additions in the codegen_test gtest, as there is not direct way to assess the support of not-int from a Java source. Indeed, compiling a Java expression such as `~a' using javac and then dx generates an xor-int/lit8 Dex instruction instead of the expected not-int Dex instruction. This is probably because the Java bytecode has an `ixor' instruction, but there's not instruction directly corresponding to a bit-wise not operation. Change-Id: I223aed75c4dac5785e04d99da0d22e8d699aee2b
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b5bfa96ff20e86316961327dec5c859239dab6a0 |
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21-Oct-2014 |
Calin Juravle <calin@google.com> |
Add multiplication for floats/doubles in optimizing compiler Change-Id: I61de8ce1d9e37e30db62e776979b3f22dc643894
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a3d05a40de076aabf12ea284c67c99ff28b43dbf |
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20-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement array creation related DEX instructions. Implement new-array, filled-new-array, and fill-array-data. Change-Id: I405560d66777a57d881e384265322617ac5d3ce3
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102cbed1e52b7c5f09458b44903fe97bb3e14d5f |
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15-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement register allocator for floating point registers. Also: - Fix misuses of emitting the rex prefix in the x86_64 assembler. - Fix movaps code generation in the x86_64 assembler. Change-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe
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88cb1755e1d6acaed0f66ce65d7a2a4465053342 |
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20-Oct-2014 |
Roland Levillain <rpl@google.com> |
Implement int negate instruction in the optimizing compiler. - Add support for the neg-int (integer two's complement negate) instruction in the optimizing compiler. - Add a HNeg node type for control-flow graphs and an intermediate HUnaryOperation base class. - Generate ARM, x86 and x86-64 code for integer HNeg nodes. Change-Id: I72fd3e1e5311a75c38a8cb665a9211a20325a42e
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8e3964b766652a0478e8e0e303e8556c997675f1 |
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17-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Remove the notion of dies at entry. - Instead, explicitly say that the output does not overlap. - Inputs that must be in a fixed register do die at entry, as we know they have a location that others can not take. - There is also no need to differentiate between an input move and a connecting sibling move - those can be put in the same parallel move instruction. Change-Id: I1b2b2827906601f822b59fb9d6a21d48e43bae27
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34bacdf7eb46c0ffbf24ba7aa14a904bc9176fb2 |
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07-Oct-2014 |
Calin Juravle <calin@google.com> |
Add multiplication for integral types This also fixes an issue where we could allocate a pair register even if one of its parts was already blocked. Change-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01
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92a73aef279be78e3c2b04db1713076183933436 |
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16-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Don't use assembler classes in code_generator.h. The arm64 backend uses its own assembler and does not share the same classes as the other backends. To avoid conflicts or unnecessary mappings, just don't use those classes in the shared part of the code generator. Change-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d
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3a3fd0f8d3981691aa2331077a8fae5feee08dd1 |
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10-Oct-2014 |
Roland Levillain <rpl@google.com> |
Turn constant conditional jumps into unconditional jumps. If a condition (input of an art::HIf instruction) is constant (an art::HConstant object), evaluate it at compile time and generate an unconditional branch instruction if it is true (in lieu of a conditional jump). Change-Id: I262e43ffe66d5c25dbbfa98092a41c8b3c4c75d6
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71175b7f19a4f6cf9cc264feafd820dbafa371fb |
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09-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Cleanup baseline register allocator. - Use three arrays for blocking regsters instead of one and computing offsets in that array.] - Don't pass blocked_registers_ to methods, just use the field. Change-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6
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fc787ecd91127b2c8458afd94e5148e2ae51a1f5 |
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10-Oct-2014 |
Ian Rogers <irogers@google.com> |
Enable -Wimplicit-fallthrough. Falling through switch cases on a clang build must now annotate the fallthrough with the FALLTHROUGH_INTENDED macro. Bug: 17731372 Change-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324
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476df557fed5f0b3f32f8d11a654674bb403a8f8 |
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09-Oct-2014 |
Roland Levillain <rpl@google.com> |
Use Is*() helpers to shorten code in the optimizing compiler. Change-Id: I79f31833bc9a0aa2918381aa3fb0b05d45f75689
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360231a056e796c36ffe62348507e904dc9efb9b |
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08-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix code generation of materialized conditions. Move the logic for knowing if a condition needs to be materialized in an optimization pass (so that the information does not change as a side effect of another optimization). Also clean-up arm and x86_64 codegen: - arm: ldr and str are for power-users when a constant is in play. We should use LoadFromOffset and StoreToOffset. - x86_64: fix misuses of movq instead of movl. Change-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3
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56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f |
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09-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Stop converting from Location to ManagedRegister. Now the source of truth is the Location object that knows which register (core, pair, fpu) it needs to refer to. Change-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1
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7e70b002c4552347ed1af8c002a0e13f08864f20 |
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08-Oct-2014 |
Ian Rogers <irogers@google.com> |
Header file clean up. Remove runtime.h from object.h. Move TypeStaticIf to its own header file to avoid bringing utils.h into allocator.h. Move Array::DataOffset into -inl.h as it now has a utils.h dependency. Fix include issues arising from this. Change-Id: I4605b1aa4ff5f8dc15706a0132e15df03c7c8ba0
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01ef345767ea609417fc511e42007705c9667546 |
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01-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add trivial register hints to the register allocator. - Add hints for phis, same as first input, and expected registers. - Make the if instruction accept non-condition instructions. Change-Id: I34fa68393f0d0c19c68128f017b7a05be556fbe5
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7fb49da8ec62e8a10ed9419ade9f32c6b1174687 |
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06-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for floats and doubles. - Follows Quick conventions. - Currently only works with baseline register allocator. Change-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3
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7adfcc8cfdf5fe3a8a0aefa08bfc3249fca55c8b |
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07-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Do not use kDiesAtEntry when inputs must be in specific reg. The way the register allocator blocks registers currently does not handle these cases. Since it only applies to x86 for now, just ensure such requests cannot happen. Change-Id: Idfa25532b9b4996a192d05800f56c6e44edd3a8a
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26a25ef62a13f409f941aa39825a51b4d6f0f047 |
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30-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a prepare for register allocation pass. - Currently the pass just changes the uses of checks to the actual values. - Also optimize array access, now that inputs can be constants. - And fix another bug in the register allocator reveiled by this change. Change-Id: I43be0dbde9330ee5c8f9d678de11361292d8bd98
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9ae0daa60c568f98ef0020e52366856ff314615f |
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30-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for inputs dying at entry of instructions. - Start using it in places where it makes sense. - Also improve suspend check on arm to use subs directly. Change-Id: I09ac0589f5ccb9b850ee757c76dcbcf35ee8cd01
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5799fc0754da7ff2b50b472e05c65cd4ba32dda2 |
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25-Sep-2014 |
Roland Levillain <rpl@google.com> |
Optimizing compiler: remove unnecessary `explicit' keywords. Change-Id: I5927fd92d53308c81e14edbd6e7d1c943bfa085b
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3c04974a90b0e03f4b509010bff49f0b2a3da57f |
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24-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Optimize suspend checks in optimizing compiler. - Remove the ones added during graph build (they were added for the baseline code generator). - Emit them at loop back edges after phi moves, so that the test can directly jump to the loop header. - Fix x86 and x86_64 suspend check by using cmpw instead of cmpl. Change-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a
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3bca0df855f0e575c6ee020ed016999fc8f14122 |
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19-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support for saving and restoring live registers in a slow path. And use it in suspend check slow paths. Change-Id: I79caf28f334c145a36180c79a6e2fceae3990c31
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18efde5017369e005f1e8bcd3bbfb04e85053640 |
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22-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix code generation with materialized conditions. Change-Id: I8630af3c13fc1950d3fa718d7488407b00898796
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e982f0b8e809cece6f460fa2d8df25873aa69de4 |
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13-Aug-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement invoke virtual in optimizing compiler. Also refactor 004 tests to make them work with both Quick and Optimizing. Change-Id: I87e275cb0ae0258fc3bb32b612140000b1d2adf8
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fbc695f9b8e2084697e19c1355ab925f99f0d235 |
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15-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Implement suspend checks in new compiler."" This reverts commit 7e3652c45c30c1f2f840e6088e24e2db716eaea7. Change-Id: Ib489440c34e41cba9e9e297054f9274f6e81a2d8
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7e3652c45c30c1f2f840e6088e24e2db716eaea7 |
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15-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Implement suspend checks in new compiler." This reverts commit 6fbce029fba3ed5da6c36017754ed408e6bcb632. Change-Id: Ia915c27873b021e658a10212e559095dfc91284e
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6fbce029fba3ed5da6c36017754ed408e6bcb632 |
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10-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement suspend checks in new compiler. For simplicity, they are currently placed on all (dex-level) back edges, and at method entry. Change-Id: I6e833e244d559dd788c69727e22fe40aff5b3435
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3946844c34ad965515f677084b07d663d70ad1b8 |
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02-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Runtime support for the new stack maps for the opt compiler. Now most of the methods supported by the compiler can be optimized, instead of using the baseline. Change-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa
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b038ba66a166fb264ca121632f447712e0973b5b |
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14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Reduce stack usage for overflow checks"" Fixes stack protection issue. Fixes mac build issue. This reverts commit 83b1940e6482b9d8feba5c492507735686650ea5. Change-Id: I7ba17252882b23a740bcda2ea94aacf398255406
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4cf00ba324f5f6884059796a6ba41937f32e1844 |
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14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Reduce stack usage for overflow checks" This reverts commit 63c051a540e6dfc806f656b88ac3a63e99395429. Change-Id: I282a048994fcd130fe73842b16c21680053c592f
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03c9785a8a6d712775cf406c4371d0227c44148f |
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14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Reduce stack usage for overflow checks"" Fixes stack protection issue. Fixes mac build issue. This reverts commit 83b1940e6482b9d8feba5c492507735686650ea5. Change-Id: I7ba17252882b23a740bcda2ea94aacf398255406
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83b1940e6482b9d8feba5c492507735686650ea5 |
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14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Reduce stack usage for overflow checks" This reverts commit 63c051a540e6dfc806f656b88ac3a63e99395429. Change-Id: I282a048994fcd130fe73842b16c21680053c592f
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63c051a540e6dfc806f656b88ac3a63e99395429 |
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26-Jul-2014 |
Dave Allison <dallison@google.com> |
Reduce stack usage for overflow checks This reduces the stack space reserved for overflow checks to 12K, split into an 8K gap and a 4K protected region. GC needs over 8K when running in a stack overflow situation. Also prevents signal runaway by detecting a signal inside code that resulted from a signal handler invokation. And adds a max signal count to the SignalTest to prevent it running forever. Also reduces the number of iterations for the InterfaceTest as this was taking (almost) forever with the --trace option on run-test. Bug: 15435566 Change-Id: Id4fd46f22d52d42a9eb431ca07948673e8fda694 Conflicts: compiler/optimizing/code_generator_x86_64.cc runtime/arch/x86/fault_handler_x86.cc runtime/arch/x86_64/quick_entrypoints_x86_64.S
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648d7112609dd19c38131b3e71c37bcbbd19d11e |
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26-Jul-2014 |
Dave Allison <dallison@google.com> |
Reduce stack usage for overflow checks This reduces the stack space reserved for overflow checks to 12K, split into an 8K gap and a 4K protected region. GC needs over 8K when running in a stack overflow situation. Also prevents signal runaway by detecting a signal inside code that resulted from a signal handler invokation. And adds a max signal count to the SignalTest to prevent it running forever. Also reduces the number of iterations for the InterfaceTest as this was taking (almost) forever with the --trace option on run-test. Bug: 15435566 Change-Id: Id4fd46f22d52d42a9eb431ca07948673e8fda694
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f6e206c820fe75a341c98ef12410475d33028640 |
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07-Aug-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support x86_64 stack overflow checks in opt compiler. Also re-enable SignalTest on optimizing-32. Change-Id: I2ca13f6f9ea775c654ee07cc5026c985263d6380
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3c7bb98698f77af10372cf31824d3bb115d9bf0f |
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23-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement array get and array put in optimizing. Also fix a couple of assembler/disassembler issues. Change-Id: I705c8572988c1a9c4df3172b304678529636d5f6
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397f2e42beadb77d98e550bd1b25b9b61237c943 |
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23-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix implicit stack overflow check on optimizing/x86. They need to happen before changing ESP, and require a suspend point. Change-Id: Id41aa9c99714f7ab8591367ea5cb9ca105b17ce8
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f12feb8e0e857f2832545b3f28d31bad5a9d3903 |
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17-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Stack overflow checks and NPE checks for optimizing. Change-Id: I59e97448bf29778769b79b51ee4ea43f43493d96
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1a43dd78d054dbad8d7af9ba4829ea2f1cb70b53 |
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17-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add write barriers to optimizing compiler. Change-Id: I43a40954757f51d49782e70bc28f7c314d6dbe17
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96f89a290eb67d7bf4b1636798fa28df14309cc7 |
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11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add assembly operations with constants in optimizing compiler. Change-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f
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ab032bc1ff57831106fdac6a91a136293609401f |
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15-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix a braino in the stack layout. Also do some refactoring to have this code be just in CodeGenerator. Change-Id: I88de109889138af8d60027973c12a64bee813cb7
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e50383288a75244255d3ecedcc79ffe9caf774cb |
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04-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support fields in optimizing compiler. - Required support for temporaries, to be only used by baseline compiler. - Also fixed a few invalid assumptions around locations and instructions that don't need materialization. These instructions should not have an Out. Change-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62
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412f10cfed002ab617c78f2621d68446ca4dd8bd |
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19-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support longs in the register allocator for x86_64. Change-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867
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f61b5377068f22c0be7b2f6e62961e620408beb2 |
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25-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Re-enable tests with the optimizing compiler. Tests run ok on my host/target. I reverted the move to using thumb2, because tests were crashing. But I could not reproduce file limits issues. Make SignalTest as crashing for optimizing. We need to implement stack overflow checks. Change-Id: Ieda575501eaf30af7aaa2c44e71544c9c467c24f
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20dfc797dc631bf8d655dcf123f46f13332d3074 |
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17-Jun-2014 |
Dave Allison <dallison@google.com> |
Add some more instruction support to optimizing compiler. This adds a few more DEX instructions to the optimizing compiler's builder (constants, moves, if_xx, etc). Also: * Changes the codegen for IF_XX instructions to use a condition rather than comparing a value against 0. * Fixes some instructions in the ARM disassembler. * Fixes PushList and PopList in the thumb2 assembler. * Switches the assembler for the optimizing compiler to thumb2 rather than ARM. Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
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e27f31a81636ad74bd3376ee39cf215941b85c0e |
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12-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Enable the register allocator on ARM. - Also fixes a few bugs/wrong assumptions in code not hit by x86. - We need to differentiate between moves due to connecting siblings within a block, and moves due to control flow resolution. Change-Id: Idd05cf138a71c8f36f5531c473de613c0166fe38
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86dbb9a12119273039ce272b41c809fa548b37b6 |
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04-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Final CL to enable register allocation on x86. This CL implements: 1) Resolution after allocation: connecting the locations allocated to an interval within a block and between blocks. 2) Handling of fixed registers: some instructions require inputs/output to be at a specific location, and the allocator needs to deal with them in a special way. 3) ParallelMoveResolver::EmitNativeCode for x86. Change-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858
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ecb2f9ba57b08ceac4204ddd6a0a88a0524f8741 |
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13-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Enable the register allocator on x86_64. Also fix an x86_64 assembler bug for movl. Change-Id: I8d17c68cd35ddd1d8df159f2d6173a013a7c3347
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9cf35523764d829ae0470dae2d5dd99be469c841 |
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09-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add x86_64 support to the optimizing compiler. Change-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be
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31d76b42ef5165351499da3f8ee0ac147428c5ed |
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09-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Plug code generator into liveness analysis. Also implement spill slot support. Change-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc
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ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
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03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE Merge ART from AOSP to lmp-preview-dev. Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
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a7062e05e6048c7f817d784a5b94e3122e25b1ec |
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22-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a linear scan register allocator to the optimizing compiler. This is a "by-the-book" implementation. It currently only deals with allocating registers, with no hint optimizations. The changes remaining to make it functional are: - Allocate spill slots. - Resolution and placements of Move instructions. - Connect it to the code generator. Change-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4
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4e3d23aa1523718ea1fdf3a32516d2f9d81e84fe |
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22-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Import Dart's parallel move resolver. And write a few tests while at it. A parallel move resolver will be needed for performing multiple moves that are conceptually parallel, for example moves at a block exit that branches to a block with phi nodes. Change-Id: Ib95b247b4fc3f2c2fcab3b8c8d032abbd6104cd7
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b0fa5dc7769c1e054032f39de0a3f6d6dd06f8cf |
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29-Apr-2014 |
Ian Rogers <irogers@google.com> |
Force inlining on trivial accessors. Make volatility for GetFieldObject a template parameter. Move some trivial mirror::String routines to a -inl.h. Bug: 14285442 Change-Id: Ie23b11d4f18cb15a62c3bbb42837a8aaf6b68f92
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a7aca370a7d62ca04a1e24423d90e8020d6f1a58 |
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28-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Setup policies for register allocation. Change-Id: I857e77530fca3e2fb872fc142a916af1b48400dc
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c32e770f21540e4e9eda6dc7f770e745d33f1b9f |
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24-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a Transform to SSA phase to the optimizing compiler. Change-Id: Ia9700756a0396d797a00b529896487d52c989329
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a747a392fb5f88d2ecc4c6021edf9f1f6615ba16 |
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17-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Code cleanup in preparation for x64 backend. - Use InvokeDexCallingConventionVisitor for setting up HParameterValues - Use kVregSize instead of kX86WordSize when dealing with virtual registers. Change-Id: Ia520223010194c70a3ff0ed659077f55cec4e7d8
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db928fcc975b431d8a78700c11bd7da21090384a |
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16-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Simplify HInvokeStatic code generation. HPushArgument is not needed for now (but might be when we start optimizing). Also, calling convention for 64bits backend will require to know more about the argument than the argument's index. Therefore currently let HInvokeStatic setup the arguments, which is possible because arguments of a calls are virtual registers and not instructions. Change-Id: I8753ed6083aa083c5180ab53b436dc8de4f1fe31
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01bc96d007b67fdb7fe349232a83e4b354ce3d08 |
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11-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Long support in optimizing compiler. - Add stack locations to the Location class. - Change logic of parameter passing/setup by setting the location of such instructions the ones for the calling convention. Change-Id: I4730ad58732813dcb9c238f44f55dfc0baa18799
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b55f835d66a61e5da6fc1895ba5a0482868c9552 |
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07-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Test control flow instruction with optimizing compiler. Add support for basic instructions to implement these tests. Change-Id: I3870bf9301599043b3511522bb49dc6364c9b4c0
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f583e5976e1de9aa206fb8de4f91000180685066 |
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07-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for taking parameters in optimizing compiler. - Fix stack layout to mimic Quick's. - Implement some sub operations. Change-Id: I8cf75a4d29b662381a64f02c0bc61d859482fc4e
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707c809f661554713edfacf338365adca8dfd3a3 |
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04-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Use target-specific word instead of runtime word. Change-Id: Ia11dc3cc520a1a5c7bd017013e5699af9570ce91
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2e7038ac5848468740d6a419434d3dde8c585a53 |
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03-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for new-instance and invoke-direct. Change-Id: I2daed646904f7711972a7da15d88be7573426932
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4a34a428c6a2588e0857ef6baf88f1b73ce65958 |
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03-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support passing arguments to invoke-static* instructions. - Stop using the frame pointer for accessing locals. - Stop emulating a stack when doing code generation. Instead, rely on dex register model, where instructions only reference registers. Change-Id: Id51bd7d33ac430cb87a53c9f4b0c864eeb1006f9
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d8ee737fdbf380c5bb90c9270c8d1087ac23e76c |
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28-Mar-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for adding two integers in optimizing compiler. Change-Id: I5524e193cd07f2692a57c6b4f8069904471b2928
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8ccc3f5d06fd217cdaabd37e743adab2031d3720 |
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19-Mar-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for invoke-static in optimizing compiler. Support is limited to calls without parameters and returning void. For simplicity, we currently follow the Quick ABI. Change-Id: I54805161141b7eac5959f1cae0dc138dd0b2e8a5
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787c3076635cf117eb646c5a89a9014b2072fb44 |
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17-Mar-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Plug new optimizing compiler in compilation pipeline. Also rename accessors to ART's conventions. Change-Id: I344807055b98aa4b27215704ec362191464acecc
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bab4ed7057799a4fadc6283108ab56f389d117d4 |
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11-Mar-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
More code generation for the optimizing compiler. - Add HReturn instruction - Generate code for locals/if/return - Setup infrastructure for register allocation. Currently emulate a stack. Change-Id: Ib28c2dba80f6c526177ed9a7b09c0689ac8122fb
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3ff386aafefd5282bb76c8a50506a70a4321e698 |
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04-Mar-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add register support to the optimizing compiler. Also make if take an input and build the use list for instructions. Change-Id: I1938cee7dce5bd4c66b259fa2b431d2c79b3cf82
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d4dd255db1d110ceb5551f6d95ff31fb57420994 |
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28-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add codegen support to the optimizing compiler. Change-Id: I9aae76908ff1d6e64fb71a6718fc1426b67a5c28
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