Cross Reference: /art/compiler/utils/mips64/assembler

Lines Matching defs:fs
71 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd,
74   CHECK_NE(fs, kNoFpuRegister);
79                       static_cast<uint32_t>(fs) << kFsShift |
514 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
515   EmitFR(0x11, 0x10, ft, fs, fd, 0x0);
518 void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
519   EmitFR(0x11, 0x10, ft, fs, fd, 0x1);
522 void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
523   EmitFR(0x11, 0x10, ft, fs, fd, 0x2);
526 void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
527   EmitFR(0x11, 0x10, ft, fs, fd, 0x3);
530 void Mips64Assembler::AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
531   EmitFR(0x11, 0x11, ft, fs, fd, 0x0);
534 void Mips64Assembler::SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
535   EmitFR(0x11, 0x11, ft, fs, fd, 0x1);
538 void Mips64Assembler::MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
539   EmitFR(0x11, 0x11, ft, fs, fd, 0x2);
542 void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
543   EmitFR(0x11, 0x11, ft, fs, fd, 0x3);
546 void Mips64Assembler::MovS(FpuRegister fd, FpuRegister fs) {
547   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6);
550 void Mips64Assembler::MovD(FpuRegister fd, FpuRegister fs) {
551   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x6);
554 void Mips64Assembler::NegS(FpuRegister fd, FpuRegister fs) {
555   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x7);
558 void Mips64Assembler::NegD(FpuRegister fd, FpuRegister fs) {
559   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x7);
562 void Mips64Assembler::Cvtsw(FpuRegister fd, FpuRegister fs) {
563   EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x20);
566 void Mips64Assembler::Cvtdw(FpuRegister fd, FpuRegister fs) {
567   EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x21);
570 void Mips64Assembler::Cvtsd(FpuRegister fd, FpuRegister fs) {
571   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x20);
574 void Mips64Assembler::Cvtds(FpuRegister fd, FpuRegister fs) {
575   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x21);
578 void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) {
579   EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
582 void Mips64Assembler::Mtc1(GpuRegister rt, FpuRegister fs) {
583   EmitFR(0x11, 0x04, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
586 void Mips64Assembler::Dmfc1(GpuRegister rt, FpuRegister fs) {
587   EmitFR(0x11, 0x01, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
590 void Mips64Assembler::Dmtc1(GpuRegister rt, FpuRegister fs) {
591   EmitFR(0x11, 0x05, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);