Lines Matching refs:ISD
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
293 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
351 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
353 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
375 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
399 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
408 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
417 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
431 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
433 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
434 ISD::ANY_EXTEND, dl, VT, Result);
470 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
471 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
478 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
493 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
517 ISD::LoadExtType HiExtType = LD->getExtensionType();
520 if (HiExtType == ISD::NON_EXTLOAD)
521 HiExtType = ISD::ZEXTLOAD;
526 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
530 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
542 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
544 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
595 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
600 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
620 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
683 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
690 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
717 switch (TLI.getOperationAction(ISD::STORE, VT)) {
739 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
742 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
794 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
796 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
807 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
816 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
825 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
857 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
875 ISD::LoadExtType ExtType = LD->getExtensionType();
876 if (ExtType == ISD::NON_EXTLOAD) {
912 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
958 ISD::LoadExtType NewExtType =
959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
969 if (ExtType == ISD::SEXTLOAD)
971 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
974 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
976 Result = DAG.getNode(ISD::AssertZext, dl,
999 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1006 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1015 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1019 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1024 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1035 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1037 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1045 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1049 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1054 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1093 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0), SrcVT)) {
1101 ISD::LoadExtType MidExtType =
1102 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1107 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1121 assert(ExtType != ISD::EXTLOAD &&
1125 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1130 if (ExtType == ISD::SEXTLOAD)
1131 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1160 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1172 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1179 case ISD::INTRINSIC_W_CHAIN:
1180 case ISD::INTRINSIC_WO_CHAIN:
1181 case ISD::INTRINSIC_VOID:
1182 case ISD::STACKSAVE:
1185 case ISD::VAARG:
1191 case ISD::FP_TO_FP16:
1192 case ISD::SINT_TO_FP:
1193 case ISD::UINT_TO_FP:
1194 case ISD::EXTRACT_VECTOR_ELT:
1198 case ISD::FP_ROUND_INREG:
1199 case ISD::SIGN_EXTEND_INREG: {
1204 case ISD::ATOMIC_STORE: {
1209 case ISD::SELECT_CC:
1210 case ISD::SETCC:
1211 case ISD::BR_CC: {
1212 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1213 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1214 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1216 ISD::CondCode CCCode =
1220 if (Node->getOpcode() == ISD::SELECT_CC)
1228 case ISD::LOAD:
1229 case ISD::STORE:
1234 case ISD::CALLSEQ_START:
1235 case ISD::CALLSEQ_END:
1241 case ISD::EXTRACT_ELEMENT:
1242 case ISD::FLT_ROUNDS_:
1243 case ISD::SADDO:
1244 case ISD::SSUBO:
1245 case ISD::UADDO:
1246 case ISD::USUBO:
1247 case ISD::SMULO:
1248 case ISD::UMULO:
1249 case ISD::FPOWI:
1250 case ISD::MERGE_VALUES:
1251 case ISD::EH_RETURN:
1252 case ISD::FRAME_TO_ARGS_OFFSET:
1253 case ISD::EH_SJLJ_SETJMP:
1254 case ISD::EH_SJLJ_LONGJMP:
1261 case ISD::INIT_TRAMPOLINE:
1262 case ISD::ADJUST_TRAMPOLINE:
1263 case ISD::FRAMEADDR:
1264 case ISD::RETURNADDR:
1271 case ISD::READ_REGISTER:
1272 case ISD::WRITE_REGISTER:
1278 case ISD::DEBUGTRAP:
1281 // replace ISD::DEBUGTRAP with ISD::TRAP
1283 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1292 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1304 case ISD::SHL:
1305 case ISD::SRL:
1306 case ISD::SRA:
1307 case ISD::ROTL:
1308 case ISD::ROTR:
1321 case ISD::SRL_PARTS:
1322 case ISD::SRA_PARTS:
1323 case ISD::SHL_PARTS:
1386 case ISD::CALLSEQ_START:
1387 case ISD::CALLSEQ_END:
1389 case ISD::LOAD: {
1392 case ISD::STORE: {
1439 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1443 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1452 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1492 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1496 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1526 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1531 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1549 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1570 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1591 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1601 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1609 ISD::SETLT);
1611 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1615 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1642 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1644 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1680 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1688 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1694 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1698 case ISD::SETO:
1699 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1702 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1703 case ISD::SETUO:
1704 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1707 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1708 case ISD::SETOEQ:
1709 case ISD::SETOGT:
1710 case ISD::SETOGE:
1711 case ISD::SETOLT:
1712 case ISD::SETOLE:
1713 case ISD::SETONE:
1714 case ISD::SETUEQ:
1715 case ISD::SETUNE:
1716 case ISD::SETUGT:
1717 case ISD::SETUGE:
1718 case ISD::SETULT:
1719 case ISD::SETULE:
1724 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1725 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1726 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1730 case ISD::SETLE:
1731 case ISD::SETGT:
1732 case ISD::SETGE:
1733 case ISD::SETLT:
1737 case ISD::SETNE:
1738 case ISD::SETEQ:
1740 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1752 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1814 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1856 if (V.getOpcode() == ISD::UNDEF)
1861 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1948 if (V.getOpcode() == ISD::UNDEF)
1969 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1991 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2006 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2016 if (V.getOpcode() == ISD::UNDEF)
2022 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2025 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2211 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2214 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2216 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2238 bool isSigned = Opcode == ISD::SDIVREM;
2325 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2326 ? ISD::FCOS : ISD::FSIN;
2335 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2424 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2434 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2457 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2465 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2468 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2489 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2491 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2492 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2493 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2494 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2495 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2497 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2506 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2510 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2512 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2513 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2515 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2516 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2523 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2529 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2531 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2533 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2536 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2540 ISD::SETUGE);
2544 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2546 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2547 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2550 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2551 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2552 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2553 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2554 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2558 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2562 ISD::SETLT);
2584 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2592 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2601 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2624 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2625 OpToUse = ISD::SINT_TO_FP;
2631 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2632 OpToUse = ISD::UINT_TO_FP;
2642 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2667 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2668 OpToUse = ISD::FP_TO_SINT;
2673 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2674 OpToUse = ISD::FP_TO_UINT;
2687 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2698 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2699 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2700 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2702 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2703 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2704 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2705 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2706 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2707 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2708 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2709 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2710 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2712 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2713 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2714 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2715 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2716 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2717 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2718 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2719 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2720 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2721 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2722 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2723 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2724 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2725 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2726 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2727 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2728 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2729 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2730 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2731 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2732 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2741 case ISD::CTPOP: {
2758 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2759 DAG.getNode(ISD::AND, dl, VT,
2760 DAG.getNode(ISD::SRL, dl, VT, Op,
2764 Op = DAG.getNode(ISD::ADD, dl, VT,
2765 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2766 DAG.getNode(ISD::AND, dl, VT,
2767 DAG.getNode(ISD::SRL, dl, VT, Op,
2771 Op = DAG.getNode(ISD::AND, dl, VT,
2772 DAG.getNode(ISD::ADD, dl, VT, Op,
2773 DAG.getNode(ISD::SRL, dl, VT, Op,
2777 Op = DAG.getNode(ISD::SRL, dl, VT,
2778 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2783 case ISD::CTLZ_ZERO_UNDEF:
2785 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2786 case ISD::CTLZ: {
2801 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2802 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2805 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2807 case ISD::CTTZ_ZERO_UNDEF:
2809 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2810 case ISD::CTTZ: {
2816 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2818 DAG.getNode(ISD::SUB, dl, VT, Op,
2820 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2821 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2822 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2823 return DAG.getNode(ISD::SUB, dl, VT,
2825 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2826 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2846 case ISD::CTPOP:
2847 case ISD::CTLZ:
2848 case ISD::CTLZ_ZERO_UNDEF:
2849 case ISD::CTTZ:
2850 case ISD::CTTZ_ZERO_UNDEF:
2854 case ISD::BSWAP:
2857 case ISD::FRAMEADDR:
2858 case ISD::RETURNADDR:
2859 case ISD::FRAME_TO_ARGS_OFFSET:
2862 case ISD::FLT_ROUNDS_:
2865 case ISD::EH_RETURN:
2866 case ISD::EH_LABEL:
2867 case ISD::PREFETCH:
2868 case ISD::VAEND:
2869 case ISD::EH_SJLJ_LONGJMP:
2874 case ISD::EH_SJLJ_SETJMP:
2880 case ISD::ATOMIC_FENCE: {
2896 case ISD::ATOMIC_LOAD: {
2901 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2911 case ISD::ATOMIC_STORE: {
2913 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2926 case ISD::ATOMIC_SWAP:
2927 case ISD::ATOMIC_LOAD_ADD:
2928 case ISD::ATOMIC_LOAD_SUB:
2929 case ISD::ATOMIC_LOAD_AND:
2930 case ISD::ATOMIC_LOAD_OR:
2931 case ISD::ATOMIC_LOAD_XOR:
2932 case ISD::ATOMIC_LOAD_NAND:
2933 case ISD::ATOMIC_LOAD_MIN:
2934 case ISD::ATOMIC_LOAD_MAX:
2935 case ISD::ATOMIC_LOAD_UMIN:
2936 case ISD::ATOMIC_LOAD_UMAX:
2937 case ISD::ATOMIC_CMP_SWAP: {
2943 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2949 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2957 Res, Node->getOperand(2), ISD::SETEQ);
2964 case ISD::DYNAMIC_STACKALLOC:
2967 case ISD::MERGE_VALUES:
2971 case ISD::UNDEF: {
2981 case ISD::TRAP: {
2994 case ISD::FP_ROUND:
2995 case ISD::BITCAST:
3000 case ISD::FP_EXTEND:
3006 case ISD::SIGN_EXTEND_INREG: {
3017 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3019 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3023 case ISD::FP_ROUND_INREG: {
3036 case ISD::SINT_TO_FP:
3037 case ISD::UINT_TO_FP:
3038 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3042 case ISD::FP_TO_SINT:
3046 case ISD::FP_TO_UINT: {
3057 Tmp1, ISD::SETLT);
3058 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3059 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3060 DAG.getNode(ISD::FSUB, dl, VT,
3062 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3068 case ISD::VAARG: {
3083 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3087 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3093 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3106 case ISD::VACOPY: {
3119 case ISD::EXTRACT_VECTOR_ELT:
3122 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3128 case ISD::EXTRACT_SUBVECTOR:
3131 case ISD::INSERT_SUBVECTOR:
3134 case ISD::CONCAT_VECTORS: {
3138 case ISD::SCALAR_TO_VECTOR:
3141 case ISD::INSERT_VECTOR_ELT:
3146 case ISD::VECTOR_SHUFFLE: {
3174 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3175 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3208 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3212 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3218 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3220 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3224 case ISD::EXTRACT_ELEMENT: {
3228 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3231 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3234 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3240 case ISD::STACKSAVE:
3252 case ISD::STACKRESTORE:
3262 case ISD::FCOPYSIGN:
3265 case ISD::FNEG:
3268 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3272 case ISD::FABS: {
3278 Tmp1, Tmp2, ISD::SETUGT);
3279 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3284 case ISD::FMINNUM:
3289 case ISD::FMAXNUM:
3294 case ISD::FSQRT:
3299 case ISD::FSIN:
3300 case ISD::FCOS: {
3302 bool isSIN = Node->getOpcode() == ISD::FSIN;
3303 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3305 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3309 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3324 case ISD::FSINCOS:
3328 case ISD::FLOG:
3333 case ISD::FLOG2:
3338 case ISD::FLOG10:
3343 case ISD::FEXP:
3348 case ISD::FEXP2:
3353 case ISD::FTRUNC:
3358 case ISD::FFLOOR:
3363 case ISD::FCEIL:
3368 case ISD::FRINT:
3373 case ISD::FNEARBYINT:
3380 case ISD::FROUND:
3387 case ISD::FPOWI:
3392 case ISD::FPOW:
3397 case ISD::FDIV:
3402 case ISD::FREM:
3407 case ISD::FMA:
3412 case ISD::FMAD:
3415 case ISD::FADD:
3420 case ISD::FMUL:
3425 case ISD::FP16_TO_FP: {
3435 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3437 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3440 case ISD::FP_TO_FP16: {
3445 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3448 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3451 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3462 case ISD::ConstantFP: {
3470 case ISD::FSUB: {
3472 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3473 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3474 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3475 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3484 case ISD::SUB: {
3486 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3487 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3489 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3491 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3492 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3495 case ISD::UREM:
3496 case ISD::SREM: {
3498 bool isSigned = Node->getOpcode() == ISD::SREM;
3499 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3500 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3513 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3514 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3528 case ISD::UDIV:
3529 case ISD::SDIV: {
3530 bool isSigned = Node->getOpcode() == ISD::SDIV;
3531 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3552 case ISD::MULHU:
3553 case ISD::MULHS: {
3554 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3555 ISD::SMUL_LOHI;
3565 case ISD::SDIVREM:
3566 case ISD::UDIVREM:
3570 case ISD::MUL: {
3578 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3579 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3580 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3581 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3584 OpToUse = ISD::SMUL_LOHI;
3586 OpToUse = ISD::UMUL_LOHI;
3588 OpToUse = ISD::SMUL_LOHI;
3590 OpToUse = ISD::UMUL_LOHI;
3600 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3601 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3602 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3603 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3605 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3606 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3609 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3610 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3621 case ISD::SADDO:
3622 case ISD::SSUBO: {
3625 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3626 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3643 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3644 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3646 Node->getOpcode() == ISD::SADDO ?
3647 ISD::SETEQ : ISD::SETNE);
3649 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3650 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3652 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3656 case ISD::UADDO:
3657 case ISD::USUBO: {
3660 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3661 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3667 ISD::CondCode CC
3668 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3674 case ISD::UMULO:
3675 case ISD::SMULO: {
3683 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3684 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3685 bool isSigned = Node->getOpcode() == ISD::SMULO;
3687 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3696 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3697 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3699 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3720 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3722 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3731 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3733 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3746 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3748 ISD::SETNE);
3751 DAG.getConstant(0, VT), ISD::SETNE);
3757 case ISD::BUILD_PAIR: {
3759 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3760 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3761 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3764 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3767 case ISD::SELECT:
3771 if (Tmp1.getOpcode() == ISD::SETCC) {
3778 Tmp2, Tmp3, ISD::SETNE);
3782 case ISD::BR_JT: {
3793 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3795 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3799 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3807 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3810 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3814 case ISD::BRCOND:
3819 if (Tmp2.getOpcode() == ISD::SETCC) {
3820 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3826 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3827 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3829 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3830 DAG.getCondCode(ISD::SETNE), Tmp3,
3836 case ISD::SETCC: {
3847 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3872 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3878 case ISD::SELECT_CC: {
3885 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3891 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3892 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3895 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3905 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3914 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3938 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3942 CC = DAG.getCondCode(ISD::SETNE);
3943 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3950 case ISD::BR_CC: {
3969 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3973 Tmp4 = DAG.getCondCode(ISD::SETNE);
3974 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3980 case ISD::BUILD_VECTOR:
3983 case ISD::SRA:
3984 case ISD::SRL:
3985 case ISD::SHL: {
3994 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3998 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4006 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4010 case ISD::GLOBAL_OFFSET_TABLE:
4011 case ISD::GlobalAddress:
4012 case ISD::GlobalTLSAddress:
4013 case ISD::ExternalSymbol:
4014 case ISD::ConstantPool:
4015 case ISD::JumpTable:
4016 case ISD::INTRINSIC_W_CHAIN:
4017 case ISD::INTRINSIC_WO_CHAIN:
4018 case ISD::INTRINSIC_VOID:
4031 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4032 Node->getOpcode() == ISD::SINT_TO_FP ||
4033 Node->getOpcode() == ISD::SETCC) {
4036 if (Node->getOpcode() == ISD::BR_CC)
4042 case ISD::CTTZ:
4043 case ISD::CTTZ_ZERO_UNDEF:
4044 case ISD::CTLZ:
4045 case ISD::CTLZ_ZERO_UNDEF:
4046 case ISD::CTPOP:
4048 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4052 if (Node->getOpcode() == ISD::CTTZ) {
4056 ISD::SETEQ);
4059 } else if (Node->getOpcode() == ISD::CTLZ ||
4060 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4062 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4066 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4068 case ISD::BSWAP: {
4070 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4071 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4072 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4077 case ISD::FP_TO_UINT:
4078 case ISD::FP_TO_SINT:
4080 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4083 case ISD::UINT_TO_FP:
4084 case ISD::SINT_TO_FP:
4086 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4089 case ISD::VAARG: {
4095 TruncOp = ISD::BITCAST;
4099 TruncOp = ISD::TRUNCATE;
4120 case ISD::AND:
4121 case ISD::OR:
4122 case ISD::XOR: {
4125 ExtOp = ISD::BITCAST;
4126 TruncOp = ISD::BITCAST;
4129 ExtOp = ISD::ANY_EXTEND;
4130 TruncOp = ISD::TRUNCATE;
4140 case ISD::SELECT: {
4144 ExtOp = ISD::BITCAST;
4145 TruncOp = ISD::BITCAST;
4147 ExtOp = ISD::ANY_EXTEND;
4148 TruncOp = ISD::TRUNCATE;
4150 ExtOp = ISD::FP_EXTEND;
4151 TruncOp = ISD::FP_ROUND;
4159 if (TruncOp != ISD::FP_ROUND)
4167 case ISD::VECTOR_SHUFFLE: {
4171 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4172 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4176 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4180 case ISD::SETCC: {
4181 unsigned ExtOp = ISD::FP_EXTEND;
4183 ISD::CondCode CCCode =
4185 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4189 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4193 case ISD::BR_CC: {
4194 unsigned ExtOp = ISD::FP_EXTEND;
4196 ISD::CondCode CCCode =
4198 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4202 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4207 case ISD::FADD:
4208 case ISD::FSUB:
4209 case ISD::FMUL:
4210 case ISD::FDIV:
4211 case ISD::FREM:
4212 case ISD::FMINNUM:
4213 case ISD::FMAXNUM:
4214 case ISD::FCOPYSIGN:
4215 case ISD::FPOW: {
4216 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4217 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4219 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4223 case ISD::FMA: {
4224 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4225 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4226 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4228 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4233 case ISD::FPOWI: {
4234 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4237 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4241 case ISD::FFLOOR:
4242 case ISD::FCEIL:
4243 case ISD::FRINT:
4244 case ISD::FNEARBYINT:
4245 case ISD::FROUND:
4246 case ISD::FTRUNC:
4247 case ISD::FNEG:
4248 case ISD::FSQRT:
4249 case ISD::FSIN:
4250 case ISD::FCOS:
4251 case ISD::FLOG:
4252 case ISD::FLOG2:
4253 case ISD::FLOG10:
4254 case ISD::FABS:
4255 case ISD::FEXP:
4256 case ISD::FEXP2: {
4257 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4259 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,