Lines Matching refs:ISD
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
70 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
71 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
73 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
74 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
75 case ISD::SIGN_EXTEND_INREG:
77 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
78 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
79 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
80 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
81 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
83 case ISD::EXTRACT_SUBVECTOR:
85 case ISD::VECTOR_SHUFFLE:
87 case ISD::INSERT_VECTOR_ELT:
89 case ISD::BUILD_VECTOR:
91 case ISD::SCALAR_TO_VECTOR:
93 case ISD::CONCAT_VECTORS:
96 case ISD::SIGN_EXTEND:
97 case ISD::ZERO_EXTEND:
98 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
100 case ISD::FP_TO_SINT:
101 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
103 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
105 case ISD::AND:
106 case ISD::OR:
107 case ISD::XOR:
108 case ISD::ADD:
109 case ISD::SUB:
110 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
112 case ISD::SDIV:
113 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
115 case ISD::UDIV:
116 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
118 case ISD::SADDO:
119 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
120 case ISD::UADDO:
121 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
122 case ISD::SMULO:
123 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
125 case ISD::ATOMIC_LOAD:
128 case ISD::ATOMIC_LOAD_ADD:
129 case ISD::ATOMIC_LOAD_SUB:
130 case ISD::ATOMIC_LOAD_AND:
131 case ISD::ATOMIC_LOAD_OR:
132 case ISD::ATOMIC_LOAD_XOR:
133 case ISD::ATOMIC_LOAD_NAND:
134 case ISD::ATOMIC_LOAD_MIN:
135 case ISD::ATOMIC_LOAD_MAX:
136 case ISD::ATOMIC_LOAD_UMIN:
137 case ISD::ATOMIC_LOAD_UMAX:
138 case ISD::ATOMIC_SWAP:
141 case ISD::ATOMIC_CMP_SWAP:
142 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
161 return DAG.getNode(ISD::AssertSext, SDLoc(N),
168 return DAG.getNode(ISD::AssertZext, SDLoc(N),
201 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
212 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
253 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
258 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
259 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
270 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
284 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
288 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
295 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
298 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
309 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
316 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
328 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
337 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
338 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
339 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
340 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
357 ISD::SUB, dl, NVT, Op,
365 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
373 if (N->getOpcode() == ISD::CTTZ) {
379 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
387 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
400 if (N->getOpcode() == ISD::FP_TO_UINT &&
401 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
402 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
403 NewOpc = ISD::FP_TO_SINT;
410 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
411 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
421 return DAG.getNode(ISD::AssertZext, dl,
438 if (N->getOpcode() == ISD::SIGN_EXTEND)
439 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
441 if (N->getOpcode() == ISD::ZERO_EXTEND)
444 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
454 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
456 ISD::LoadExtType ExtType =
457 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
480 N->getMemOperand(), ISD::SEXTLOAD);
515 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
520 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
523 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
554 return DAG.getNode(ISD::VSELECT, SDLoc(N),
561 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
597 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
604 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
609 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
628 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
636 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
668 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
669 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
671 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
675 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
691 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
698 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
719 if (N->getOpcode() == ISD::SMULO) {
733 if (N->getOpcode() == ISD::UMULO) {
735 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
738 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
741 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
743 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
748 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
792 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
794 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
796 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
799 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
832 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
833 case ISD::ATOMIC_STORE:
836 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
837 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
838 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
839 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
840 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
841 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
842 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
843 case ISD::CONVERT_RNDSAT:
845 case ISD::INSERT_VECTOR_ELT:
847 case ISD::SCALAR_TO_VECTOR:
849 case ISD::VSELECT:
850 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
851 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
852 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
853 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
854 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
855 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
857 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
859 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
861 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
862 case ISD::FP16_TO_FP:
863 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
864 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
866 case ISD::SHL:
867 case ISD::SRA:
868 case ISD::SRL:
869 case ISD::ROTL:
870 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
891 ISD::CondCode CCCode) {
897 case ISD::SETEQ:
898 case ISD::SETNE: {
906 if (OpL->getOpcode() == ISD::AssertSext &&
908 OpR->getOpcode() == ISD::AssertSext &&
918 case ISD::SETUGE:
919 case ISD::SETUGT:
920 case ISD::SETULE:
921 case ISD::SETULT:
928 case ISD::SETGE:
929 case ISD::SETGT:
930 case ISD::SETLT:
931 case ISD::SETLE:
940 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
989 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
991 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1018 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1019 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1020 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1021 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1067 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1105 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1106 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1116 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1165 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
1187 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1198 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1229 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1230 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1231 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1232 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1234 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1235 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1236 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1237 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1238 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1240 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1241 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1242 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1243 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1244 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1245 case ISD::CTLZ_ZERO_UNDEF:
1246 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1247 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1248 case ISD::CTTZ_ZERO_UNDEF:
1249 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1250 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1251 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1252 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1253 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1254 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1255 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1256 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1257 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1258 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1259 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1260 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1261 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1262 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1264 case ISD::ATOMIC_LOAD_ADD:
1265 case ISD::ATOMIC_LOAD_SUB:
1266 case ISD::ATOMIC_LOAD_AND:
1267 case ISD::ATOMIC_LOAD_OR:
1268 case ISD::ATOMIC_LOAD_XOR:
1269 case ISD::ATOMIC_LOAD_NAND:
1270 case ISD::ATOMIC_LOAD_MIN:
1271 case ISD::ATOMIC_LOAD_MAX:
1272 case ISD::ATOMIC_LOAD_UMIN:
1273 case ISD::ATOMIC_LOAD_UMAX:
1274 case ISD::ATOMIC_SWAP:
1275 case ISD::ATOMIC_CMP_SWAP: {
1281 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1285 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1294 N->getOperand(2), ISD::SETEQ);
1302 case ISD::AND:
1303 case ISD::OR:
1304 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1306 case ISD::ADD:
1307 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1309 case ISD::ADDC:
1310 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1312 case ISD::ADDE:
1313 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1315 case ISD::SHL:
1316 case ISD::SRA:
1317 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1319 case ISD::SADDO:
1320 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1321 case ISD::UADDO:
1322 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1323 case ISD::UMULO:
1324 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1364 if (N->getOpcode() == ISD::SHL) {
1369 Hi = DAG.getNode(ISD::SHL, DL,
1375 TLI.isOperationLegalOrCustom(ISD::ADDC,
1380 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1382 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1384 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1385 Hi = DAG.getNode(ISD::OR, DL, NVT,
1386 DAG.getNode(ISD::SHL, DL, NVT, InH,
1388 DAG.getNode(ISD::SRL, DL, NVT, InL,
1394 if (N->getOpcode() == ISD::SRL) {
1399 Lo = DAG.getNode(ISD::SRL, DL,
1406 Lo = DAG.getNode(ISD::OR, DL, NVT,
1407 DAG.getNode(ISD::SRL, DL, NVT, InL,
1409 DAG.getNode(ISD::SHL, DL, NVT, InH,
1411 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1416 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1418 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1421 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1423 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1427 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1430 Lo = DAG.getNode(ISD::OR, DL, NVT,
1431 DAG.getNode(ISD::SRL, DL, NVT, InL,
1433 DAG.getNode(ISD::SHL, DL, NVT, InH,
1435 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1470 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1475 case ISD::SHL:
1477 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1479 case ISD::SRL:
1481 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1483 case ISD::SRA:
1484 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1486 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1497 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1503 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1504 case ISD::SRL:
1505 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1509 if (N->getOpcode() != ISD::SHL)
1519 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1521 if (N->getOpcode() != ISD::SHL)
1546 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1547 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1549 Amt, NVBitsNode, ISD::SETULT);
1554 case ISD::SHL:
1556 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1557 HiS = DAG.getNode(ISD::OR, dl, NVT,
1558 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1561 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1565 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1570 case ISD::SRL:
1572 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1573 LoS = DAG.getNode(ISD::OR, dl, NVT,
1574 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1577 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1581 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1586 case ISD::SRA:
1588 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1589 LoS = DAG.getNode(ISD::OR, dl, NVT,
1590 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1593 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1596 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1598 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1624 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1625 ISD::ADDC : ISD::SUBC,
1630 if (N->getOpcode() == ISD::ADD) {
1631 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1633 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1635 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1637 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1642 if (N->getOpcode() == ISD::ADD) {
1643 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1644 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1646 ISD::SETULT);
1651 ISD::SETULT);
1654 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1656 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1657 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1660 LoOps[0], LoOps[1], ISD::SETULT);
1664 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1679 if (N->getOpcode() == ISD::ADDC) {
1680 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1682 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1684 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1686 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1727 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1753 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1757 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1759 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1774 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1778 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1788 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1789 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1813 DAG.getConstant(0, NVT), ISD::SETNE);
1816 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1819 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1830 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1831 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1843 DAG.getConstant(0, NVT), ISD::SETNE);
1845 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1849 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1888 if (ISD::isNormalLoad(N)) {
1893 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1899 ISD::LoadExtType ExtType = N->getExtensionType();
1919 if (ExtType == ISD::SEXTLOAD) {
1923 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1925 } else if (ExtType == ISD::ZEXTLOAD) {
1929 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1945 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1954 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1972 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1975 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1983 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1988 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1989 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1993 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
2054 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2055 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2073 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2074 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2076 Node->getOpcode() == ISD::SADDO ?
2077 ISD::SETEQ : ISD::SETNE);
2079 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2080 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2082 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2125 if (N->getOpcode() == ISD::SHL) {
2126 PartsOpc = ISD::SHL_PARTS;
2127 } else if (N->getOpcode() == ISD::SRL) {
2128 PartsOpc = ISD::SRL_PARTS;
2130 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2131 PartsOpc = ISD::SRA_PARTS;
2165 if (N->getOpcode() == ISD::SHL) {
2175 } else if (N->getOpcode() == ISD::SRL) {
2186 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2216 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2219 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2234 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2248 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2253 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2261 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2291 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2292 Hi = DAG.getNode(ISD::SRL, dl,
2295 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2306 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2307 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2314 N->getOpcode () == ISD::UADDO ?
2315 ISD::SETULT : ISD::SETUGT);
2327 if (N->getOpcode() == ISD::UMULO) {
2330 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2336 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2339 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2341 ISD::SETNE);
2402 ISD::SETNE);
2454 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2482 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2516 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2517 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2518 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2519 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2520 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2521 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2522 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2523 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2524 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2525 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2526 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2527 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2529 case ISD::SHL:
2530 case ISD::SRA:
2531 case ISD::SRL:
2532 case ISD::ROTL:
2533 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2534 case ISD::RETURNADDR:
2535 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2537 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2559 ISD::CondCode &CCCode,
2565 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2570 NewLHS = DAG.getNode(ISD::AND, dl,
2578 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2579 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2580 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2588 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2589 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2596 ISD::CondCode LowCC;
2599 case ISD::SETLT:
2600 case ISD::SETULT: LowCC = ISD::SETULT; break;
2601 case ISD::SETGT:
2602 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2603 case ISD::SETLE:
2604 case ISD::SETULE: LowCC = ISD::SETULE; break;
2605 case ISD::SETGE:
2606 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2630 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2638 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2639 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2641 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2642 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2652 LHSHi, RHSHi, ISD::SETEQ, false,
2656 LHSHi, RHSHi, ISD::SETEQ);
2664 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2671 CCCode = ISD::SETNE;
2682 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2689 CCCode = ISD::SETNE;
2700 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2743 if (ISD::isNormalStore(N))
2746 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2782 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2788 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2804 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2807 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2808 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2818 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2826 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2833 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2847 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2849 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2876 ISD::SETLT);
2890 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2896 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2901 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2913 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2942 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2944 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2947 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2952 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2989 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2995 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3010 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3012 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3036 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3039 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3043 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3056 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3058 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3066 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3092 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3094 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3099 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);