Cross Reference: /external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines Matching defs:V0
264   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
265   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
266   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
267   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
270   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
271   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
272   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1564 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1565   SDLoc dl(V0.getNode());
1570   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1575 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1576   SDLoc dl(V0.getNode());
1581   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1586 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1587   SDLoc dl(V0.getNode());
1591   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1596 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1597   SDLoc dl(V0.getNode());
1601   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1606 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1608   SDLoc dl(V0.getNode());
1615   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1621 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1623   SDLoc dl(V0.getNode());
1629   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1635 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1637   SDLoc dl(V0.getNode());
1643   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1962       SDValue V0 = N->getOperand(Vec0Idx + 0);
1965         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1973         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2015   SDValue V0 = N->getOperand(Vec0Idx + 0);
2021   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2127   SDValue V0 = N->getOperand(Vec0Idx + 0);
2131       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2133       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2140       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2142       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2263   SDValue V0 = N->getOperand(FirstTblReg + 0);
2266     RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2274     RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
3302     SDValue V0 = N->getOperand(0);
3304     SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3387     SDValue V0 = N->getOperand(i+1);
3389     unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();