Cross Reference: /external/llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines Matching defs:VA
1345     CCValAssign VA = RVLocs[i];
1350       assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1357     if (VA.needsCustom()) {
1359       SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1363       VA = RVLocs[++i]; // skip ahead to next loc
1364       SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1372       if (VA.getLocVT() == MVT::v2f64) {
1377         VA = RVLocs[++i]; // skip ahead to next loc
1378         Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1381         VA = RVLocs[++i]; // skip ahead to next loc
1382         Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1392       Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1398     switch (VA.getLocInfo()) {
1402       Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1417                                     const CCValAssign &VA,
1419   unsigned LocMemOffset = VA.getLocMemOffset();
1430                                          CCValAssign &VA, CCValAssign &NextVA,
1438   RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1527     CCValAssign &VA = ArgLocs[i];
1533     switch (VA.getLocInfo()) {
1537       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1540       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1543       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1546       Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1551     if (VA.needsCustom()) {
1552       if (VA.getLocVT() == MVT::v2f64) {
1559                          VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1561         VA = ArgLocs[++i]; // skip ahead to next loc
1562         if (VA.isRegLoc()) {
1564                            VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1566           assert(VA.isMemLoc());
1569                                                  dl, DAG, VA, Flags));
1572         PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1575     } else if (VA.isRegLoc()) {
1577         assert(VA.getLocVT() == MVT::i32 &&
1583       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1585       assert(VA.isMemLoc());
1619         unsigned LocMemOffset = VA.getLocMemOffset();
1635       assert(VA.isMemLoc());
1638                                              dl, DAG, VA, Flags));
2097         CCValAssign &VA = ArgLocs[i];
2098         EVT RegVT = VA.getLocVT();
2101         if (VA.getLocInfo() == CCValAssign::Indirect)
2103         if (VA.needsCustom()) {
2108           if (!VA.isRegLoc())
2118         } else if (!VA.isRegLoc()) {
2119           if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2204     CCValAssign &VA = RVLocs[i];
2205     assert(VA.isRegLoc() && "Can only return in registers!");
2209     switch (VA.getLocInfo()) {
2213       Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2217     if (VA.needsCustom()) {
2218       if (VA.getLocVT() == MVT::v2f64) {
2225         Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2229         RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2230         VA = RVLocs[++i]; // skip ahead to next loc
2231         Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2235         RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2236         VA = RVLocs[++i]; // skip ahead to next loc
2246       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2250       RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2251       VA = RVLocs[++i]; // skip ahead to next loc
2252       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2256       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2261     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2796 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2809   unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2957     CCValAssign &VA = ArgLocs[i];
2958     unsigned Index = VA.getValNo();
2963     assert(VA.isMemLoc() && "unexpected byval pointer in reg");
2983     CCValAssign &VA = ArgLocs[i];
2984     if (Ins[VA.getValNo()].isOrigArg()) {
2986                    Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
2987       CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
2990     if (VA.isRegLoc()) {
2991       EVT RegVT = VA.getLocVT();
2993       if (VA.needsCustom()) {
2996         if (VA.getLocVT() == MVT::v2f64) {
2997           SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2999           VA = ArgLocs[++i]; // skip ahead to next loc
3001           if (VA.isMemLoc()) {
3002             int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3008             ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3017           ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3035         unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3042       switch (VA.getLocInfo()) {
3046         ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3050                                DAG.getValueType(VA.getValVT()));
3051         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3055                                DAG.getValueType(VA.getValVT()));
3056         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3062     } else { // VA.isRegLoc()
3065       assert(VA.isMemLoc());
3066       assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3068       int index = VA.getValNo();
3086                                             CurByValIndex, VA.getLocMemOffset(),
3091             unsigned FIOffset = VA.getLocMemOffset();
3092             int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3097             InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,