69 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
71   unsigned Opcode = MI->getOpcode();
79     switch (MI->getOperand(0).getImm()) {
102       printInstruction(MI, STI, O);
106     printPredicateOperand(MI, 1, STI, O);
115     const MCOperand &Dst = MI->getOperand(0);
116     const MCOperand &MO1 = MI->getOperand(1);
117     const MCOperand &MO2 = MI->getOperand(2);
118     const MCOperand &MO3 = MI->getOperand(3);
121     printSBitModifierOperand(MI, 6, STI, O);
122     printPredicateOperand(MI, 4, STI, O);
138     const MCOperand &Dst = MI->getOperand(0);
139     const MCOperand &MO1 = MI->getOperand(1);
140     const MCOperand &MO2 = MI->getOperand(2);
143     printSBitModifierOperand(MI, 5, STI, O);
144     printPredicateOperand(MI, 3, STI, O);
165     if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
168       printPredicateOperand(MI, 2, STI, O);
172       printRegisterList(MI, 4, STI, O);
179     if (MI->getOperand(2).getReg() == ARM::SP &&
180         MI->getOperand(3).getImm() == -4) {
182       printPredicateOperand(MI, 4, STI, O);
184       printRegName(O, MI->getOperand(1).getReg());
194     if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
197       printPredicateOperand(MI, 2, STI, O);
201       printRegisterList(MI, 4, STI, O);
208     if (MI->getOperand(2).getReg() == ARM::SP &&
209         MI->getOperand(4).getImm() == 4) {
211       printPredicateOperand(MI, 5, STI, O);
213       printRegName(O, MI->getOperand(0).getReg());
223     if (MI->getOperand(0).getReg() == ARM::SP) {
225       printPredicateOperand(MI, 2, STI, O);
227       printRegisterList(MI, 4, STI, O);
236     if (MI->getOperand(0).getReg() == ARM::SP) {
238       printPredicateOperand(MI, 2, STI, O);
240       printRegisterList(MI, 4, STI, O);
248     unsigned BaseReg = MI->getOperand(0).getReg();
249     for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
250       if (MI->getOperand(i).getReg() == BaseReg)
256     printPredicateOperand(MI, 1, STI, O);
262     printRegisterList(MI, 3, STI, O);
279     unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
286         NewMI.addOperand(MI->getOperand(0));
292       for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
293         NewMI.addOperand(MI->getOperand(i));
303     if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
304         MI->getOperand(0).getImm() == 0 &&
307       printPredicateOperand(MI, 1, STI, O);
315   printInstruction(MI, STI, O);
319 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
321   const MCOperand &Op = MI->getOperand(OpNo);
357 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
360   const MCOperand &MO1 = MI->getOperand(OpNum);
387 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
390   const MCOperand &MO1 = MI->getOperand(OpNum);
391   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
392   const MCOperand &MO3 = MI->getOperand(OpNum + 2);
407 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
410   const MCOperand &MO1 = MI->getOperand(OpNum);
411   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
424 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
427   const MCOperand &MO1 = MI->getOperand(Op);
428   const MCOperand &MO2 = MI->getOperand(Op + 1);
429   const MCOperand &MO3 = MI->getOperand(Op + 2);
453 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
456   const MCOperand &MO1 = MI->getOperand(Op);
457   const MCOperand &MO2 = MI->getOperand(Op + 1);
465 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
468   const MCOperand &MO1 = MI->getOperand(Op);
469   const MCOperand &MO2 = MI->getOperand(Op + 1);
477 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
480   const MCOperand &MO1 = MI->getOperand(Op);
483     printOperand(MI, Op, STI, O);
488   const MCOperand &MO3 = MI->getOperand(Op + 2);
493   printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
496 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
500   const MCOperand &MO1 = MI->getOperand(OpNum);
501   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
522 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
525   const MCOperand &MO1 = MI->getOperand(Op);
526   const MCOperand &MO2 = MI->getOperand(Op + 1);
527   const MCOperand &MO3 = MI->getOperand(Op + 2);
551 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
554   const MCOperand &MO1 = MI->getOperand(Op);
556     printOperand(MI, Op, STI, O);
560   assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
563   printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
566 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
570   const MCOperand &MO1 = MI->getOperand(OpNum);
571   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
585 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
588   const MCOperand &MO = MI->getOperand(OpNum);
594 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
597   const MCOperand &MO1 = MI->getOperand(OpNum);
598   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
604 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
607   const MCOperand &MO = MI->getOperand(OpNum);
613 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
617       ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
622 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
625   const MCOperand &MO1 = MI->getOperand(OpNum);
626   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
629     printOperand(MI, OpNum, STI, O);
645 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
648   const MCOperand &MO1 = MI->getOperand(OpNum);
649   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
659 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
662   const MCOperand &MO1 = MI->getOperand(OpNum);
668 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
672   const MCOperand &MO = MI->getOperand(OpNum);
681 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
685   const MCOperand &MO = MI->getOperand(OpNum);
694 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
697   unsigned val = MI->getOperand(OpNum).getImm();
701 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
704   unsigned val = MI->getOperand(OpNum).getImm();
708 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
711   unsigned ShiftOp = MI->getOperand(OpNum).getImm();
722 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
725   unsigned Imm = MI->getOperand(OpNum).getImm();
732 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
735   unsigned Imm = MI->getOperand(OpNum).getImm();
743 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
747   for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
750     printRegName(O, MI->getOperand(i).getReg());
755 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
758   unsigned Reg = MI->getOperand(OpNum).getReg();
764 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
767   const MCOperand &Op = MI->getOperand(OpNum);
774 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
776   const MCOperand &Op = MI->getOperand(OpNum);
780 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
782   const MCOperand &Op = MI->getOperand(OpNum);
792 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
795   const MCOperand &Op = MI->getOperand(OpNum);
802     unsigned Opcode = MI->getOpcode();
941 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
944   uint32_t Banked = MI->getOperand(OpNum).getImm();
993 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
996   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1004 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
1008   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1012 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1015   if (MI->getOperand(OpNum).getReg()) {
1016     assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1022 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1025   O << MI->getOperand(OpNum).getImm();
1028 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1031   O << "p" << MI->getOperand(OpNum).getImm();
1034 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1037   O << "c" << MI->getOperand(OpNum).getImm();
1040 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1043   O << "{" << MI->getOperand(OpNum).getImm() << "}";
1046 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1052 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1055   const MCOperand &MO = MI->getOperand(OpNum);
1074 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1077   O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1081 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1084   unsigned Imm = MI->getOperand(OpNum).getImm();
1089 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1093   unsigned Mask = MI->getOperand(OpNum).getImm();
1094   unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1107 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1110   const MCOperand &MO1 = MI->getOperand(Op);
1111   const MCOperand &MO2 = MI->getOperand(Op + 1);
1114     printOperand(MI, Op, STI, O);
1127 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1132   const MCOperand &MO1 = MI->getOperand(Op);
1133   const MCOperand &MO2 = MI->getOperand(Op + 1);
1136     printOperand(MI, Op, STI, O);
1149 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1153   printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1156 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1160   printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1163 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1167   printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1170 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1173   printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1180 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1183   const MCOperand &MO1 = MI->getOperand(OpNum);
1184   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1196 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1199   const MCOperand &MO1 = MI->getOperand(OpNum);
1200   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1203     printOperand(MI, OpNum, STI, O);
1224 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1228   const MCOperand &MO1 = MI->getOperand(OpNum);
1229   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1248 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1252   const MCOperand &MO1 = MI->getOperand(OpNum);
1253   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1256     printOperand(MI, OpNum, STI, O);
1280     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1282   const MCOperand &MO1 = MI->getOperand(OpNum);
1283   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1295     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1297   const MCOperand &MO1 = MI->getOperand(OpNum);
1310     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1312   const MCOperand &MO1 = MI->getOperand(OpNum);
1327 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1331   const MCOperand &MO1 = MI->getOperand(OpNum);
1332   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1333   const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1350 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1353   const MCOperand &MO = MI->getOperand(OpNum);
1358 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1361   unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1369 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1372   unsigned Imm = MI->getOperand(OpNum).getImm();
1376 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1379   unsigned Imm = MI->getOperand(OpNum).getImm();
1399 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1402   MCOperand Op = MI->getOperand(OpNum);
1406     return printOperand(MI, OpNum, STI, O);
1412   switch (MI->getOpcode()) {
1415     PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1440 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1442   O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1446 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1448   O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1452 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1455   O << "[" << MI->getOperand(OpNum).getImm() << "]";
1458 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1462   printRegName(O, MI->getOperand(OpNum).getReg());
1466 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1469   unsigned Reg = MI->getOperand(OpNum).getReg();
1479 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1482   unsigned Reg = MI->getOperand(OpNum).getReg();
1492 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1499   printRegName(O, MI->getOperand(OpNum).getReg());
1501   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1503   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1507 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1514   printRegName(O, MI->getOperand(OpNum).getReg());
1516   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1518   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1520   printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1524 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1529   printRegName(O, MI->getOperand(OpNum).getReg());
1533 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1537   unsigned Reg = MI->getOperand(OpNum).getReg();
1547 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1555   printRegName(O, MI->getOperand(OpNum).getReg());
1557   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1559   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1563 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1571   printRegName(O, MI->getOperand(OpNum).getReg());
1573   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1575   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1577   printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1582     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1584   unsigned Reg = MI->getOperand(OpNum).getReg();
1595     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1601   printRegName(O, MI->getOperand(OpNum).getReg());
1603   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1605   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1610     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1616   printRegName(O, MI->getOperand(OpNum).getReg());
1618   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1620   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1622   printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1626 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1634   printRegName(O, MI->getOperand(OpNum).getReg());
1636   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1638   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1642 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1649   printRegName(O, MI->getOperand(OpNum).getReg());
1651   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1653   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1655   printRegName(O, MI->getOperand(OpNum).getReg() + 6);

Indexes created Fri Jan 08 05:29:00 CET 2016