Cross Reference: /external/llvm/lib/Target/R600/SILowerControlFlow.cpp

Lines Matching refs:MI
78   void SkipIfDead(MachineInstr &MI);
80   void If(MachineInstr &MI);
81   void Else(MachineInstr &MI);
82   void Break(MachineInstr &MI);
83   void IfBreak(MachineInstr &MI);
84   void ElseBreak(MachineInstr &MI);
85   void Loop(MachineInstr &MI);
86   void EndCf(MachineInstr &MI);
88   void Kill(MachineInstr &MI);
89   void Branch(MachineInstr &MI);
91   void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
92   void IndirectSrc(MachineInstr &MI);
93   void IndirectDst(MachineInstr &MI);
146 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
148   MachineBasicBlock &MBB = *MI.getParent();
149   DebugLoc DL = MI.getDebugLoc();
156   MachineBasicBlock::iterator Insert = &MI;
180 void SILowerControlFlowPass::If(MachineInstr &MI) {
181   MachineBasicBlock &MBB = *MI.getParent();
182   DebugLoc DL = MI.getDebugLoc();
183   unsigned Reg = MI.getOperand(0).getReg();
184   unsigned Vcc = MI.getOperand(1).getReg();
186   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
189   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
193   Skip(MI, MI.getOperand(2));
195   MI.eraseFromParent();
198 void SILowerControlFlowPass::Else(MachineInstr &MI) {
199   MachineBasicBlock &MBB = *MI.getParent();
200   DebugLoc DL = MI.getDebugLoc();
201   unsigned Dst = MI.getOperand(0).getReg();
202   unsigned Src = MI.getOperand(1).getReg();
208   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
212   Skip(MI, MI.getOperand(2));
214   MI.eraseFromParent();
217 void SILowerControlFlowPass::Break(MachineInstr &MI) {
218   MachineBasicBlock &MBB = *MI.getParent();
219   DebugLoc DL = MI.getDebugLoc();
221   unsigned Dst = MI.getOperand(0).getReg();
222   unsigned Src = MI.getOperand(1).getReg();
224   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
228   MI.eraseFromParent();
231 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
232   MachineBasicBlock &MBB = *MI.getParent();
233   DebugLoc DL = MI.getDebugLoc();
235   unsigned Dst = MI.getOperand(0).getReg();
236   unsigned Vcc = MI.getOperand(1).getReg();
237   unsigned Src = MI.getOperand(2).getReg();
239   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
243   MI.eraseFromParent();
246 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
247   MachineBasicBlock &MBB = *MI.getParent();
248   DebugLoc DL = MI.getDebugLoc();
250   unsigned Dst = MI.getOperand(0).getReg();
251   unsigned Saved = MI.getOperand(1).getReg();
252   unsigned Src = MI.getOperand(2).getReg();
254   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
258   MI.eraseFromParent();
261 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
262   MachineBasicBlock &MBB = *MI.getParent();
263   DebugLoc DL = MI.getDebugLoc();
264   unsigned Src = MI.getOperand(0).getReg();
266   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
270   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
271           .addOperand(MI.getOperand(1))
274   MI.eraseFromParent();
277 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
278   MachineBasicBlock &MBB = *MI.getParent();
279   DebugLoc DL = MI.getDebugLoc();
280   unsigned Reg = MI.getOperand(0).getReg();
287   MI.eraseFromParent();
290 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
291   if (MI.getOperand(0).getMBB() == MI.getParent()->getNextNode())
292     MI.eraseFromParent();
297 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
298   MachineBasicBlock &MBB = *MI.getParent();
299   DebugLoc DL = MI.getDebugLoc();
300   const MachineOperand &Op = MI.getOperand(0);
314       BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
318     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
323   MI.eraseFromParent();
326 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
328   MachineBasicBlock &MBB = *MI.getParent();
329   DebugLoc DL = MI.getDebugLoc();
330   MachineBasicBlock::iterator I = MI;
332   unsigned Save = MI.getOperand(1).getReg();
333   unsigned Idx = MI.getOperand(3).getReg();
336     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
345     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
349     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
354     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
358     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
363     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
370     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
375     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
380     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
384   MI.eraseFromParent();
387 void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
389   MachineBasicBlock &MBB = *MI.getParent();
390   DebugLoc DL = MI.getDebugLoc();
392   unsigned Dst = MI.getOperand(0).getReg();
393   unsigned Vec = MI.getOperand(2).getReg();
394   unsigned Off = MI.getOperand(4).getImm();
405   LoadM0(MI, MovRel);
408 void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
410   MachineBasicBlock &MBB = *MI.getParent();
411   DebugLoc DL = MI.getDebugLoc();
413   unsigned Dst = MI.getOperand(0).getReg();
414   unsigned Off = MI.getOperand(4).getImm();
415   unsigned Val = MI.getOperand(5).getReg();
427   LoadM0(MI, MovRel);
449       MachineInstr &MI = *I;
450       if (TII->isWQM(MI.getOpcode()) || TII->isDS(MI.getOpcode()))
454       if (TII->isFLAT(MI.getOpcode()))
457       switch (MI.getOpcode()) {
461           If(MI);
465           Else(MI);
469           Break(MI);
473           IfBreak(MI);
477           ElseBreak(MI);
482           Loop(MI);
487             SkipIfDead(MI);
490           EndCf(MI);
495             SkipIfDead(MI);
498           Kill(MI);
502           Branch(MI);
506           IndirectSrc(MI);
514           IndirectDst(MI);