Searched defs:Cand (Results 1 - 3 of 3) sorted by relevance

/external/llvm/lib/CodeGen/
H A DRegAllocGreedy.cpp337 void growRegion(GlobalSplitCandidate &Cand);
1004 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) { argument
1007 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
1040 if (Cand.PhysReg)
1041 addThroughConstraints(Cand.Intf, NewBlocks);
1061 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) { argument
1067 Cand.reset(IntfCache, 0);
1073 SpillPlacer->prepare(Cand.LiveBundles);
1075 // The static split cost will be zero since Cand.Intf reports no interference.
1077 if (!addSplitConstraints(Cand
1121 calcGlobalSplitCost(GlobalSplitCandidate &Cand) argument
1197 GlobalSplitCandidate &Cand = GlobalCand[CandIn]; local
1206 GlobalSplitCandidate &Cand = GlobalCand[CandOut]; local
1246 GlobalSplitCandidate &Cand = GlobalCand[CandIn]; local
1254 GlobalSplitCandidate &Cand = GlobalCand[CandOut]; local
1375 GlobalSplitCandidate &Cand = GlobalCand[NumCands]; local
1437 GlobalSplitCandidate &Cand = GlobalCand[BestCand]; local
1449 GlobalSplitCandidate &Cand = GlobalCand.front(); local
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H A DMachineScheduler.cpp2244 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) { argument
2248 switch (Cand.Reason) {
2252 P = Cand.RPDelta.Excess;
2255 P = Cand.RPDelta.CriticalMax;
2258 P = Cand.RPDelta.CurrentMax;
2261 ResIdx = Cand.Policy.ReduceResIdx;
2264 ResIdx = Cand.Policy.DemandResIdx;
2267 Latency = Cand.SU->getDepth();
2270 Latency = Cand.SU->getHeight();
2273 Latency = Cand
2298 tryLess(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) argument
2315 tryGreater(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) argument
2332 tryLatency(GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone) argument
2358 tracePick(const GenericSchedulerBase::SchedCandidate &Cand, bool IsTop) argument
2497 tryPressure(const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) argument
2564 tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary &Zone, const RegPressureTracker &RPTracker, RegPressureTracker &TempTracker) argument
2699 pickNodeFromQueue(SchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Cand) argument
2941 tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) argument
2974 pickNodeFromQueue(SchedCandidate &Cand) argument
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/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp421 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]); local
423 if (Cand == this || getSubRegIndex(Cand))
425 // Check if each component of Cand is already a sub-register.
429 assert(!Cand->ExplicitSubRegs.empty() &&
431 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) {
432 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j]))
440 // If some Cand sub-register is not part of this register, or if Cand only
445 // Each part of Cand i
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