/external/llvm/lib/MC/MCParser/ |
H A D | DarwinAsmParser.cpp | 467 SMLoc IDLoc) { 482 return Warning(IDLoc, "ignoring directive .dump for now"); 484 return Warning(IDLoc, "ignoring directive .load for now"); 624 bool DarwinAsmParser::parseDirectiveSecureLogUnique(StringRef, SMLoc IDLoc) { argument 630 return Error(IDLoc, ".secure_log_unique specified multiple times"); 635 return Error(IDLoc, ".secure_log_unique used but AS_SECURE_LOG_FILE " 646 return Error(IDLoc, Twine("can't open secure log file: ") + 653 unsigned CurBuf = getSourceManager().FindBufferContainingLoc(IDLoc); 655 << ":" << getSourceManager().FindLineNumber(IDLoc, CurBuf) << ":" 665 bool DarwinAsmParser::parseDirectiveSecureLogReset(StringRef, SMLoc IDLoc) { argument 466 parseDirectiveDumpOrLoad(StringRef Directive, SMLoc IDLoc) argument 692 SMLoc IDLoc = getLexer().getLoc(); local 775 SMLoc IDLoc = getLexer().getLoc(); local [all...] |
H A D | AsmParser.cpp | 1189 SMLoc IDLoc = ID.getLoc(); local 1194 return parseCppHashLineFilenameComment(IDLoc); 1239 return parseDirectiveIf(IDLoc, DirKind); 1241 return parseDirectiveIfb(IDLoc, true); 1243 return parseDirectiveIfb(IDLoc, false); 1245 return parseDirectiveIfc(IDLoc, true); 1247 return parseDirectiveIfeqs(IDLoc, true); 1249 return parseDirectiveIfc(IDLoc, false); 1251 return parseDirectiveIfeqs(IDLoc, false); 1253 return parseDirectiveIfdef(IDLoc, tru 2003 SMLoc IDLoc = Lexer.getLoc(); local 3704 SMLoc IDLoc = getLexer().getLoc(); local 4484 parseDirectiveMSEmit(SMLoc IDLoc, ParseStatementInfo &Info, size_t Len) argument 4501 parseDirectiveMSAlign(SMLoc IDLoc, ParseStatementInfo &Info) argument [all...] |
/external/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 386 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument 397 Inst.setLoc(IDLoc); 403 return Error(IDLoc, 407 SMLoc ErrorLoc = IDLoc; 410 return Error(IDLoc, "too few operands for instruction"); 414 ErrorLoc = IDLoc; 420 return Error(IDLoc, "invalid instruction mnemonic");
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 257 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1129 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument 1139 Inst.setLoc(IDLoc); 1143 return Error(IDLoc, "instruction use requires an option to be enabled"); 1145 return Error(IDLoc, "unrecognized instruction mnemonic"); 1147 SMLoc ErrorLoc = IDLoc; 1150 return Error(IDLoc, "too few operands for instruction"); 1153 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
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/external/llvm/lib/Target/R600/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 329 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 505 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument 515 Inst.setLoc(IDLoc); 519 return Error(IDLoc, "missing feature"); 522 return Error(IDLoc, "unrecognized instruction mnemonic"); 525 SMLoc ErrorLoc = IDLoc; 528 return Error(IDLoc, "too few operands for instruction"); 533 ErrorLoc = IDLoc;
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/external/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 378 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 713 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument 725 Inst.setLoc(IDLoc); 742 return Error(IDLoc, Msg); 746 SMLoc ErrorLoc = IDLoc; 749 return Error(IDLoc, "too few operands for instruction"); 753 ErrorLoc = IDLoc; 759 return Error(IDLoc, "invalid instruction");
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 696 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 701 void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands, 704 bool ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo, 707 bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, 712 bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, 2465 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument 2470 return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo, 2472 return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo, 2476 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, argument 2495 Inst.setLoc(IDLoc); 2502 ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo, bool MatchingInlineAsm) argument 2518 MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument 2693 MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 85 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 3606 bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument 3850 Inst.setLoc(IDLoc); 3867 return Error(IDLoc, Msg); 3870 return showMatchError(IDLoc, MatchResult); 3872 SMLoc ErrorLoc = IDLoc; 3875 return Error(IDLoc, "too few operands for instruction"); 3879 ErrorLoc = IDLoc; 3937 return Error(IDLoc, "too few operands for instruction"); 3942 ErrorLoc = IDLoc; [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 123 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 176 bool expandInstruction(MCInst &Inst, SMLoc IDLoc, 179 bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, 182 bool expandLoadImm(MCInst &Inst, SMLoc IDLoc, 185 bool expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc, 188 bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc, 190 bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, 193 void expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc, 196 void expandMemInst(MCInst &Inst, SMLoc IDLoc, 200 bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, 1234 processInstruction(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1388 createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions); local 1607 expandInstruction(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1636 createShiftOr(MCOperand Operand, unsigned RegNo, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1657 createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1661 IDLoc, Instructions); local 1665 expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1707 expandLoadImm(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1803 expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1852 expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1892 expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1956 expandUncondBranchMMPseudo( MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1995 expandMemInst(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) argument 2112 expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 2134 createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 2162 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 375 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 8577 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument 8610 Warning(IDLoc, "deprecated instruction in IT block"); 8624 Inst.setLoc(IDLoc); 8640 return Error(IDLoc, Msg); 8643 SMLoc ErrorLoc = IDLoc; 8646 return Error(IDLoc, "too few operands for instruction"); 8649 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8655 return Error(IDLoc, "invalid instruction", 8658 return Error(IDLoc, "fla [all...] |