/external/llvm/include/llvm/IR/ |
H A D | GetElementPtrTypeIterator.h | 102 gep_type_begin(Type *Op0, ArrayRef<T> A) { argument 103 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin()); 108 gep_type_end(Type * /*Op0*/, ArrayRef<T> A) {
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H A D | PatternMatch.h | 1234 inline typename m_Intrinsic_Ty<T0>::Ty m_Intrinsic(const T0 &Op0) { argument 1235 return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0)); 1239 inline typename m_Intrinsic_Ty<T0, T1>::Ty m_Intrinsic(const T0 &Op0, argument 1241 return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1)); 1246 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument 1247 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2)); 1253 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument 1254 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3)); 1259 inline typename m_Intrinsic_Ty<Opnd0>::Ty m_BSwap(const Opnd0 &Op0) { argument 1260 return m_Intrinsic<Intrinsic::bswap>(Op0); 1264 m_FMin(const Opnd0 &Op0, const Opnd1 &Op1) argument 1270 m_FMax(const Opnd0 &Op0, const Opnd1 &Op1) argument [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 837 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local 839 Ops[1].getAsInteger(10, Op0); 844 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 868 uint32_t Op0 = (Bits >> 14) & 0x3; 874 return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 100 MachineOperand &Op0 = MI->getOperand(0); local 111 NewMI->addOperand(Op0); 143 MachineOperand &Op0 = MI->getOperand(0); local 155 NewMI->addOperand(Op0); 185 MachineOperand &Op0 = MI->getOperand(0); local 196 NewMI->addOperand(Op0); 222 MachineOperand &Op0 = MI->getOperand(0); local 232 NewMI->addOperand(Op0);
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H A D | HexagonPeephole.cpp | 246 MachineOperand &Op0 = MI->getOperand(0); local 247 unsigned Reg0 = Op0.getReg();
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H A D | HexagonCopyToCombine.cpp | 130 const MachineOperand &Op0 = MI->getOperand(0); local 132 assert(Op0.isReg()); 134 unsigned DestReg = Op0.getReg();
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 200 SDValue Op0, Op1; local 205 if (!SelectADDRrr(Op, Op0, Op1)) 206 SelectADDRri(Op, Op0, Op1); 210 OutOps.push_back(Op0);
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/external/llvm/lib/Transforms/Scalar/ |
H A D | CorrelatedValuePropagation.cpp | 167 Value *Op0 = C->getOperand(0); local 168 if (isa<Instruction>(Op0) && 169 cast<Instruction>(Op0)->getParent() == C->getParent())
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H A D | Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 375 Scatterer Op0 = scatter(&I, I.getOperand(0)); local 377 assert(Op0.size() == NumElems && "Mismatched binary operation"); 382 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 403 Scatterer Op0 local 409 Value *Op0 = SI.getOperand(0); local 470 Scatterer Op0 = scatter(&CI, CI.getOperand(0)); local 490 Scatterer Op0 = scatter(&BCI, BCI.getOperand(0)); local 542 Scatterer Op0 = scatter(&SVI, SVI.getOperand(0)); local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | IntrinsicLowering.cpp | 489 Value *Op0 = CI->getArgOperand(0); local 490 Type *IntPtr = DL.getIntPtrType(Op0->getType()); 494 Ops[0] = Op0;
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/external/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 2021 GenericValue Op0 = getOperandValue(CE->getOperand(0), SF); local 2026 case Instruction::Add: Dest.IntVal = Op0.IntVal + Op1.IntVal; break; 2027 case Instruction::Sub: Dest.IntVal = Op0.IntVal - Op1.IntVal; break; 2028 case Instruction::Mul: Dest.IntVal = Op0.IntVal * Op1.IntVal; break; 2029 case Instruction::FAdd: executeFAddInst(Dest, Op0, Op1, Ty); break; 2030 case Instruction::FSub: executeFSubInst(Dest, Op0, Op1, Ty); break; 2031 case Instruction::FMul: executeFMulInst(Dest, Op0, Op1, Ty); break; 2032 case Instruction::FDiv: executeFDivInst(Dest, Op0, Op1, Ty); break; 2033 case Instruction::FRem: executeFRemInst(Dest, Op0, Op1, Ty); break; 2034 case Instruction::SDiv: Dest.IntVal = Op0 [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 285 SDValue Op0, Op1; local 289 if (!SelectAddr(Op, Op0, Op1)) 294 OutOps.push_back(Op0);
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/external/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 594 Value *Op0 = CI->getArgOperand(0); local 606 Rep = Builder.CreateShuffleVector(Op0, Op1, ConstantVector::get(Idxs)); 611 Value *Op0 = CI->getArgOperand(0); local 652 Rep = Builder.CreateShuffleVector(Op0, Rep, ConstantVector::get(Idxs2)); 657 Value *Op0 = CI->getArgOperand(0); local 672 Value *UndefV = UndefValue::get(Op0->getType()); 673 Rep = Builder.CreateShuffleVector(Op0, UndefV, ConstantVector::get(Idxs)); 686 Value *Op0 = CI->getArgOperand(0); local 707 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVecto [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 33 if (isa<Constant>(Op0)) 39 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) 321 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, argument 339 CanEvaluateShifted(Op0, COp1->getZExtValue(), isLeftShift, *this, &I)) { 341 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n"); 344 I, GetShiftedValue(Op0, COp1->getZExtValue(), isLeftShift, *this, DL)); 349 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits(); 355 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0)) 362 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) [all...] |
H A D | InstCombineMulDivRem.cpp | 170 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 175 if (Value *V = SimplifyMulInst(Op0, Op1, DL, TLI, DT, AC)) 183 BinaryOperator *BO = BinaryOperator::CreateNeg(Op0, I.getName()); 241 if (Op0->hasOneUse()) { 244 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) 246 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) 260 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) 264 if (isa<PHINode>(Op0)) 272 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) { 282 if (Value *Op0v = dyn_castNegVal(Op0)) { // 525 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 780 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 950 foldUDivPow2Cst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 961 foldUDivNegCst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 970 foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 993 visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, SmallVectorImpl<UDivFoldAction> &Actions, unsigned Depth = 0) argument 1033 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1106 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1204 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1338 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1370 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1405 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1480 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
/external/llvm/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 623 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 626 Ops.push_back(Op0); 641 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 644 Ops.push_back(Op0);
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/external/llvm/lib/Analysis/ |
H A D | ConstantFolding.cpp | 616 /// One of Op0/Op1 is a constant expression. 620 static Constant *SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0, argument 630 unsigned BitWidth = DL.getTypeSizeInBits(Op0->getType()->getScalarType()); 633 computeKnownBits(Op0, KnownZero0, KnownOne0, DL); 636 // All the bits of Op0 that the 'and' could be masking are already zero. 637 return Op0; 647 return ConstantInt::get(Op0->getType(), KnownOne); 657 if (IsConstantOffsetFromGlobal(Op0, GV1, Offs1, DL)) 659 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType()); 664 return ConstantInt::get(Op0 [all...] |
H A D | InstructionSimplify.cpp | 147 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)) 148 if (Op0->getOpcode() == OpcodeToExpand) { 150 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS; 206 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); 210 if (Op0 && Op0->getOpcode() == Opcode) { 211 Value *A = Op0->getOperand(0); 212 Value *B = Op0->getOperand(1); 252 if (Op0 530 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 586 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 662 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 779 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 789 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 831 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 867 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 895 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 958 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 967 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 976 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 985 SimplifyMulInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 995 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1081 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1089 SimplifySDivInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1099 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1107 SimplifyUDivInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1115 SimplifyFDivInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned) argument 1134 SimplifyFDivInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1145 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1206 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1214 SimplifySRemInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1224 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1232 SimplifyURemInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1240 SimplifyFRemInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &, unsigned) argument 1259 SimplifyFRemInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1297 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1335 SimplifyRightShift(unsigned Opcode, Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1366 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 1383 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1393 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1407 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1418 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1441 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1493 SimplifyAndOfICmps(ICmpInst *Op0, ICmpInst *Op1) argument 1545 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1642 SimplifyAndInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1652 SimplifyOrOfICmps(ICmpInst *Op0, ICmpInst *Op1) argument 1704 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1830 SimplifyOrInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1840 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1887 SimplifyXorInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument [all...] |
H A D | ValueTracking.cpp | 191 static void computeKnownBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW, argument 197 if (ConstantInt *CLHS = dyn_cast<ConstantInt>(Op0)) { 225 computeKnownBits(Op0, LHSKnownZero, LHSKnownOne, DL, Depth + 1, Q); 271 static void computeKnownBitsMul(Value *Op0, Value *Op1, bool NSW, argument 278 computeKnownBits(Op0, KnownZero2, KnownOne2, DL, Depth + 1, Q); 284 if (Op0 == Op1) { 299 isKnownNonZero(Op0, DL, Depth, Q)) || 2149 Value *Op0 = I->getOperand(0); local 2155 // Turn Op0 << Op1 into Op0 * [all...] |
/external/llvm/lib/ExecutionEngine/ |
H A D | ExecutionEngine.cpp | 624 Constant *Op0 = CE->getOperand(0); local 628 GenericValue Result = getConstantValue(Op0); 637 GenericValue GV = getConstantValue(Op0); 643 GenericValue GV = getConstantValue(Op0); 649 GenericValue GV = getConstantValue(Op0); 656 GenericValue GV = getConstantValue(Op0); 662 GenericValue GV = getConstantValue(Op0); 667 GenericValue GV = getConstantValue(Op0); 682 GenericValue GV = getConstantValue(Op0); 698 GenericValue GV = getConstantValue(Op0); [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 66 const MCOperand &Op0 = MI->getOperand(0); local 99 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 135 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 145 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 153 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 160 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 local 170 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", " 180 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 5045 SDValue Op0, Op1; local 5050 if (SelectDirectAddr(Op, Op0)) { 5051 OutOps.push_back(Op0); 5055 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) { 5056 OutOps.push_back(Op0);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 285 // If Op0 is null, then Node is a constant that can be loaded using: 289 // If Op0 is nonnull, then Node can be implemented using: 291 // (Opcode (Opcode Op0 UpperVal) LowerVal) 292 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 398 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 401 SDValue Op0, uint64_t Op1) { 405 changeComponent(AM, IsBase, Op0); 424 SDValue Op0 = N.getOperand(0); local 427 unsigned Op0Code = Op0->getOpcode(); 433 return expandAdjDynAlloc(AM, IsBase, Op0); 400 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1) argument 941 SDValue Op0 = N->getOperand(I ^ 1); local 970 splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, uint64_t UpperVal, uint64_t LowerVal) argument 1102 SDValue Op0 = Node->getOperand(0); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 1150 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); local 1152 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 1160 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1165 moveToTop(Op0, I); // Move dead operand to TOS. 1166 TOS = Op0; 1176 duplicateToTop(Op0, Dest, I); 1177 Op0 = TOS = Dest; 1184 duplicateToTop(Op0, Dest, I); 1185 Op0 = TOS = Dest; 1191 assert((TOS == Op0 || TO 1248 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); local 1274 unsigned Op0 = getFPReg(MI->getOperand(0)); local [all...] |
H A D | X86MCInstLower.cpp | 317 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); local 322 if (Op0 == X86::AX && Op1 == X86::AL) 326 if (Op0 == X86::EAX && Op1 == X86::AX) 330 if (Op0 == X86::RAX && Op1 == X86::EAX)
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