Searched defs:PredReg (Results 1 - 13 of 13) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp66 ARMCC::CondCodes Pred, unsigned PredReg,
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
86 ARMCC::CondCodes Pred, unsigned PredReg,
106 unsigned PredReg, unsigned MIFlags) const {
113 PredReg, MIFlags);
116 PredReg, MIFlags);
62 emitThumb1LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) argument
82 emitThumb2LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) argument
103 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DThumb2ITBlockPass.cpp171 unsigned PredReg = 0; local
172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
H A DThumb2InstrInfo.cpp60 unsigned PredReg = 0; local
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
108 unsigned PredReg = 0; local
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
223 ARMCC::CondCodes Pred, unsigned PredReg,
228 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
245 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
252 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
261 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
267 .addImm((unsigned)Pred).addReg(PredReg)
220 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
[all...]
H A DMLxExpansionPass.cpp285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); local
298 MIB.addImm(Pred).addReg(PredReg);
310 MIB.addImm(Pred).addReg(PredReg);
H A DARMBaseRegisterInfo.cpp396 unsigned PredReg, unsigned MIFlags) const {
407 .addImm(0).addImm(Pred).addReg(PredReg)
747 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); local
755 Offset, Pred, PredReg, TII);
759 Offset, Pred, PredReg, TII);
391 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DThumb2SizeReduction.cpp581 unsigned PredReg = 0; local
582 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
685 unsigned PredReg = 0; local
686 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
782 unsigned PredReg = 0; local
783 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
H A DARMExpandPseudoInsts.cpp656 unsigned PredReg = 0; local
657 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
684 LO16.addImm(Pred).addReg(PredReg).addReg(0);
685 HI16.addImm(Pred).addReg(PredReg).addReg(0);
733 LO16.addImm(Pred).addReg(PredReg);
734 HI16.addImm(Pred).addReg(PredReg);
H A DARMConstantIslandPass.cpp1358 unsigned PredReg = 0; local
1359 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
1365 DEBUG(unsigned PredReg;
1366 assert(!isThumb || getITInstrPredicate(MI, PredReg) == ARMCC::AL));
1809 unsigned PredReg = 0; local
1810 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg);
1828 Pred = getInstrPredicate(CmpMI, PredReg);
H A DARMFrameLowering.cpp120 unsigned PredReg = 0) {
123 Pred, PredReg, TII, MIFlags);
126 Pred, PredReg, TII, MIFlags);
134 unsigned PredReg = 0) {
136 MIFlags, Pred, PredReg);
1791 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1792 unsigned PredReg = Old->getOperand(2).getReg(); local
1794 Pred, PredReg);
1796 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1797 unsigned PredReg local
[all...]
H A DARMLoadStoreOptimizer.cpp104 ARMCC::CondCodes Pred, unsigned PredReg);
107 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
121 unsigned PredReg,
127 ARMCC::CondCodes Pred, unsigned PredReg,
382 ARMCC::CondCodes Pred, unsigned PredReg) {
451 .addImm(Pred).addReg(PredReg);
470 .addImm(Pred).addReg(PredReg);
482 unsigned PredReg, unsigned Scratch, DebugLoc dl,
590 .addImm(Pred).addReg(PredReg);
600 .addImm(Pred).addReg(PredReg);
378 UpdateBaseRegUses(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc dl, unsigned Base, unsigned WordOffset, ARMCC::CondCodes Pred, unsigned PredReg) argument
478 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument
728 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument
831 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument
908 isMatchingDecrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument
943 isMatchingIncrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument
1111 unsigned PredReg = 0; local
1268 unsigned PredReg = 0; local
1449 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1506 unsigned PredReg = 0; local
1625 unsigned PredReg = 0; local
1959 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument
2121 unsigned BaseReg = 0, PredReg = 0; local
2218 unsigned PredReg = 0; local
[all...]
H A DARMISelDAGToDAG.cpp2488 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local
2489 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2755 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local
2756 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2775 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local
2776 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2794 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local
2795 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
H A DARMBaseInstrInfo.cpp1733 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { argument
1736 PredReg = 0;
1740 PredReg = MI->getOperand(PIdx+1).getReg();
1763 unsigned PredReg = 0; local
1764 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1766 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1948 ARMCC::CondCodes Pred, unsigned PredReg,
1953 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1975 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1945 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp495 unsigned PredReg = Cond[Cond.size()-1].getReg(); local
496 MachineInstr *CondI = MRI->getVRegDef(PredReg);

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