/external/llvm/test/MC/ELF/ |
H A D | pr9292.s | 7 mov %eax,bar label
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H A D | section-sym2.s | 5 mov .rodata, %rsi label
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/external/llvm/test/MC/MachO/ |
H A D | bad-darwin-x86_64-32-bit-abs-addr.s | 4 mov $_f, %rsi label
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H A D | bad-macro.s | 6 mov $1, %eax label 7 mov $2, %eax label
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/external/llvm/test/MC/X86/ |
H A D | x86-32-ms-inline-asm.s | 3 mov eax, [ebx].0 label 4 mov [ebx].4, ecx label 13 mov eax, [4*eax + 4] 16 mov eax, [4*eax][4] 20 mov eax, [esi + eax] 23 mov eax, [esi][eax] 27 mov eax, [esi + 4*eax] 30 mov eax, [esi][4*eax] 34 mov eax, [esi + eax + 4] 37 mov ea [all...] |
H A D | intel-syntax-unsized-memory.s | 8 mov [rax], al label 11 mov [rax], ax label 14 mov [rax], eax label 17 mov [rax], rax label
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H A D | intel-syntax-ambiguous.s | 19 mov [eax], 1 label 20 // CHECK: error: ambiguous operand size for instruction 'mov'
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H A D | intel-syntax.s | 9 mov DWORD PTR [RSP - 4], 257 11 mov DWORD PTR [RSP + 4], 258 13 mov QWORD PTR [RSP - 16], 123 15 mov BYTE PTR [RSP - 17], 97 17 mov EAX, DWORD PTR [RSP - 4] 19 mov RAX, QWORD PTR [RSP] 21 mov DWORD PTR [RSP - 4], -4 23 mov RCX, QWORD PTR [0] 25 mov EAX, DWORD PTR [RSP + 4*RAX - 24] 27 mov BYT 600 mov rbx, qword ptr [_g0] label 601 mov rcx, qword ptr [_g0 + 8] label [all...] |
H A D | x86-64.s | 396 mov %CS, %ax label 419 mov %rdx, %cr0 label 422 mov %rdx, %cr4 label 425 mov %rdx, %cr8 label 428 mov %rdx, %cr15 label 939 mov %dr6, %rax label 940 mov %db6, %rax label 988 mov (%rsi), %gs // CHECK: movl (%rsi), %gs # encoding: [0x8e,0x2e] label 989 mov %gs, (%rsi) // CHECK: movl %gs, (%rsi) # encoding: [0x8c,0x2e] label
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/external/llvm/test/MC/ARM/ |
H A D | directive-fpu-instrs.s | 12 mov r6, r5 label
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/external/boringssl/src/crypto/poly1305/ |
H A D | poly1305_arm_asm.S | 161 mov r12,sp label 166 # asm 1: mov >len=int32#4,<input_3=int32#4 167 # asm 2: mov >len=r3,<input_3=r3 168 mov r3,r3 label 1514 # asm 1: mov >len=int32#1,<len=int32#4 1515 # asm 2: mov >len=r0,<len=r3 1516 mov r0,r3 label 1519 mov sp,r12 label
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_dataflow_swizzles.c | 50 struct rc_instruction * mov = rc_insert_new_instruction(c, inst->Prev); local 54 mov->U.I.Opcode = RC_OPCODE_MOV; 55 mov->U.I.DstReg.File = RC_FILE_TEMPORARY; 56 mov->U.I.DstReg.Index = tempreg; 57 mov->U.I.DstReg.WriteMask = split.Phase[phase]; 58 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src]; 59 mov->U.I.PreSub = inst->U.I.PreSub; 64 SET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED); 66 phase_refmask |= 1 << GET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan); 71 masked_negate = split.Phase[phase] & mov [all...] |
/external/mesa3d/src/gallium/auxiliary/util/ |
H A D | u_atomic.h | 213 mov eax, [v] 225 mov eax, [v] 234 mov eax, [v] 245 mov ecx, [v] 246 mov eax, [old] 247 mov edx, [_new] 249 mov [orig], eax local
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H A D | u_math.h | 470 __asm mov [i], eax local
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/external/libvpx/libvpx/third_party/libyuv/source/ |
H A D | rotate_win.cc | 30 mov eax, [esp + 12 + 4] // src 31 mov edi, [esp + 12 + 8] // src_stride 32 mov edx, [esp + 12 + 12] // dst 33 mov esi, [esp + 12 + 16] // dst_stride 34 mov ecx, [esp + 12 + 20] // width 62 mov eax, ebp 124 mov eax, [esp + 16 + 4] // src 125 mov edi, [esp + 16 + 8] // src_stride 126 mov edx, [esp + 16 + 12] // dst_a 127 mov es 133 mov [esp + 16], ecx local [all...] |
H A D | scale_win.cc | 102 mov eax, [esp + 4] // src_ptr 104 mov edx, [esp + 12] // dst_ptr 105 mov ecx, [esp + 16] // dst_width 128 mov eax, [esp + 4] // src_ptr 130 mov edx, [esp + 12] // dst_ptr 131 mov ecx, [esp + 16] // dst_width 165 mov eax, [esp + 4 + 4] // src_ptr 166 mov esi, [esp + 4 + 8] // src_stride 167 mov edx, [esp + 4 + 12] // dst_ptr 168 mov ec 906 mov [edi], bx local 926 mov [edi], bl local [all...] |
/external/zlib/src/contrib/inflate86/ |
H A D | inffas86.c | 800 mov [eax], esp /* save esp, ebp */ local 801 mov [eax+4], ebp local 802 mov esp, eax 803 mov esi, [esp+8] /* esi = in */ 804 mov edi, [esp+16] /* edi = out */ 805 mov edx, [esp+40] /* edx = hold */ 806 mov ebx, [esp+44] /* ebx = bits */ 807 mov ebp, [esp+32] /* ebp = lcode */ 825 mov cl, bl /* cl = bits, needs it for shifting */ 831 mov ea 851 mov [esp+64], ecx /* save len */ local 948 mov [edi], al local 974 mov [edi], al /* memset out with from[-1] */ local 1115 mov [esp+16], edi /* save out */ local 1116 mov [esp+44], ebx /* save bits */ local 1117 mov [esp+40], edx /* save hold */ local [all...] |
/external/libyuv/files/source/ |
H A D | rotate.cc | 70 mov eax, [esp + 12 + 4] // src 71 mov edi, [esp + 12 + 8] // src_stride 72 mov edx, [esp + 12 + 12] // dst 73 mov esi, [esp + 12 + 16] // dst_stride 74 mov ecx, [esp + 12 + 20] // width 102 mov eax, ebp 165 mov eax, [esp + 16 + 4] // src 166 mov edi, [esp + 16 + 8] // src_stride 167 mov edx, [esp + 16 + 12] // dst_a 168 mov es 174 mov [esp + 16], ecx local [all...] |
H A D | row_win.cc | 128 mov eax, [esp + 4] // src_y 129 mov edx, [esp + 8] // dst_argb 130 mov ecx, [esp + 12] // pix 156 mov eax, [esp + 4] // src_bgra 157 mov edx, [esp + 8] // dst_argb 158 mov ecx, [esp + 12] // pix 177 mov eax, [esp + 4] // src_abgr 178 mov edx, [esp + 8] // dst_argb 179 mov ecx, [esp + 12] // pix 198 mov ea 3639 mov [eax], bl local 3640 mov [eax + 1], dl local 3643 mov [eax + 2], bl local 3644 mov [eax + 3], dl local [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_optimize.c | 36 [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1, .is_arith = 1 }, 228 /* SEND may perform an implicit mov to a mrf register */ 275 /* Look if SEND uses an implicit mov. In that case, we read one less register 378 brw_is_control_done(const struct brw_instruction *mov) { argument 380 mov->header.dependency_control != 0 || 381 mov->header.thread_control != 0 || 382 mov->header.mask_control != 0 || 383 mov->header.saturate != 0 || 384 mov->header.debug_control != 0; 388 brw_is_predicated(const struct brw_instruction *mov) { argument 393 brw_is_grf_to_mrf_mov(const struct brw_instruction *mov, int *mrf_index, int *grf_index, bool *is_compr4) argument 505 const struct brw_instruction *mov = p->store + i; local 554 const struct brw_instruction *mov = p->store + i; local [all...] |
/external/mesa3d/src/gallium/drivers/nouveau/ |
H A D | nouveau_video.c | 222 static unsigned pos(int pos, int mov, int max) { argument 223 int ret = pos + mov;
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/external/mesa3d/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir_lowering_nv50.cpp | 750 // mov coordinates from lane l to all lanes 765 Instruction *mov; local 767 mov = bld.mkMov(def[c][l], tex->getDef(c)); 768 mov->fixed = 1; 769 mov->lanes = 1 << l; 897 if (addr >= 0x400) // mov $sreg
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H A D | nv50_ir_peephole.cpp | 95 Instruction *mov, *si, *next; local 97 for (mov = bb->getEntry(); mov; mov = next) { 98 next = mov->next; 99 if (mov->op != OP_MOV || mov->fixed || !mov->getSrc(0)->asLValue()) 101 if (mov->getPredicate()) 103 if (mov [all...] |
/external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
H A D | nv50_ir_lowering_nvc0.cpp | 140 const Instruction *tex; // or split / mov 772 // mov coordinates from lane l to all lanes 787 Instruction *mov; local 789 mov = bld.mkMov(def[c][l], tex->getDef(c)); 790 mov->fixed = 1; 791 mov->lanes = 1 << l; 899 if (addr >= 0x400) // mov $sreg
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/external/mesa3d/src/mesa/program/ |
H A D | prog_optimize.c | 132 get_dst_mask_for_mov(const struct prog_instruction *mov, GLuint src_mask) argument 134 const GLuint mask = mov->DstReg.WriteMask; 138 ASSERT(mov->Opcode == OPCODE_MOV); 144 src_comp = GET_SWZ(mov->SrcReg[0].Swizzle, comp); 464 can_downward_mov_be_modifed(const struct prog_instruction *mov) argument 467 mov->Opcode == OPCODE_MOV && 468 mov->CondUpdate == GL_FALSE && 469 mov->SrcReg[0].RelAddr == 0 && 470 mov->SrcReg[0].Negate == 0 && 471 mov 480 can_upward_mov_be_modifed(const struct prog_instruction *mov) argument 515 const struct prog_instruction *mov = prog->Instructions + i; local 648 _mesa_merge_mov_into_inst(struct prog_instruction *inst, const struct prog_instruction *mov) argument 760 const struct prog_instruction *mov = prog->Instructions + i; local [all...] |