/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | r200_ioctl.c | 59 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 66 if (rmesa->radeon.sarea) 67 fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage);
|
H A D | radeon_common.h | 65 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) argument 68 rrb = radeon_renderbuffer(rmesa->state.depth.rb); 75 static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) argument 79 rrb = radeon_renderbuffer(rmesa->state.color.rb);
|
H A D | r200_maos_arrays.c | 78 r200ContextPtr rmesa = R200_CONTEXT( ctx ); local 117 if (!rmesa->radeon.tcl.aos[i].bo) { 120 &(rmesa->radeon.tcl.aos[nr]), 127 &(rmesa->radeon.tcl.aos[nr]), 176 if (!rmesa->radeon.tcl.aos[nr].bo) { 178 &(rmesa->radeon.tcl.aos[nr]), 190 if (vfmt0 != rmesa->hw.vtx.cmd[VTX_VTXFMT_0] || 191 vfmt1 != rmesa->hw.vtx.cmd[VTX_VTXFMT_1]) { 192 R200_STATECHANGE( rmesa, vtx ); 193 rmesa [all...] |
H A D | radeon_span.c | 121 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 radeon_firevertices(rmesa);
|
H A D | r200_ioctl.h | 48 extern void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count); 49 extern void r200EmitVertexAOS( r200ContextPtr rmesa, 54 extern void r200EmitVbufPrim( r200ContextPtr rmesa, 60 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, 64 extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); 68 void r200SetUpAtomList( r200ContextPtr rmesa ); 76 #define R200_NEWPRIM( rmesa ) \ 78 if ( rmesa->radeon.dma.flush ) \ 79 rmesa->radeon.dma.flush( rmesa 106 R200_DB_STATECHANGE( r200ContextPtr rmesa, struct radeon_state_atom *atom ) argument [all...] |
H A D | r200_cmdbuf.c | 55 void r200SetUpAtomList( r200ContextPtr rmesa ) 59 mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; 61 make_empty_list(&rmesa->radeon.hw.atomlist); 62 rmesa->radeon.hw.atomlist.name = "atom-list"; 64 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx ); 65 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.set ); 66 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa 116 r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, GLuint vertex_nr ) argument 137 r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) argument 162 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 184 r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, GLuint min_nr ) argument 210 r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count) argument 220 r200EmitVertexAOS( r200ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset ) argument 239 r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) argument [all...] |
H A D | r200_context.c | 74 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 77 GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 : 78 rmesa->radeon.radeonScreen->AGPMode; 88 !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE) 148 r200ContextPtr rmesa = (r200ContextPtr)radeon; local 151 R200_STATECHANGE( rmesa, ctx ); 152 if (rmesa->radeon.sarea->tiling_enabled) { 153 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; 155 else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE; 157 if ( sarea->ctx_owner != rmesa 163 r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) argument 210 r200ContextPtr rmesa; local 476 r200ContextPtr rmesa = (r200ContextPtr)driContextPriv->driverPrivate; local [all...] |
H A D | r200_fragshader.c | 126 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 131 R200_STATECHANGE( rmesa, afs[0] ); 132 R200_STATECHANGE( rmesa, afs[1] ); 135 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; 138 afs_cmd = (GLuint *) rmesa->hw.afs[0].cmd; 320 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; 322 rmesa->afs_loaded = ctx->ATIFragmentShader.Current; 326 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 330 R200_STATECHANGE( rmesa, ctx ); 331 R200_STATECHANGE( rmesa, cs 504 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 542 r200ContextPtr rmesa = R200_CONTEXT(ctx); local [all...] |
H A D | r200_tex.c | 301 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 318 if ( rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] != envColor ) { 319 R200_STATECHANGE( rmesa, tf ); 320 rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] = envColor; 336 min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? 342 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] & R200_LOD_BIAS_MASK) != b ) { 343 R200_STATECHANGE( rmesa, tex[unit] ); 344 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] &= ~R200_LOD_BIAS_MASK; 345 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] |= b; 351 R200_STATECHANGE( rmesa, sp 414 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 454 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 471 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 495 r200ContextPtr rmesa = R200_CONTEXT(ctx); local [all...] |
H A D | r200_state_init.c | 166 static int cmdpkt( r200ContextPtr rmesa, int id ) argument 224 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 225 (void) rmesa; \ 232 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 233 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 239 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 240 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 246 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 248 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 257 CHECK( texenv, (rmesa [all...] |
H A D | radeon_dma.c | 140 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 144 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); 148 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); 175 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 182 radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); 186 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); 204 void radeon_init_dma(radeonContextPtr rmesa) argument 206 make_empty_list(&rmesa->dma.free); 207 make_empty_list(&rmesa->dma.wait); 208 make_empty_list(&rmesa 212 radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) argument 265 radeonAllocDmaRegion(radeonContextPtr rmesa, struct radeon_bo **pbo, int *poffset, int bytes, int alignment) argument 295 radeonFreeDmaRegions(radeonContextPtr rmesa) argument 321 radeonReturnDmaRegion(radeonContextPtr rmesa, int return_bytes) argument 343 radeonReleaseDmaRegions(radeonContextPtr rmesa) argument 423 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 452 rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) argument [all...] |
H A D | r200_sanity.c | 1341 int r200SanityCmdBuffer( r200ContextPtr rmesa, argument 1356 cmdbuf.buf = rmesa->store.cmd_buf; 1357 cmdbuf.bufsz = rmesa->store.cmd_used;
|
H A D | r200_tcl.c | 105 #define LOCAL_VARS r200ContextPtr rmesa = R200_CONTEXT(ctx) 124 R200_STATECHANGE( rmesa, lin ); \ 125 radeonEmitState(&rmesa->radeon); \ 129 R200_STATECHANGE( rmesa, lin ); \ 131 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \ 134 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \ 136 radeonEmitState(&rmesa->radeon); \ 140 #define ALLOC_ELTS(nr) r200AllocElts( rmesa, nr ) 142 static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) argument 144 if (rmesa 184 r200ContextPtr rmesa = R200_CONTEXT( ctx ); local 262 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 293 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 359 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 515 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 539 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 609 r200ContextPtr rmesa = R200_CONTEXT(ctx); local [all...] |
H A D | r200_vertprog.c | 105 r200ContextPtr rmesa = R200_CONTEXT( ctx ); local 106 GLfloat *fcmd = (GLfloat *)&rmesa->hw.vpp[0].cmd[VPP_CMD_0 + 1]; 112 R200_STATECHANGE( rmesa, vpp[0] ); 113 R200_STATECHANGE( rmesa, vpp[1] ); 139 fcmd = (GLfloat *)&rmesa->hw.vpp[1].cmd[VPP_CMD_0 + 1]; 143 rmesa->hw.vpp[0].cmd_size = 145 tmp.i = rmesa->hw.vpp[0].cmd[VPP_CMD_0]; 147 rmesa->hw.vpp[0].cmd[VPP_CMD_0] = tmp.i; 149 rmesa->hw.vpp[1].cmd_size = 1 + 4 * (paramList->NumParameters - 96); 150 tmp.i = rmesa 1118 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 1199 r200ContextPtr rmesa = R200_CONTEXT(ctx); local 1240 r200ContextPtr rmesa = R200_CONTEXT(ctx); local [all...] |
H A D | radeon_common.c | 109 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 134 rmesa->state.scissor.rect.x1 = CLAMP(x1, min_x, max_x); 135 rmesa->state.scissor.rect.y1 = CLAMP(y1, min_y, max_y); 136 rmesa->state.scissor.rect.x2 = CLAMP(x2, min_x, max_x); 137 rmesa->state.scissor.rect.y2 = CLAMP(y2, min_y, max_y); 139 if (rmesa->vtbl.update_scissor) 140 rmesa->vtbl.update_scissor(ctx); 385 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); local 386 const GLboolean was_front_buffer_reading = rmesa->is_front_buffer_reading; 387 rmesa 655 rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller) argument 685 rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller) argument 709 rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller) argument 721 rcommonInitCmdBuf(radeonContextPtr rmesa) argument 769 rcommonDestroyCmdBuf(radeonContextPtr rmesa) argument 775 rcommonBeginBatch(radeonContextPtr rmesa, int n, int dostate, const char *file, const char *function, int line) argument [all...] |
/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_common.h | 65 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) argument 68 rrb = radeon_renderbuffer(rmesa->state.depth.rb); 75 static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) argument 79 rrb = radeon_renderbuffer(rmesa->state.color.rb);
|
H A D | radeon_span.c | 121 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 124 radeon_firevertices(rmesa);
|
H A D | radeon_ioctl.h | 43 extern void radeonEmitVertexAOS( r100ContextPtr rmesa, 48 extern void radeonEmitVbufPrim( r100ContextPtr rmesa, 56 extern GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, 62 extern void radeonEmitAOS( r100ContextPtr rmesa, 66 extern void radeonEmitBlit( r100ContextPtr rmesa, 76 extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags ); 78 extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * ); 83 extern void radeonGetAllParams( r100ContextPtr rmesa ); 84 extern void radeonSetUpAtomList( r100ContextPtr rmesa ); 92 #define RADEON_NEWPRIM( rmesa ) \ 113 RADEON_DB_STATECHANGE(r100ContextPtr rmesa, struct radeon_state_atom *atom ) argument [all...] |
H A D | radeon_maos_arrays.c | 86 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 101 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * 4, 32); 106 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * count * 4, 32); 146 r100ContextPtr rmesa = R100_CONTEXT( ctx ); local 159 if (!rmesa->tcl.obj.buf) 161 &(rmesa->tcl.aos[nr]), 179 if (!rmesa->tcl.norm.buf) 181 &(rmesa->tcl.aos[nr]), 205 if (!rmesa->tcl.rgba.buf) 207 &(rmesa [all...] |
H A D | radeon_context.c | 96 r100ContextPtr rmesa = (r100ContextPtr)radeon; local 99 RADEON_STATECHANGE(rmesa, ctx); 100 if (rmesa->radeon.sarea->tiling_enabled) { 101 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= 104 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= 108 if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) { 109 sarea->ctx_owner = rmesa->radeon.dri.hwContext; 113 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) argument 119 r100ContextPtr rmesa = (r100ContextPtr)radeon; local 122 rmesa 128 r100ContextPtr rmesa = R100_CONTEXT(ctx); local 176 r100ContextPtr rmesa; local [all...] |
H A D | radeon_ioctl.c | 65 void radeonSetUpAtomList( r100ContextPtr rmesa ) 67 int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; 69 make_empty_list(&rmesa->radeon.hw.atomlist); 70 rmesa->radeon.hw.atomlist.name = "atom-list"; 72 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx); 73 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set); 74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa 99 radeonEmitScissor(r100ContextPtr rmesa) argument 124 radeonEmitVbufPrim( r100ContextPtr rmesa, GLuint vertex_format, GLuint primitive, GLuint vertex_nr ) argument 171 r100ContextPtr rmesa = R100_CONTEXT(ctx); local 216 radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint vertex_format, GLuint primitive, GLuint min_nr ) argument 276 radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset ) argument 302 radeonEmitAOS( r100ContextPtr rmesa, GLuint nr, GLuint offset ) argument 383 r100ContextPtr rmesa = R100_CONTEXT(ctx); local [all...] |
H A D | radeon_maos_verts.c | 312 r100ContextPtr rmesa = R100_CONTEXT(ctx); local 316 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & 359 if (((rmesa->NeedTexMatrix >> unit) & 1) && 360 (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) 361 radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; 366 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) { 367 RADEON_STATECHANGE( rmesa, tcl ); 368 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx; 375 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && 376 rmesa [all...] |
H A D | radeon_tex.c | 261 r100ContextPtr rmesa = R100_CONTEXT(ctx); local 276 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) { 277 RADEON_STATECHANGE( rmesa, tex[unit] ); 278 rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor; 292 min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? 302 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) { 303 RADEON_STATECHANGE( rmesa, tex[unit] ); 304 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK; 305 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK); 357 r100ContextPtr rmesa local 397 r100ContextPtr rmesa = R100_CONTEXT(ctx); local 411 r100ContextPtr rmesa = R100_CONTEXT(ctx); local 434 r100ContextPtr rmesa = R100_CONTEXT(ctx); local [all...] |
H A D | radeon_dma.c | 140 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 144 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); 148 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); 175 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 182 radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); 186 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); 204 void radeon_init_dma(radeonContextPtr rmesa) argument 206 make_empty_list(&rmesa->dma.free); 207 make_empty_list(&rmesa->dma.wait); 208 make_empty_list(&rmesa 212 radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) argument 265 radeonAllocDmaRegion(radeonContextPtr rmesa, struct radeon_bo **pbo, int *poffset, int bytes, int alignment) argument 295 radeonFreeDmaRegions(radeonContextPtr rmesa) argument 321 radeonReturnDmaRegion(radeonContextPtr rmesa, int return_bytes) argument 343 radeonReleaseDmaRegions(radeonContextPtr rmesa) argument 423 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); local 452 rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) argument [all...] |
H A D | radeon_state_init.c | 161 static int cmdpkt( r100ContextPtr rmesa, int id ) argument 197 r100ContextPtr rmesa = R100_CONTEXT(ctx); \ 198 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 504 void radeonInitState( r100ContextPtr rmesa ) 506 struct gl_context *ctx = rmesa->radeon.glCtx; 509 rmesa->radeon.Fallback = 0; 512 rmesa->radeon.hw.max_state_size = 0; 516 rmesa->hw.ATOM.cmd_size = SZ; \ 517 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 518 rmesa [all...] |