/external/mesa3d/src/gallium/drivers/i915/ |
H A D | i915_screen.h | 50 boolean tiling; member in struct:i915_screen::__anon12056
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H A D | i915_resource.h | 69 /* tiling flags */ 70 enum i915_winsys_buffer_tile tiling; member in struct:i915_texture
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H A D | i915_state_sampler.c | 278 ms3_tiling_bits(enum i915_winsys_buffer_tile tiling) argument 282 switch (tiling) { 325 | ms3_tiling_bits(tex->tiling));
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H A D | i915_state_static.c | 79 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling) argument 83 switch (tiling) { 110 buf_3d_tiling_bits(tex->tiling); 135 buf_3d_tiling_bits(tex->tiling); 219 if (is->is_i945 && tex->tiling != I915_TILE_NONE
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H A D | i915_resource_texture.c | 178 if (!is->debug.tiling) 216 tex->tiling = I915_TILE_X; 254 tex->tiling = I915_TILE_X; 959 tex->tiling = I915_TILE_NONE; 961 tex->tiling = i915_texture_tiling(is, tex); 982 &tex->tiling, buf_usage); 986 I915_DBG(DBG_TEXTURE, "%s: %p stride %u, blocks (%u, %u) tiling %s\n", __func__, 989 tex->total_nblocksy, get_tiling_string(tex->tiling)); 1008 enum i915_winsys_buffer_tile tiling; local 1012 buffer = iws->buffer_from_handle(iws, whandle, &tiling, [all...] |
/external/mesa3d/src/gallium/winsys/i915/sw/ |
H A D | i915_sw_winsys.h | 46 enum i915_winsys_buffer_tile tiling; member in struct:i915_sw_buffer
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H A D | i915_sw_buffer.c | 33 enum i915_winsys_buffer_tile *tiling, 44 buf->tiling = *tiling; 31 i915_sw_buffer_create_tiled(struct i915_winsys *iws, unsigned *stride, unsigned height, enum i915_winsys_buffer_tile *tiling, enum i915_winsys_buffer_type type) argument
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/external/libdrm/tegra/ |
H A D | tegra.c | 355 struct drm_tegra_bo_tiling *tiling) 372 if (tiling) { 373 tiling->mode = args.mode; 374 tiling->value = args.value; 382 const struct drm_tegra_bo_tiling *tiling) 393 args.mode = tiling->mode; 394 args.value = tiling->value; 354 drm_tegra_bo_get_tiling(struct drm_tegra_bo *bo, struct drm_tegra_bo_tiling *tiling) argument 381 drm_tegra_bo_set_tiling(struct drm_tegra_bo *bo, const struct drm_tegra_bo_tiling *tiling) argument
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/external/mesa3d/src/gallium/winsys/i915/drm/ |
H A D | i915_drm_buffer.c | 58 enum i915_winsys_buffer_tile *tiling, 64 uint32_t tiling_mode = *tiling; 82 *tiling = tiling_mode; 94 enum i915_winsys_buffer_tile *tiling, 115 *tiling = tile; 56 i915_drm_buffer_create_tiled(struct i915_winsys *iws, unsigned *stride, unsigned height, enum i915_winsys_buffer_tile *tiling, enum i915_winsys_buffer_type type) argument 92 i915_drm_buffer_from_handle(struct i915_winsys *iws, struct winsys_handle *whandle, enum i915_winsys_buffer_tile *tiling, unsigned *stride) argument
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/external/mesa3d/src/mesa/drivers/dri/intel/ |
H A D | intel_regions.h | 70 uint32_t tiling; /**< Which tiling mode the region is in */ member in struct:intel_region 81 uint32_t tiling,
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H A D | intel_regions.c | 136 if (region->tiling != I915_TILING_NONE) 156 if (region->tiling != I915_TILING_NONE) 171 uint32_t tiling, drm_intel_bo *buffer) 185 region->tiling = tiling; 194 uint32_t tiling, 208 &tiling, &aligned_pitch, flags); 213 aligned_pitch / cpp, tiling, buffer); 247 uint32_t bit_6_swizzle, tiling; local 266 ret = drm_intel_bo_get_tiling(buffer, &tiling, 168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument 193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument 411 uint32_t tiling = region->tiling; local 444 uint32_t tiling = region->tiling; local [all...] |
/external/mesa3d/src/mesa/drivers/dri/i915/ |
H A D | intel_regions.c | 136 if (region->tiling != I915_TILING_NONE) 156 if (region->tiling != I915_TILING_NONE) 171 uint32_t tiling, drm_intel_bo *buffer) 185 region->tiling = tiling; 194 uint32_t tiling, 208 &tiling, &aligned_pitch, flags); 213 aligned_pitch / cpp, tiling, buffer); 247 uint32_t bit_6_swizzle, tiling; local 266 ret = drm_intel_bo_get_tiling(buffer, &tiling, 168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument 193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument 411 uint32_t tiling = region->tiling; local 444 uint32_t tiling = region->tiling; local [all...] |
H A D | intel_mipmap_tree.c | 200 uint32_t tiling = I915_TILING_NONE; local 216 tiling = I915_TILING_Y; 224 * Our usual reason for preferring X tiling (fast blits using the 228 * So use Y tiling, since it makes better use of the cache. 230 tiling = I915_TILING_Y; 232 tiling = I915_TILING_X; 255 tiling = I915_TILING_NONE; 262 tiling, 707 0, src_mt->region->tiling, 709 0, dst_mt->region->tiling, [all...] |
H A D | intel_screen.c | 58 DRI_CONF_DESC(en, "Enable texture tiling") 386 uint32_t tiling; local 389 tiling = I915_TILING_X; 393 tiling = I915_TILING_NONE; 399 intel_region_alloc(intelScreen, tiling, cpp, width, height, true); 564 image->region->tiling = parent->region->tiling; 893 uint32_t tiling = I915_TILING_X; local 898 &tiling, &aligned_pitch, flags); 902 drm_intel_bo_get_tiling(buffer, &tiling, [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | gen7_wm_surface_state.c | 65 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling) argument 67 switch (tiling) { 113 assert(mcs_mt->region->tiling == I915_TILING_Y); 342 gen7_set_surface_tiling(surf, intelObj->mt->region->tiling); 429 gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */ 566 gen7_set_surface_tiling(surf, region->tiling);
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H A D | intel_regions.c | 136 if (region->tiling != I915_TILING_NONE) 156 if (region->tiling != I915_TILING_NONE) 171 uint32_t tiling, drm_intel_bo *buffer) 185 region->tiling = tiling; 194 uint32_t tiling, 208 &tiling, &aligned_pitch, flags); 213 aligned_pitch / cpp, tiling, buffer); 247 uint32_t bit_6_swizzle, tiling; local 266 ret = drm_intel_bo_get_tiling(buffer, &tiling, 168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument 193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument 411 uint32_t tiling = region->tiling; local 444 uint32_t tiling = region->tiling; local [all...] |
H A D | gen7_blorp.cpp | 185 uint32_t tiling = surface->map_stencil_as_y_tiled local 186 ? I915_TILING_Y : region->tiling; 187 gen7_set_surface_tiling(surf, tiling);
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H A D | gen6_blorp.cpp | 446 uint32_t tiling = surface->map_stencil_as_y_tiled local 448 : brw_get_surface_tiling_bits(region->tiling); 452 surf[3] = (tiling |
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H A D | brw_wm_surface_state.c | 633 brw_get_surface_tiling_bits(uint32_t tiling) argument 635 switch (tiling) { 806 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) | 1201 surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
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H A D | intel_mipmap_tree.c | 200 uint32_t tiling = I915_TILING_NONE; local 216 tiling = I915_TILING_Y; 224 * Our usual reason for preferring X tiling (fast blits using the 228 * So use Y tiling, since it makes better use of the cache. 230 tiling = I915_TILING_Y; 232 tiling = I915_TILING_X; 255 tiling = I915_TILING_NONE; 262 tiling, 707 0, src_mt->region->tiling, 709 0, dst_mt->region->tiling, [all...] |
H A D | intel_screen.c | 58 DRI_CONF_DESC(en, "Enable texture tiling") 386 uint32_t tiling; local 389 tiling = I915_TILING_X; 393 tiling = I915_TILING_NONE; 399 intel_region_alloc(intelScreen, tiling, cpp, width, height, true); 564 image->region->tiling = parent->region->tiling; 893 uint32_t tiling = I915_TILING_X; local 898 &tiling, &aligned_pitch, flags); 902 drm_intel_bo_get_tiling(buffer, &tiling, [all...] |
/external/drm_gralloc/ |
H A D | gralloc_drm_intel.c | 71 uint32_t tiling; member in struct:intel_buffer 243 uint32_t *tiling, unsigned long *stride) 275 *tiling = I915_TILING_X; 278 *tiling = I915_TILING_NONE; 287 bpp, tiling, stride, flags); 294 if (*tiling != I915_TILING_NONE) { 296 *tiling = I915_TILING_NONE; 309 *tiling = I915_TILING_NONE; 313 *tiling = I915_TILING_X; 315 *tiling 241 alloc_ibo(struct intel_info *info, const struct gralloc_drm_handle_t *handle, uint32_t *tiling, unsigned long *stride) argument [all...] |
H A D | gralloc_drm_radeon.c | 81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) argument 86 if (tiling & RADEON_TILING_MACRO) { 92 } else if (tiling & RADEON_TILING_MICRO) { 112 if (tiling) 122 static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling) argument 127 if (tiling & RADEON_TILING_MACRO) 129 else if (tiling & RADEON_TILING_MICRO) 135 if (tiling) 146 int bpe, uint32_t tiling) 148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling); 145 radeon_get_base_align(struct radeon_info *info, int bpe, uint32_t tiling) argument 191 uint32_t tiling, domain; local [all...] |
/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | radeon_mipmap_tree.c | 78 unsigned tiling) 86 } else if (tiling) { 99 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target) argument 108 } else if (tiling) { 73 get_texture_image_size( gl_format format, unsigned rowStride, unsigned height, unsigned depth, unsigned tiling) argument
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_mipmap_tree.c | 78 unsigned tiling) 86 } else if (tiling) { 99 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target) argument 108 } else if (tiling) { 73 get_texture_image_size( gl_format format, unsigned rowStride, unsigned height, unsigned depth, unsigned tiling) argument
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