Searched refs:MI (Results 151 - 175 of 523) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp147 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
149 const MachineOperand &MO = MI->getOperand(OpNum);
159 const MachineFunction &MF = *MI->getParent()->getParent();
222 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
232 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
234 if (MI->getOperand(OpNum).isReg()) {
236 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
242 if (!MI->getOperand(OpNum).isImm())
244 O << MI->getOperand(OpNum).getImm();
248 printOperand(MI, OpNu
397 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
930 EmitJumpTable(const MachineInstr *MI) argument
981 EmitJump2Table(const MachineInstr *MI) argument
1042 EmitUnwindingInstruction(const MachineInstr *MI) argument
1186 EmitInstruction(const MachineInstr *MI) argument
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H A DThumb1FrameLowering.h34 MachineBasicBlock::iterator MI,
38 MachineBasicBlock::iterator MI,
47 MachineBasicBlock::iterator MI) const override;
H A DARMConstantIslandPass.cpp185 MachineInstr *MI; member in struct:__anon10665::ARMConstantIslands::CPUser
196 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm),
200 /// getMaxDisp - Returns the maximum displacement supported by MI.
235 MachineInstr *MI; member in struct:__anon10665::ARMConstantIslands::ImmBranch
240 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
283 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
295 bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
300 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
305 bool mayOptimizeThumb2Instruction(const MachineInstr *MI) const;
314 unsigned getOffsetOf(MachineInstr *MI) cons
875 splitBlockBeforeInstr(MachineInstr *MI) argument
1035 isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, MachineInstr *CPEMI, unsigned MaxDisp, bool NegOk, bool DoDump) argument
1325 MachineBasicBlock::iterator MI = UserMI; local
1518 isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB, unsigned MaxDisp) argument
1544 MachineInstr *MI = Br.MI; local
1562 MachineInstr *MI = Br.MI; local
1585 MachineInstr *MI = Br.MI; local
1672 MachineInstr *MI = PushPopMIs[i]; local
1865 MachineInstr *MI = T2JumpTables[i]; local
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H A DThumbRegisterInfo.cpp332 static void removeOperands(MachineInstr &MI, unsigned i) {
334 for (unsigned e = MI.getNumOperands(); i != e; ++i)
335 MI.RemoveOperand(Op);
356 MachineInstr &MI = *II;
357 MachineBasicBlock &MBB = *MI.getParent();
360 DebugLoc dl = MI.getDebugLoc();
361 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
362 unsigned Opcode = MI.getOpcode();
363 const MCInstrDesc &Desc = MI.getDesc();
367 Offset += MI
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/external/llvm/lib/Target/R600/
H A DR600InstrInfo.cpp38 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
39 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
42 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
43 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
48 MachineBasicBlock::iterator MI, DebugLoc DL,
67 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
74 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
161 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
162 if (isALUInstr(MI->getOpcode()))
164 if (isVector(*MI) || isCubeO
47 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
353 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const argument
627 MachineInstr *MI = MIs[i]; local
674 MachineInstr *MI = I; local
996 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument
1010 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument
1048 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument
1260 buildSlotOfVectorInstruction( MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const argument
1324 getOperandIdx(const MachineInstr &MI, unsigned Op) const argument
1332 setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const argument
1348 getFlagOp(MachineInstr *MI, unsigned SrcIdx, unsigned Flag) const argument
1403 addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const argument
1424 clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const argument
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H A DAMDGPUMCInstLower.cpp43 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument
45 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
48 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
50 "a target-specific version: " + Twine(MI->getOpcode()));
55 for (const MachineOperand &MO : MI->explicit_operands()) {
94 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument
100 if (!STI.getInstrInfo()->verifyInstruction(MI, Err)) {
102 MI->dump();
105 if (MI->isBundle()) {
106 const MachineBasicBlock *MBB = MI
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H A DSIFoldOperands.cpp59 FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp) : argument
60 UseMI(MI), UseOpNo(OpNo) {
108 MachineInstr *MI = Fold.UseMI; local
109 MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
130 MachineInstr *MI, unsigned OpNo,
133 if (!TII->isOperandLegal(MI, OpNo, OpToFold)) {
138 bool CanCommute = TII->findCommutedOpIndices(MI, CommuteIdx0, CommuteIdx1);
147 if (!CanCommute || !TII->commuteInstruction(MI))
150 if (!TII->isOperandLegal(MI, OpNo, OpToFold))
154 FoldList.push_back(FoldCandidate(MI, OpN
129 tryAddToFoldList(std::vector<FoldCandidate> &FoldList, MachineInstr *MI, unsigned OpNo, MachineOperand *OpToFold, const SIInstrInfo *TII) argument
171 MachineInstr &MI = *I; local
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H A DSIInstrInfo.cpp300 MachineBasicBlock::iterator MI, DebugLoc DL,
338 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
345 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
350 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
359 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
381 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
419 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
429 unsigned SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
430 const unsigned Opcode = MI.getOpcode();
462 MachineBasicBlock::iterator MI,
299 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
461 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
515 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
563 calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, RegScavenger *RS, unsigned TmpReg, unsigned FrameOffset, unsigned Size) const argument
657 insertNOPs(MachineBasicBlock::iterator MI, int Count) const argument
754 commuteInstruction(MachineInstr *MI, bool NewMI) const argument
830 findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const argument
889 removeModOperands(MachineInstr &MI) argument
1015 isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const argument
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/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp88 static bool tryOrrMovk(uint64_t UImm, uint64_t OrrImm, MachineInstr &MI, argument
99 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
100 .addOperand(MI.getOperand(0))
106 const unsigned DstReg = MI.getOperand(0).getReg();
107 const bool DstIsDead = MI.getOperand(0).isDead();
109 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
115 transferImpOps(MI, MIB, MIB1);
116 MI.eraseFromParent();
139 static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
166 BuildMI(MBB, MBBI, MI
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/external/mesa3d/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp66 MachineInstr * MI, MachineBasicBlock * BB) const
70 MachineBasicBlock::iterator I = MI;
72 if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) {
73 AppendS_WAITCNT(MI, *BB, llvm::next(I));
77 switch (MI->getOpcode()) {
79 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI
65 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument
142 AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I) const argument
149 LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
181 LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const argument
203 LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
235 LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const argument
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H A DR600ISelLowering.cpp54 MachineInstr * MI, MachineBasicBlock * BB) const
58 MachineBasicBlock::iterator I = *MI;
60 switch (MI->getOpcode()) {
61 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
66 .addOperand(MI->getOperand(0))
67 .addOperand(MI->getOperand(1))
77 .addOperand(MI->getOperand(0))
78 .addOperand(MI->getOperand(1))
89 .addOperand(MI->getOperand(0))
90 .addOperand(MI
53 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.h37 void EncodeInstruction(MCInst const &MI, raw_ostream &OS,
43 uint64_t getBinaryCodeForInstr(MCInst const &MI,
48 unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
/external/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.h33 void EmitInstruction(const MachineInstr *MI) override;
35 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
38 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
H A DSystemZInstrBuilder.h28 MachineInstr *MI = MIB; local
29 MachineFunction &MF = *MI->getParent()->getParent();
31 const MCInstrDesc &MCID = MI->getDesc();
H A DSystemZInstrInfo.h121 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
122 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
123 void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
125 void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
127 void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
129 void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
140 unsigned isLoadFromStackSlot(const MachineInstr *MI,
142 unsigned isStoreToStackSlot(const MachineInstr *MI,
144 bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
155 bool analyzeCompare(const MachineInstr *MI, unsigne
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/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.h35 unsigned isLoadFromStackSlot(const MachineInstr *MI,
43 unsigned isStoreToStackSlot(const MachineInstr *MI,
47 MachineBasicBlock::iterator MI, DebugLoc DL,
52 MachineBasicBlock::iterator MI,
59 MachineBasicBlock::iterator MI,
65 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
/external/llvm/lib/Target/X86/
H A DX86AsmPrinter.h83 void LowerSTACKMAP(const MachineInstr &MI);
84 void LowerPATCHPOINT(const MachineInstr &MI);
86 void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
103 void EmitInstruction(const MachineInstr *MI) override;
109 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
112 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
H A DX86FloatingPoint.cpp271 static bool isFPCopy(MachineInstr *MI) { argument
272 unsigned DstReg = MI->getOperand(0).getReg();
273 unsigned SrcReg = MI->getOperand(1).getReg();
372 MachineInstr *MI = I; local
373 uint64_t Flags = MI->getDesc().TSFlags;
376 if (MI->isInlineAsm())
379 if (MI->isCopy() && isFPCopy(MI))
382 if (MI->isImplicitDef() &&
383 X86::RFP80RegClass.contains(MI
792 MachineInstr* MI = I; local
959 MachineInstr *MI = I; local
973 MachineInstr *MI = I; local
1034 MachineInstr *MI = I; local
1145 MachineInstr *MI = I; local
1244 MachineInstr *MI = I; local
1272 MachineInstr *MI = I; local
1301 MachineInstr *MI = Inst; local
1662 MachineInstr &MI = *I; local
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/external/llvm/lib/Target/BPF/
H A DBPFFrameLowering.h36 MachineBasicBlock::iterator MI) const override {
37 MBB.erase(MI);
/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp70 void NVPTXInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument
72 printInstruction(MI, OS);
78 void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument
80 const MCOperand &Op = MI->getOperand(OpNo);
92 void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O, argument
94 const MCOperand &MO = MI->getOperand(OpNum);
142 void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O, argument
144 const MCOperand &MO = MI->getOperand(OpNum);
215 void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum, argument
218 const MCOperand &MO = MI
263 printMemOperand(const MCInst *MI, int OpNum, raw_ostream &O, const char *Modifier) argument
279 printProtoIdent(const MCInst *MI, int OpNum, raw_ostream &O, const char *Modifier) argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp69 HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI, argument
72 MI->getParent()->getParent()->getSubtarget().getInstrInfo();
74 switch(MI->getOpcode()) {
95 MI->setDesc(TII->get(NewOpcode));
96 MI->getOperand(1).setMBB(NewTarget);
109 MachineInstr *MI = MII; local
110 int Opc = MI->getOpcode();
162 if ((MI->getOpcode() == Hexagon::J2_jumpt) ||
163 (MI->getOpcode() == Hexagon::J2_jumpf)) {
164 CondBranchTarget = MI
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXReplaceImageHandles.cpp43 bool processInstr(MachineInstr &MI);
63 MachineInstr &MI = *I; local
64 Changed |= processInstr(MI);
79 bool NVPTXReplaceImageHandles::processInstr(MachineInstr &MI) { argument
80 MachineFunction &MF = *MI.getParent()->getParent();
81 const MCInstrDesc &MCID = MI.getDesc();
86 MachineOperand &TexHandle = MI.getOperand(4);
90 MachineOperand &SampHandle = MI.getOperand(5);
100 MachineOperand &SurfHandle = MI.getOperand(VecSize);
107 MachineOperand &SurfHandle = MI
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/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp76 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI, argument
79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
80 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
84 SC = resolveSchedClass(MI);
88 return MI->isTransient() ? 0 : 1;
102 resolveSchedClass(const MachineInstr *MI) const {
105 unsigned SchedClass = MI->getDesc().getSchedClass();
116 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
127 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) { argument
130 const MachineOperand &MO = MI
143 findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) argument
250 computeInstrLatency(const MachineInstr *MI, bool UseDefaultDefLatency) const argument
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H A DLiveRangeEdit.cpp147 MachineBasicBlock::iterator MI,
153 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
155 return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
170 MachineInstr *MI = MO.getParent(); local
172 if (DefMI && DefMI != MI)
174 if (!MI->canFoldAsLoad())
176 DefMI = MI;
178 if (UseMI && UseMI != MI)
183 UseMI = MI;
222 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSe argument
146 rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &tri, bool Late) argument
232 DEBUG(dbgs() << "Won't delete: " << Idx << '\\t' << *MI); local
239 DEBUG(dbgs() << "Can't delete: " << Idx << '\\t' << *MI); local
243 DEBUG(dbgs() << "Deleting dead def " << Idx << '\\t' << *MI); local
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/external/llvm/lib/Target/R600/MCTargetDesc/
H A DSIMCCodeEmitter.cpp55 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
60 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
66 unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
182 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, argument
186 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
187 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
198 for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
208 const MCOperand &Op = MI.getOperand(i);
229 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, argument
232 const MCOperand &MO = MI
244 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
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