/external/llvm/lib/Target/ARM/ |
H A D | ARMInstrInfo.cpp | 92 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI, argument 94 MachineFunction &MF = *MI->getParent()->getParent(); 99 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12, RM); 101 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12, RM); 106 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12, RM); 111 cast<GlobalValue>((*MI->memoperands_begin())->getValue()); 114 expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12, RM); 118 MachineBasicBlock &MBB = *MI->getParent(); 119 DebugLoc DL = MI->getDebugLoc(); 120 unsigned Reg = MI [all...] |
H A D | ARMInstrInfo.h | 42 void expandLoadStackGuard(MachineBasicBlock::iterator MI,
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/external/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 77 /// \brief Test if MI jumps to a function via a register. 82 bool isCallViaRegister(MachineInstr &MI, unsigned &Reg, 103 /// Return the first MachineOperand of MI if it is a used virtual register. 104 static MachineOperand *getCallTargetRegOpnd(MachineInstr &MI) { argument 105 if (MI.getNumOperands() == 0) 108 MachineOperand &MO = MI.getOperand(0); 141 /// Search MI's operands for register GP and erase it. 142 static void eraseGPOpnd(MachineInstr &MI) { argument 146 MachineFunction &MF = *MI.getParent()->getParent(); 147 MVT::SimpleValueType Ty = getRegTy(MI 246 isCallViaRegister(MachineInstr &MI, unsigned &Reg, ValueType &Val) const argument [all...] |
H A D | MipsConstantIslandPass.cpp | 81 static unsigned int branchTargetOperand(MachineInstr *MI) { argument 82 switch (MI->getOpcode()) { 267 MachineInstr *MI; member in struct:__anon10769::MipsConstantIslands::CPUser 280 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), 285 /// getMaxDisp - Returns the maximum displacement supported by MI. 329 MachineInstr *MI; member in struct:__anon10769::MipsConstantIslands::ImmBranch 334 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {} 382 unsigned getOffsetOf(MachineInstr *MI) const; 392 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI); 405 bool isCPEntryInRange(MachineInstr *MI, unsigne 875 splitBlockBeforeInstr(MachineInstr *MI) argument 1004 isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, MachineInstr *CPEMI, unsigned MaxDisp, bool NegOk, bool DoDump) argument 1310 MachineBasicBlock::iterator MI = UserMI; local 1495 isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB, unsigned MaxDisp) argument 1523 MachineInstr *MI = Br.MI; local 1542 MachineInstr *MI = Br.MI; local 1583 MachineInstr *MI = Br.MI; local [all...] |
H A D | Mips16FrameLowering.h | 30 MachineBasicBlock::iterator MI, 35 MachineBasicBlock::iterator MI,
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H A D | MipsDelaySlotFiller.cpp | 73 void init(const MachineInstr &MI); 76 void setCallerSaved(const MachineInstr &MI); 86 bool update(const MachineInstr &MI, unsigned Begin, unsigned End); 106 /// Return true if MI cannot be moved to delay slot. 107 bool hasHazard(const MachineInstr &MI); 120 virtual bool hasHazard_(const MachineInstr &MI) = 0; 128 bool hasHazard_(const MachineInstr &MI) override { return true; } 136 bool hasHazard_(const MachineInstr &MI) override; 148 bool hasHazard_(const MachineInstr &MI) override; 155 /// Get the list of underlying objects of MI' 256 hasUnoccupiedSlot(const MachineInstr *MI) argument 298 init(const MachineInstr &MI) argument 315 setCallerSaved(const MachineInstr &MI) argument 355 update(const MachineInstr &MI, unsigned Begin, unsigned End) argument 393 hasHazard(const MachineInstr &MI) argument 415 hasHazard_(const MachineInstr &MI) argument 436 hasHazard_(const MachineInstr &MI) argument 469 getUnderlyingObjects(const MachineInstr &MI, SmallVectorImpl<ValueType> &Objects) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 118 bool isCoalescableExtInstr(const MachineInstr &MI, 121 unsigned isLoadFromStackSlot(const MachineInstr *MI, 123 unsigned isStoreToStackSlot(const MachineInstr *MI, 128 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override; 130 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 134 MachineBasicBlock::iterator MI) const override; 153 MachineBasicBlock::iterator MI, DebugLoc DL, 209 bool isPredicated(const MachineInstr *MI) const override; 211 bool isUnpredicatedTerminator(const MachineInstr *MI) const override; 213 bool PredicateInstruction(MachineInstr *MI, [all...] |
H A D | PPCAsmPrinter.cpp | 84 void EmitInstruction(const MachineInstr *MI) override; 86 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); 88 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 91 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, 98 const MachineInstr &MI); 100 const MachineInstr &MI); 101 void EmitTlsCall(const MachineInstr *MI, MCSymbolRefExpr::VariantKind VK); 164 void PPCAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, argument 167 const MachineOperand &MO = MI->getOperand(OpNo); 240 bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigne argument 278 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 333 LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) argument 361 LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) argument 406 EmitTlsCall(const MachineInstr *MI, MCSymbolRefExpr::VariantKind VK) argument 440 EmitInstruction(const MachineInstr *MI) argument [all...] |
H A D | PPCVSXCopy.cpp | 87 MachineInstr *MI = I; local 88 if (!MI->isFullCopy()) 91 MachineOperand &DstMO = MI->getOperand(0); 92 MachineOperand &SrcMO = MI->getOperand(1); 107 BuildMI(MBB, MI, MI->getDebugLoc(), 131 BuildMI(MBB, MI, MI->getDebugLoc(),
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/external/llvm/lib/Target/X86/ |
H A D | X86VZeroUpper.cpp | 125 static bool hasYmmReg(MachineInstr *MI) { argument 126 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 127 const MachineOperand &MO = MI->getOperand(i); 128 if (MI->isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO)) 142 static bool callClobbersAnyYmmReg(MachineInstr *MI) { argument 143 assert(MI->isCall() && "Can only be called on call instructions."); 144 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 145 const MachineOperand &MO = MI->getOperand(i); 183 MachineInstr *MI = I; local 184 bool isControlFlow = MI [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineVerifier.cpp | 199 void visitMachineBundleBefore(const MachineInstr *MI); 200 void visitMachineInstrBefore(const MachineInstr *MI); 202 void visitMachineInstrAfter(const MachineInstr *MI); 203 void visitMachineBundleAfter(const MachineInstr *MI); 209 void report(const char *msg, const MachineInstr *MI); 220 void verifyInlineAsm(const MachineInstr *MI); 386 void MachineVerifier::report(const char *msg, const MachineInstr *MI) { argument 387 assert(MI); 388 report(msg, MI->getParent()); 390 if (Indexes && Indexes->hasIndex(MI)) 703 visitMachineBundleBefore(const MachineInstr *MI) argument 727 verifyInlineAsm(const MachineInstr *MI) argument 769 visitMachineInstrBefore(const MachineInstr *MI) argument 813 const MachineInstr *MI = MO->getParent(); local 984 const MachineInstr *MI = MO->getParent(); local 1141 visitMachineInstrAfter(const MachineInstr *MI) argument 1148 visitMachineBundleAfter(const MachineInstr *MI) argument 1419 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def); local 1517 const MachineInstr *MI = local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterPressure.h | 162 /// Store the effects of a change in pressure on things that MI scheduler cares 292 /// Get the MI position corresponding to this register pressure. 295 // Reset the MI position corresponding to the register pressure. This allows 349 void getMaxUpwardPressureDelta(const MachineInstr *MI, 355 void getUpwardPressureDelta(const MachineInstr *MI, 365 void getMaxDownwardPressureDelta(const MachineInstr *MI, 373 void getMaxPressureDelta(const MachineInstr *MI, 378 return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets, 382 return getMaxUpwardPressureDelta(MI, nullptr, Delta, CriticalPSets, 387 void getUpwardPressure(const MachineInstr *MI, [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIPrepareScratchRegs.cpp | 128 MachineInstr &MI = *I; local 130 DebugLoc DL = MI.getDebugLoc(); 131 switch(MI.getOpcode()) { 192 MI.getOperand(2).setReg(ScratchRsrcReg); 193 MI.getOperand(2).setIsKill(true); 194 MI.getOperand(2).setIsUndef(false); 195 MI.getOperand(3).setReg(ScratchOffsetReg); 196 MI.getOperand(3).setIsUndef(false); 197 MI.getOperand(3).setIsKill(false); 198 MI [all...] |
H A D | R600OptimizeVectorRegisters.cpp | 67 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { argument 68 assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE); 99 MachineInstr *RebuildVector(RegSeqInfo *MI, 132 bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI) 134 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 136 switch (MI.getOpcode()) { 234 void R600VectorRegMerger::RemoveMI(MachineInstr *MI) { argument 238 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end()); 243 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MI 247 SwizzleInput(MachineInstr &MI, const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const argument 328 MachineInstr *MI = MII; local [all...] |
H A D | R600ControlFlowFinalizer.cpp | 225 bool IsTrivialInst(MachineInstr *MI) const { 226 switch (MI->getOpcode()) { 281 bool isCompatibleWithClause(const MachineInstr *MI, argument 284 for (MachineInstr::const_mop_iterator I = MI->operands_begin(), 285 E = MI->operands_end(); I != E; ++I) { 343 void getLiteral(MachineInstr *MI, std::vector<int64_t> &Lits) const { argument 351 TII->getSrcs(MI); 460 void CounterPropagateAddr(MachineInstr *MI, unsigned Addr) const { argument 461 MI->getOperand(0).setImm(Addr + MI 507 MachineBasicBlock::iterator MI = I; variable [all...] |
H A D | SIInsertWaits.cpp | 88 Counters getHwCounts(MachineInstr &MI); 106 bool unorderedDefines(MachineInstr &MI); 109 Counters handleOperands(MachineInstr &MI); 140 Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { argument 142 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags; 149 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore())); 154 if (TII->isSMRD(MI.getOpcode())) { 156 MachineOperand &Op = MI.getOperand(0); 186 MachineInstr &MI 383 handleOperands(MachineInstr &MI) argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64LoadStoreOptimizer.cpp | 443 static void trackRegDefsUses(MachineInstr *MI, BitVector &ModifiedRegs, argument 446 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 447 MachineOperand &MO = MI->getOperand(i); 522 MachineInstr *MI = MBBI; local 525 if (MI->isDebugValue()) 531 bool CanMergeOpc = Opc == MI->getOpcode(); 540 CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode(MI->getOpcode()); 543 if (CanMergeOpc && MI->getOperand(2).isImm()) { 554 unsigned MIBaseReg = MI->getOperand(1).getReg(); 555 int MIOffset = MI 723 isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg, int Offset) argument 786 MachineInstr *MI = MBBI; local 839 MachineInstr *MI = MBBI; local 883 MachineInstr *MI = MBBI; local 954 MachineInstr *MI = MBBI; local [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DbgValueHistoryCalculator.h | 43 void startInstrRange(InlinedVariable Var, const MachineInstr &MI); 44 void endInstrRange(InlinedVariable Var, const MachineInstr &MI);
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H A D | AsmPrinterHandler.h | 54 virtual void beginInstruction(const MachineInstr *MI) = 0;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCopyToCombine.cpp | 87 MachineBasicBlock::iterator &MI, bool DoInsertAtI1); 113 static bool isCombinableInstType(MachineInstr *MI, argument 116 switch(MI->getOpcode()) { 119 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg()); 121 unsigned DestReg = MI->getOperand(0).getReg(); 122 unsigned SrcReg = MI->getOperand(1).getReg(); 130 const MachineOperand &Op0 = MI->getOperand(0); 131 const MachineOperand &Op1 = MI->getOperand(1); 150 assert(MI 207 removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) argument 358 MachineInstr *MI = I; local 509 combine(MachineInstr *I1, MachineInstr *I2, MachineBasicBlock::iterator &MI, bool DoInsertAtI1) argument [all...] |
H A D | HexagonFrameLowering.h | 30 MachineBasicBlock::iterator MI, 41 MachineBasicBlock::iterator MI,
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.h | 38 MachineBasicBlock::iterator MI, 42 MachineBasicBlock::iterator MI,
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.h | 35 MachineBasicBlock::iterator MI, 39 MachineBasicBlock::iterator MI,
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUConvertToISA.cpp | 57 MachineInstr &MI = *I; local 58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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H A D | R600ISelLowering.h | 27 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, 41 void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
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