Searched refs:MI (Results 26 - 50 of 523) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.h51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
55 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
57 bool hasLoadFromStackSlot(const MachineInstr *MI,
60 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
61 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
63 bool hasStoreFromStackSlot(const MachineInstr *MI,
74 MachineBasicBlock::iterator MI, DebugLoc DL,
79 MachineBasicBlock::iterator MI,
84 MachineBasicBlock::iterator MI,
[all...]
H A DAMDGPUMCInstLower.cpp30 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument
31 OutMI.setOpcode(MI->getOpcode());
33 for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
34 const MachineOperand &MO = MI->getOperand(i);
58 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument
62 if (MI->getOpcode() == AMDGPU::MASK_WRITE) {
66 if (MI->isBundle()) {
67 const MachineBasicBlock *MBB = MI->getParent();
68 MachineBasicBlock::const_instr_iterator I = MI;
79 MCInstLowering.lower(MI, TmpIns
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp127 bool ignorePseudoInstruction(MachineInstr *MI,
130 // isSoloInstruction - return true if instruction MI can not be packetized
131 // with any other instruction, which means that MI itself is a packet.
132 bool isSoloInstruction(MachineInstr *MI) override;
142 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
144 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
145 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
148 bool CanPromoteToDotNew(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
153 CanPromoteToNewValue(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
157 MachineInstr *MI, MachineInst
216 MachineBasicBlock::iterator MI = MBB->begin(); local
266 IsIndirectCall(MachineInstr* MI) argument
272 reserveResourcesForConstExt(MachineInstr* MI) argument
288 canReserveResourcesForConstExt(MachineInstr *MI) argument
302 tryAllocateResourcesForConstExt(MachineInstr* MI) argument
319 IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg) argument
367 IsDirectJump(MachineInstr* MI) argument
371 IsSchedBarrier(MachineInstr* MI) argument
379 IsControlFlow(MachineInstr* MI) argument
383 IsLoopN(MachineInstr *MI) argument
390 DoesModifyCalleeSavedReg(MachineInstr *MI, const TargetRegisterInfo *TRI) argument
404 isNewifiable(MachineInstr* MI) argument
409 isCondInst(MachineInstr* MI) argument
428 PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) argument
445 DemoteToDotOld(MachineInstr* MI) argument
460 getPredicateSense(MachineInstr* MI, const HexagonInstrInfo *QII) argument
471 GetPostIncrementOperand(MachineInstr *MI, const HexagonInstrInfo *QII) argument
511 GetStoreValueOperand(MachineInstr *MI) argument
535 CanPromoteToNewValueStore( MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg, const std::map<MachineInstr *, SUnit *> &MIToSUnit) argument
716 CanPromoteToNewValue( MachineInstr *MI, SUnit *PacketSU, unsigned DepReg, const std::map<MachineInstr *, SUnit *> &MIToSUnit, MachineBasicBlock::iterator &MII) argument
741 CanPromoteToDotNew( MachineInstr *MI, SUnit *PacketSU, unsigned DepReg, const std::map<MachineInstr *, SUnit *> &MIToSUnit, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC) argument
796 RestrictingDepExistInPacket( MachineInstr *MI, unsigned DepReg, const std::map<MachineInstr *, SUnit *> &MIToSUnit) argument
832 getPredicatedRegister(MachineInstr *MI, const HexagonInstrInfo *QII) argument
948 ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) argument
969 isSoloInstruction(MachineInstr *MI) argument
1338 addToPacket(MachineInstr *MI) argument
[all...]
H A DHexagonPeephole.cpp133 MachineInstr *MI = MII; local
136 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::A2_sxtw) {
137 assert (MI->getNumOperands() == 2);
138 MachineOperand &Dst = MI->getOperand(0);
139 MachineOperand &Src = MI->getOperand(1);
155 MI->getOpcode () == Hexagon::A4_combineir) {
156 assert (MI->getNumOperands() == 3);
157 MachineOperand &Dst = MI->getOperand(0);
158 MachineOperand &Src1 = MI->getOperand(1);
159 MachineOperand &Src2 = MI
[all...]
/external/llvm/lib/Target/SystemZ/InstPrinter/
H A DSystemZInstPrinter.cpp45 void SystemZInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument
48 printInstruction(MI, O);
56 void SystemZInstPrinter::printU4ImmOperand(const MCInst *MI, int OpNum, argument
58 int64_t Value = MI->getOperand(OpNum).getImm();
63 void SystemZInstPrinter::printU6ImmOperand(const MCInst *MI, int OpNum, argument
65 int64_t Value = MI->getOperand(OpNum).getImm();
70 void SystemZInstPrinter::printS8ImmOperand(const MCInst *MI, int OpNum, argument
72 int64_t Value = MI->getOperand(OpNum).getImm();
77 void SystemZInstPrinter::printU8ImmOperand(const MCInst *MI, int OpNum, argument
79 int64_t Value = MI
84 printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument
91 printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument
98 printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument
105 printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument
112 printAccessRegOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp49 void printOperand(const MachineInstr *MI, int OpNum,
51 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
53 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
56 bool PrintAsmMemoryOperand(const MachineInstr *MI,
59 void EmitInstruction(const MachineInstr *MI) override;
64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
66 const MachineOperand &MO = MI->getOperand(OpNum);
105 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, argument
107 const MachineOperand &Base = MI->getOperand(OpNum);
108 const MachineOperand &Disp = MI
127 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
138 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
150 EmitInstruction(const MachineInstr *MI) argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument
22 const MCInstrDesc &MCID = MI->getDesc();
24 if (MI->mayStore())
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
38 MachineInstr *MI = SU->getInstr(); local
40 if (!MI->isDebugValue()) {
43 const MCInstrDesc &MCID = MI->getDesc();
47 const MachineFunction *MF = MI->getParent()->getParent();
65 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
66 hasRAWHazard(DefMI, MI, TI
85 MachineInstr *MI = SU->getInstr(); local
[all...]
H A DA15SDOptimizer.cpp64 bool runOnInstruction(MachineInstr *MI);
104 bool hasPartialWrite(MachineInstr *MI);
105 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
112 MachineInstr *elideCopies(MachineInstr *MI);
113 void elideCopiesAndPHIs(MachineInstr *MI,
119 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
120 unsigned optimizeSDPattern(MachineInstr *MI);
126 void eraseInstrWithNoUses(MachineInstr *MI);
163 MachineInstr *MI = MRI->getVRegDef(SReg);
164 if (!MI) retur
184 eraseInstrWithNoUses(MachineInstr *MI) argument
252 optimizeSDPattern(MachineInstr *MI) argument
334 hasPartialWrite(MachineInstr *MI) argument
352 elideCopies(MachineInstr *MI) argument
365 elideCopiesAndPHIs(MachineInstr *MI, SmallVectorImpl<MachineInstr*> &Outs) argument
407 getReadDPRs(MachineInstr *MI) argument
533 optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) argument
588 runOnInstruction(MachineInstr *MI) argument
639 MachineInstr *MI = *II; local
[all...]
/external/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.cpp50 MachineInstr &MI = *II; local
51 MachineFunction &MF = *MI.getParent()->getParent();
52 DebugLoc DL = MI.getDebugLoc();
54 while (!MI.getOperand(i).isFI()) {
56 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
60 int FrameIndex = MI.getOperand(i).getIndex();
62 if (MI.getOpcode() == BPF::MOV_rr) {
66 MI.getOperand(i).ChangeToRegister(FrameReg, false);
68 MachineBasicBlock &MBB = *MI.getParent();
69 unsigned reg = MI
[all...]
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp47 uint64_t getBinaryCodeForInstr(const MCInst &MI,
53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
61 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
67 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
73 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
79 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
85 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigne
213 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
224 getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
245 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
271 getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
298 getCondBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
320 getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
340 getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
349 getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
368 getTestBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
390 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
418 getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
441 getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
449 getSIMDShift64_32OpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
458 getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
467 getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
477 getFixedPointScaleOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
486 getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
495 getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
504 getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
513 getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
522 getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
531 getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
540 getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
549 getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
559 getMoveVecShifterOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
570 fixMOVZ(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
601 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
619 fixMulHigh(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
629 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
638 fixOneOperandFPComparison( const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
[all...]
/external/llvm/lib/Target/PowerPC/InstPrinter/
H A DPPCInstPrinter.cpp53 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument
56 if (MI->getOpcode() == PPC::RLWINM) {
57 unsigned char SH = MI->getOperand(2).getImm();
58 unsigned char MB = MI->getOperand(3).getImm();
59 unsigned char ME = MI->getOperand(4).getImm();
69 printOperand(MI, 0, O);
71 printOperand(MI, 1, O);
79 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
80 MI
120 printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier) argument
217 printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
224 printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
231 printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
238 printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
245 printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
252 printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
259 printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
266 printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
273 printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
281 printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
289 printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
300 printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
309 printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
327 printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
338 printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
351 printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
386 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
[all...]
/external/llvm/include/llvm/CodeGen/
H A DLiveVariables.h94 bool removeKill(MachineInstr *MI) { argument
96 I = std::find(Kills.begin(), Kills.end(), MI);
146 // DistanceMap - Keep track the distance of a MI from the start of the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
161 void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
179 void runOnInstr(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
188 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
202 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI, argument
212 removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) argument
238 addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI, bool AddIfNotFound = false) argument
248 removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) argument
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp48 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
50 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI, argument
52 MachineBasicBlock *MBB = MI->getParent();
57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
58 MBB->insert(MI, EarlierMI);
62 MachineOperand &LowRegOp = MI->getOperand(0);
69 MachineOperand &LowOffsetOp = MI->getOperand(2);
78 MI->setDesc(get(LowOpcode));
81 // Split ADJDYNALLOC instruction MI.
82 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) cons
103 expandRIPseudo(MachineInstr *MI, unsigned LowOpcode, unsigned HighOpcode, bool ConvertHigh) const argument
117 expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode, unsigned LowOpcodeK, unsigned HighOpcode) const argument
138 expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode, unsigned HighOpcode) const argument
149 expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode, unsigned Size) const argument
193 isSimpleMove(const MachineInstr *MI, int &FrameIndex, unsigned Flag) argument
206 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
211 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
216 isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, int &SrcFrameIndex) const argument
399 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
426 isShift(MachineInstr *MI, int Opcode, int64_t Imm) argument
433 eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) argument
467 MachineInstr *MI = MBBI; local
533 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument
623 isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) argument
677 MachineInstr *MI = MBBI; local
749 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, int FrameIndex) const argument
867 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, MachineInstr *LoadMI) const argument
[all...]
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp69 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument
71 unsigned Opcode = MI->getOpcode();
79 switch (MI->getOperand(0).getImm()) {
102 printInstruction(MI, STI, O);
106 printPredicateOperand(MI, 1, STI, O);
115 const MCOperand &Dst = MI->getOperand(0);
116 const MCOperand &MO1 = MI->getOperand(1);
117 const MCOperand &MO2 = MI->getOperand(2);
118 const MCOperand &MO3 = MI->getOperand(3);
121 printSBitModifierOperand(MI,
319 printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) argument
357 printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument
[all...]
/external/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp64 MachineBasicBlock::iterator MI) const {
122 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI, argument
124 const MCInstrDesc &MCID = MI->getDesc();
126 if (HasDef && !MI->getOperand(0).isReg())
130 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
131 assert(MI->isCommutable() && "Precondition violation: MI must be commutable.");
135 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
137 unsigned Reg0 = HasDef ? MI
181 findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const argument
215 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument
245 hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const argument
265 hasStoreToStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const argument
322 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); local
343 canFoldCopy(const MachineInstr *MI, unsigned FoldIdx) argument
379 canFoldMemoryOperand(const MachineInstr *MI, ArrayRef<unsigned> Ops) const argument
384 foldPatchpoint(MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, int FrameIndex, const TargetInstrInfo &TII) argument
446 foldMemoryOperand(MachineBasicBlock::iterator MI, ArrayRef<unsigned> Ops, int FI) const argument
514 foldMemoryOperand(MachineBasicBlock::iterator MI, ArrayRef<unsigned> Ops, MachineInstr *LoadMI) const argument
561 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, AliasAnalysis *AA) const argument
666 isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const argument
785 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument
876 getRegSequenceInputs( const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const argument
901 getExtractSubregInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const argument
924 getInsertSubregInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const argument
[all...]
/external/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.h85 void printInstruction(const MCInst *MI, raw_ostream &O);
89 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
92 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
93 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
97 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
98 void printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O);
99 void printUnsignedImm8(const MCInst *MI, int opNum, raw_ostream &O);
100 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
101 void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
102 void printFCCOperand(const MCInst *MI, in
[all...]
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp40 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument
42 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
48 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
59 if (MI->getOpcode() == X86::CALLpcrel32 &&
62 printPCRelImm(MI, 0, OS);
65 else if (!printAliasInstr(MI, OS))
66 printInstruction(MI, OS);
72 void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, argument
74 int64_t Imm = MI->getOperand(Op).getImm();
112 void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigne argument
128 printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O) argument
142 printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
162 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
185 printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O) argument
229 printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O) argument
248 printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O) argument
259 printMemOffset(const MCInst *MI, unsigned Op, raw_ostream &O) argument
282 printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O) argument
[all...]
H A DX86InstComments.h21 bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
/external/llvm/lib/Target/MSP430/InstPrinter/
H A DMSP430InstPrinter.h28 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
32 void printInstruction(const MCInst *MI, raw_ostream &O);
35 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
37 void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
38 void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
40 void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
/external/llvm/lib/Target/XCore/InstPrinter/
H A DXCoreInstPrinter.h31 void printInstruction(const MCInst *MI, raw_ostream &O);
35 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
38 void printInlineJT(const MCInst *MI, int opNum, raw_ostream &O);
39 void printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O);
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp22 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument
25 printInstruction(MI, OS);
30 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, argument
32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
35 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, argument
37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
40 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, argument
42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
45 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, argument
47 O << formatDec(MI
50 printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
55 printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
61 printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
67 printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
73 printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
81 printDSOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
90 printDSOffset0(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
98 printDSOffset1(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
106 printGDS(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
112 printGLC(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
118 printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
124 printTFE(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
222 printVOPDst(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
290 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
346 printOperandAndMods(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
358 printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
373 printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
380 printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default) argument
392 printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
397 printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
402 printClampSI(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
408 printOModSI(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
419 printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
425 printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
430 printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
435 printOMOD(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
451 printRel(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
456 printUpdateExecMask(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
461 printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
466 printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
474 printSel(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
498 printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
523 printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
553 printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
568 printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
580 printSendMsg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
611 printWaitFlag(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
[all...]
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h53 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
59 uint64_t getBinaryCodeForInstr(const MCInst &MI,
66 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
73 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
79 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
83 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
87 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
93 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
100 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
107 unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigne
[all...]
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DSIMCCodeEmitter.cpp74 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
84 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
96 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo,
100 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
104 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
109 unsigned getEncodingType(const MCInst &MI) const;
112 unsigned getEncodingBytes(const MCInst &MI) cons
131 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const argument
140 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const argument
161 GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const argument
167 GPR2AlignEncode(const MCInst &MI, unsigned OpNo , SmallVectorImpl<MCFixup> &Fixup) const argument
173 GPR4AlignEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument
179 i32LiteralEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument
197 SMRDmemriEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument
219 VOPPostEncode(const MCInst &MI, uint64_t Value) const argument
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp73 bool isProfitableToTransform(const MachineInstr *MI) const;
78 void transformInstruction(MachineInstr *MI);
124 static unsigned getSrcFromCopy(const MachineInstr *MI, argument
129 if (MI->getOpcode() == AArch64::FMOVDXr ||
130 MI->getOpcode() == AArch64::FMOVXDr)
131 return MI->getOperand(1).getReg();
134 if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) {
136 return MI->getOperand(1).getReg();
140 if (MI
181 isTransformable(const MachineInstr *MI) argument
271 insertCopy(const TargetInstrInfo *TII, MachineInstr *MI, unsigned Dst, unsigned Src, bool IsKill) argument
285 transformInstruction(MachineInstr *MI) argument
364 MachineInstr *MI = I; local
[all...]
/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/
H A DAMDGPUInstPrinter.h18 void printInstruction(const MCInst *MI, raw_ostream &O);
22 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
25 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
26 // void printUnsignedImm(const MCInst *MI, int OpNo, raw_ostream &O);
27 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);

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