/art/tools/dexfuzz/src/dexfuzz/rawdex/ |
H A D | OpcodeInfo.java | 27 public final Opcode opcode; field in class:OpcodeInfo 35 public OpcodeInfo(Opcode opcode, String name, int opcodeValue, AbstractFormat fmt) { argument 36 this.opcode = opcode;
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H A D | CodeItem.java | 149 Opcode opcode = insn.info.opcode; 152 if (opcode == Opcode.CONST_STRING || opcode == Opcode.CONST_STRING_JUMBO) { 160 if (opcode == Opcode.CONST_CLASS 161 || opcode == Opcode.CHECK_CAST 162 || opcode == Opcode.NEW_INSTANCE 163 || opcode == Opcode.FILLED_NEW_ARRAY 164 || opcode == Opcode.FILLED_NEW_ARRAY_RANGE) { 169 } else if (opcode [all...] |
/art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
H A D | ValuePrinter.java | 216 Opcode opcode = mInsn.insn.info.opcode; 217 if (opcode == Opcode.CONST_STRING || opcode == Opcode.CONST_STRING_JUMBO) { 220 if (opcode == Opcode.IGET_BOOLEAN || opcode == Opcode.SGET_BOOLEAN) { 223 if (opcode == Opcode.IGET_BYTE || opcode == Opcode.SGET_BYTE 224 || opcode == Opcode.INT_TO_BYTE) { 227 if (opcode [all...] |
H A D | CmpBiasChanger.java | 134 Opcode opcode = mInsn.insn.info.opcode; 135 if (opcode == Opcode.CMPG_DOUBLE) { 138 if (opcode == Opcode.CMPL_DOUBLE) { 141 if (opcode == Opcode.CMPG_FLOAT) { 148 Opcode opcode = mInsn.insn.info.opcode; 149 if (Opcode.isBetween(opcode, Opcode.CMPL_FLOAT, Opcode.CMPG_DOUBLE)) {
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H A D | InstructionDuplicator.java | 74 Opcode opcode = oldInsn.insn.info.opcode; 76 if (opcode == Opcode.SPARSE_SWITCH || opcode == Opcode.PACKED_SWITCH 77 || opcode == Opcode.FILL_ARRAY_DATA || oldInsn.insn.justRaw) {
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/art/compiler/dex/quick/ |
H A D | mir_to_lir-inl.h | 46 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0, argument 50 insn->opcode = opcode; 58 if ((opcode == kPseudoTargetLabel) || (opcode == kPseudoSafepointPC) || 59 (opcode == kPseudoExportedPC)) { 71 inline LIR* Mir2Lir::NewLIR0(int opcode) { argument 72 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND)) 73 << GetTargetInstName(opcode) << " " << opcod 81 NewLIR1(int opcode, int dest) argument 91 NewLIR2(int opcode, int dest, int src1) argument 101 NewLIR2NoDest(int opcode, int src, int info) argument 111 NewLIR3(int opcode, int dest, int src1, int src2) argument 121 NewLIR4(int opcode, int dest, int src1, int src2, int info) argument 131 NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2) argument 166 int opcode = lir->opcode; local [all...] |
H A D | dex_file_method_inliner.cc | 122 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); 123 if (IsInvokeInstructionRange(invoke->dalvikInsn.opcode)) { 126 DCHECK_EQ(Instruction::FormatOf(invoke->dalvikInsn.opcode), Instruction::k35c); 133 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); 134 return IsInvokeInstructionRange(invoke->dalvikInsn.opcode) || 537 if (kIntrinsicIsStatic[intrinsic.opcode] != (info->type == kStatic)) { 541 switch (intrinsic.opcode) { 618 LOG(FATAL) << "Unexpected intrinsic opcode: " << intrinsic.opcode; 656 switch (method.opcode) { 870 Instruction::Code opcode = Instruction::MOVE_FROM16; local 908 Instruction::Code opcode = static_cast<Instruction::Code>(Instruction::IGET + data.op_variant); local 957 Instruction::Code opcode = static_cast<Instruction::Code>(Instruction::IPUT + data.op_variant); local [all...] |
H A D | local_optimizations.cc | 157 if (this_lir->flags.is_nop || IsPseudoLirOp(this_lir->opcode)) { 161 uint64_t target_flags = GetTargetInstFlags(this_lir->opcode); 211 if (check_lir->flags.is_nop || IsPseudoLirOp(check_lir->opcode)) { 222 uint64_t check_flags = GetTargetInstFlags(check_lir->opcode); 334 if (IsPseudoLirOp(this_lir->opcode)) { 338 uint64_t target_flags = GetTargetInstFlags(this_lir->opcode); 413 if (stop_here || !IsPseudoLirOp(check_lir->opcode)) { 444 if (!IsPseudoLirOp(dep_lir->opcode) && 445 (GetTargetInstFlags(dep_lir->opcode) & IS_LOAD)) { 462 if (GetTargetInstFlags(cur_lir->opcode) [all...] |
/art/runtime/ |
H A D | dex_instruction_utils.h | 52 constexpr bool IsInstructionReturn(Instruction::Code opcode) { argument 53 return Instruction::RETURN_VOID <= opcode && opcode <= Instruction::RETURN_OBJECT; 56 constexpr bool IsInstructionInvoke(Instruction::Code opcode) { argument 57 return Instruction::INVOKE_VIRTUAL <= opcode && opcode <= Instruction::INVOKE_INTERFACE_RANGE && 58 opcode != Instruction::RETURN_VOID_NO_BARRIER; 61 constexpr bool IsInstructionQuickInvoke(Instruction::Code opcode) { argument 62 return opcode == Instruction::INVOKE_VIRTUAL_QUICK || 63 opcode 66 IsInstructionInvokeStatic(Instruction::Code opcode) argument 70 IsInstructionGoto(Instruction::Code opcode) argument 74 IsInstructionIfCc(Instruction::Code opcode) argument 78 IsInstructionIfCcZ(Instruction::Code opcode) argument 129 IsInvokeInstructionRange(Instruction::Code opcode) argument 136 InvokeInstructionType(Instruction::Code opcode) argument [all...] |
H A D | dex_instruction.cc | 63 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \ 64 ((opcode == NOP) ? -1 : \ 93 Code opcode = static_cast<Code>(insn & 0xFF); local 94 return FlagsOf(opcode) & Instruction::kContinue; 156 const char* opcode = kInstructionNames[Opcode()]; local 158 case k10x: os << opcode; break; local 159 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break; 160 case k11n: os << StringPrintf("%s v%d, #%+d", opcode, VRegA_11n(), VRegB_11n()); break; 161 case k11x: os << StringPrintf("%s v%d", opcode, VRegA_11x()); break; 162 case k10t: os << StringPrintf("%s %+d", opcode, VRegA_10 332 os << opcode << " {"; local 349 os << opcode << " {"; local 363 os << opcode << " {"; local [all...] |
/art/compiler/dex/quick/x86/ |
H A D | utility_x86.cc | 34 int opcode; local 39 opcode = kX86MovsdRR; 43 opcode = kX86MovssRR; 45 opcode = kX86MovdxrRR; 49 opcode = kX86MovdrxRR; 52 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); 53 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 127 X86OpCode opcode = kX86Bkpt; local 129 case kOpNeg: opcode = r_dest_src.Is64Bit() ? kX86Neg64R : kX86Neg32R; break; 130 case kOpNot: opcode 140 X86OpCode opcode = kX86Bkpt; local 203 X86OpCode opcode = kX86Nop; local 259 X86OpCode opcode = kX86Nop; local 313 X86OpCode opcode = kX86Nop; local 372 X86OpCode opcode = kX86Nop; local 402 X86OpCode opcode = kX86Nop; local 430 X86OpCode opcode = kX86Nop; local 506 X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; local 532 X86OpCode opcode = kX86Bkpt; local 545 X86OpCode opcode = kX86Bkpt; local 557 X86OpCode opcode = kX86Bkpt; local 650 X86OpCode opcode = kX86Nop; local 801 X86OpCode opcode = kX86Nop; local 963 int opcode = mir->dalvikInsn.opcode; local 1026 AnalyzeFPInstruction(int opcode, MIR* mir) argument [all...] |
H A D | x86_lir.h | 357 // MR - Memory Register - opcode [base + disp], reg 359 // AR - Array Register - opcode [base + index * scale + disp], reg 361 // TR - Thread Register - opcode fs:[disp], reg - where fs: is equal to Thread::Current() 363 // RR - Register Register - opcode reg1, reg2 365 // RM - Register Memory - opcode reg, [base + disp] 367 // RA - Register Array - opcode reg, [base + index * scale + disp] 369 // RT - Register Thread - opcode reg, fs:[disp] - where fs: is equal to Thread::Current() 371 // RI - Register Immediate - opcode reg, #immediate 373 // MI - Memory Immediate - opcode [base + disp], #immediate 375 // AI - Array Immediate - opcode [bas 676 X86OpCode opcode; // e.g. kOpAddRI member in struct:art::X86EncodingMap 684 uint8_t opcode; // 1 byte opcode. member in struct:art::X86EncodingMap::__anon26 [all...] |
/art/disassembler/ |
H A D | disassembler_arm.cc | 252 std::string opcode; local 260 opcode = "bkpt"; 267 opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); 274 opcode = kDataProcessingOperations[op]; 313 opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); 343 opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); 350 opcode = (bl ? "bl" : "b"); 357 opcode = "???"; 360 opcode += kConditionCodeNames[cond]; 361 opcode 486 std::ostringstream opcode; local 1561 std::ostringstream opcode; local [all...] |
/art/compiler/dex/quick/arm64/ |
H A D | utility_arm64.cc | 93 bool opcode_is_wide = IS_WIDE(lir->opcode); 94 A64Opcode opcode = UNWIDE(lir->opcode); local 95 DCHECK(!IsPseudoLirOp(opcode)); 96 const A64EncodingMap *encoder = &EncodingMap[opcode]; 103 uint64_t check_flags = GetTargetInstFlags(lir->opcode); 336 bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { argument 337 switch (opcode) { 420 A64Opcode opcode = LIKELY(low_bits == 0) ? kA64Mov2rr : kA64Mvn2rr; local 421 res = NewLIR2(opcode, r_des 471 A64Opcode opcode = LIKELY(value == 0) ? WIDE(kA64Mov2rr) : WIDE(kA64Mvn2rr); local 553 A64Opcode opcode = kA64Brk1d; local 567 A64Opcode opcode = kA64Brk1d; local 633 A64Opcode opcode = kA64Brk1d; local 697 A64Opcode opcode = kA64Brk1d; local 765 A64Opcode opcode = kA64Brk1d; local 813 A64Opcode opcode = kA64Brk1d; local 941 A64Opcode opcode = kA64Brk1d; local 1028 A64Opcode opcode = kA64Brk1d; local 1113 A64Opcode opcode = kA64Brk1d; local 1194 A64Opcode opcode = kA64Brk1d; local 1290 A64Opcode opcode = kA64Brk1d; local [all...] |
/art/compiler/dex/quick/arm/ |
H A D | utility_arm.cc | 138 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { argument 139 switch (opcode) { 271 ArmOpcode opcode = kThumbBkpt; local 274 opcode = kThumbBlxR; 277 opcode = kThumbBx; 280 LOG(FATAL) << "Bad opcode " << op; 282 return NewLIR1(opcode, r_dest_src.GetReg()); 289 ArmOpcode opcode = kThumbBkpt; local 292 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; 295 opcode 442 ArmOpcode opcode = kThumbBkpt; local 516 ArmOpcode opcode = kThumbBkpt; local 660 ArmOpcode opcode = kThumbBkpt; local 752 ArmOpcode opcode = kThumbBkpt; local 818 ArmOpcode opcode = kThumbBkpt; local 880 LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, int displacement, RegStorage r_src_dest, RegStorage r_work) argument 1227 int opcode; local [all...] |
H A D | target_arm.cc | 168 int opcode = lir->opcode; local 227 if (opcode == kThumbPush || opcode == kThumbPop) { 229 if ((opcode == kThumbPush) && (use_mask->Intersects(r8Mask))) { 232 } else if ((opcode == kThumbPop) && (def_mask->Intersects(r8Mask))) { 298 static char* DecodeRegList(int opcode, int vector, char* buf, size_t buf_size) { argument 305 if (opcode == kThumbPush && i == 8) { 307 } else if (opcode == kThumbPop && i == 8) { 476 DecodeRegList(lir->opcode, operan 815 GetTargetInstFlags(int opcode) argument 820 GetTargetInstName(int opcode) argument 825 GetTargetInstFmt(int opcode) argument [all...] |
/art/compiler/dex/quick/mips/ |
H A D | utility_mips.cc | 33 int opcode; local 39 opcode = kMipsFmovd; 45 opcode = kMips64Dmtc1; 49 opcode = kMips64Dmfc1; 54 opcode = kMipsFmovs; 60 opcode = kMipsMtc1; 64 opcode = kMipsMfc1; 71 opcode = kMipsFmovd; 75 opcode = kMipsFmovs; 81 opcode 281 MipsOpCode opcode = kMipsNop; local 305 MipsOpCode opcode = kMipsNop; local 348 MipsOpCode opcode = kMipsNop; local 467 MipsOpCode opcode = kMipsNop; local 573 MipsOpCode opcode = kMipsNop; local 646 MipsOpCode opcode = kMipsNop; local 703 MipsOpCode opcode = kMipsNop; local 880 MipsOpCode opcode = kMipsNop; local [all...] |
H A D | fp_mips.cc | 26 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, argument 35 switch (opcode) { 63 LOG(FATAL) << "Unexpected opcode: " << opcode; 72 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, argument 77 switch (opcode) { 105 LOG(FATAL) << "Unpexpected opcode: " << opcode; 132 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, argument 136 switch (opcode) { 208 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument [all...] |
H A D | assemble_mips.cc | 29 * opcode: MipsOpCode enum 30 * skeleton: pre-designated bit-pattern for this opcode 44 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ 47 {k3, k3s, k3e}}, opcode, flags, name, fmt, size} 595 int opcode = lir->opcode; local 597 switch (opcode) { 604 case kMipsBeq: opcode = kMipsBne; break; 605 case kMipsBne: opcode = kMipsBeq; break; 606 case kMipsBeqz: opcode [all...] |
/art/runtime/quick/ |
H A D | inline_method_analyser.h | 140 InlineMethodOpcode opcode; member in struct:art::InlineMethod 162 static constexpr bool IsInstructionIGet(Instruction::Code opcode) { argument 163 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT; 166 static constexpr bool IsInstructionIPut(Instruction::Code opcode) { argument 167 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT; 170 static constexpr uint16_t IGetVariant(Instruction::Code opcode) { argument 171 return opcode - Instruction::IGET; 174 static constexpr uint16_t IPutVariant(Instruction::Code opcode) { argument [all...] |
H A D | inline_method_analyser.cc | 85 Instruction::Code opcode = instruction->Opcode(); local 87 switch (opcode) { 90 method->opcode = kInlineOpNop; 154 result->opcode = kInlineOpReturnArg; 191 result->opcode = kInlineOpNonWideConst; 202 Instruction::Code opcode = instruction->Opcode(); local 203 DCHECK(IsInstructionIGet(opcode)); 207 if (!(return_opcode == Instruction::RETURN_WIDE && opcode == Instruction::IGET_WIDE) && 208 !(return_opcode == Instruction::RETURN_OBJECT && opcode == Instruction::IGET_OBJECT) && 209 !(return_opcode == Instruction::RETURN && opcode ! 265 Instruction::Code opcode = instruction->Opcode(); local [all...] |
/art/tools/dexfuzz/src/dexfuzz/rawdex/formats/ |
H A D | Format21c.java | 67 if (info.opcode == Opcode.CONST_STRING) { 70 if (info.opcode == Opcode.CONST_CLASS 71 || info.opcode == Opcode.CHECK_CAST 72 || info.opcode == Opcode.NEW_INSTANCE) {
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/art/compiler/dex/ |
H A D | post_opt_passes.cc | 35 Instruction::Code opcode = mir->dalvikInsn.opcode; local 37 if (opcode == static_cast<Instruction::Code> (kMirOpPhi)) {
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H A D | mir_optimization.cc | 77 switch (d_insn->opcode) { 149 if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) || 150 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) || 151 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE)) { 155 if (MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) { 189 if (static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi) { 205 switch (mir->dalvikInsn.opcode) { 233 static constexpr ConditionCode ConditionCodeForIfCcZ(Instruction::Code opcode) { argument 234 return kIfCcZConditionCodes[opcode - Instruction::IF_EQZ]; 445 static bool EvaluateBranch(Instruction::Code opcode, int32_ argument 494 Instruction::Code opcode = mir->dalvikInsn.opcode; local 790 Instruction::Code opcode = prev->last_mir_insn->dalvikInsn.opcode; local 1666 Instruction::Code opcode = mir->dalvikInsn.opcode; local 1943 Instruction::Code opcode = mir->dalvikInsn.opcode; local [all...] |
/art/runtime/arch/x86/ |
H A D | fault_handler_x86.cc | 102 uint8_t opcode = *pc++; local 113 switch (opcode) { 134 opcode = *pc++; 143 if (x86_64 && opcode >= 0x40 && opcode <= 0x4f) { 144 opcode = *pc++; 147 if (opcode == 0x0f) { 148 // Two byte opcode 150 opcode = *pc++; 156 switch (opcode) { [all...] |