Searched refs:vC (Results 1 - 23 of 23) sorted by relevance

/art/compiler/dex/
H A Dmir_dataflow.cc927 // For vector MIRs, vC contains type information
929 int type_size = d_insn.vC >> 16;
960 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC);
968 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC);
969 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC + 1);
1016 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC);
1018 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+1);
1029 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+i);
1113 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC+i, i);
1119 // For vector MIRs, vC contain
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H A Dmir_graph.cc175 decoded_instruction->vC = inst->HasVRegC() ? inst->VRegC() : 0;
473 target += insn->dalvikInsn.vC;
852 int first_reg_in_range = insn->dalvikInsn.vC;
1363 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir);
1367 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir);
1371 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir);
1375 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir);
1379 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir);
1383 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir);
1387 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mi
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H A Dmir_optimization_test.cc58 uint32_t vC; member in struct:art::MirOptimizationTest::MIRDef
88 #define DEF_AGET_APUT(bb, opcode, vA, vB, vC) \
89 { bb, opcode, 0u, vA, vB, vC }
90 #define DEF_INVOKE(bb, opcode, vC, method_info) \
91 { bb, opcode, method_info, 0u, 0u, vC }
308 mir->dalvikInsn.vC = def->vC;
H A Dmir_optimization.cc522 IsInstructionIfCc(opcode) ? mir->dalvikInsn.vC : mir->dalvikInsn.vB;
589 mir_next->dalvikInsn.vB = mir->dalvikInsn.vC;
665 // "false" set val in vC
666 mir->dalvikInsn.vC = if_false->dalvikInsn.vB;
1018 src_vreg = mir->dalvikInsn.vC;
1681 uint32_t orig_this_reg = is_range ? mir->dalvikInsn.vC : mir->dalvikInsn.arg[0];
1691 mir->dalvikInsn.vC++;
1925 add_mir->dalvikInsn.vC = SRegToVReg(add_mir->ssa_rep->uses[2]);
1928 add_mir->dalvikInsn.vC = SRegToVReg(add_mir->ssa_rep->uses[1]);
H A Dmir_graph.h260 uint32_t vC; member in struct:art::MIR::DecodedInstruction
261 uint32_t arg[5]; /* vC/D/E/F/G in invoke or filled-new-array */
264 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) {
H A Dgvn_dead_code_elimination.cc515 mir->dalvikInsn.vC = mir->dalvikInsn.vB;
1326 if (mir->dalvikInsn.vC == 0) { // Explicit division by 0?
H A Dglobal_value_numbering_test.cc2361 mirs_[0].dalvikInsn.vC = 1234; // type for instance-of
2362 mirs_[1].dalvikInsn.vC = 1234; // type for instance-of
2412 mirs_[0].dalvikInsn.vC = 1234; // type for instance-of
2413 mirs_[1].dalvikInsn.vC = 1234; // type for instance-of
H A Dgvn_dead_code_elimination_test.cc316 mir->dalvikInsn.vC = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_C_WIDE) != 0);
853 EXPECT_EQ(1u, mirs_[2].dalvikInsn.vC);
891 EXPECT_EQ(1u, mirs_[2].dalvikInsn.vC);
927 EXPECT_EQ(0u, mirs_[1].dalvikInsn.vC);
H A Dmir_analysis.cc1232 field_idx = mir->dalvikInsn.vC;
H A Dlocal_value_numbering.cc1608 uint16_t type = mir->dalvikInsn.vC;
1907 // Same as res = op + 2 operands, except use vC as operand 2
1909 uint16_t operand2 = gvn_->LookupValue(Instruction::CONST, mir->dalvikInsn.vC, 0, 0);
H A Dtype_inference.cc799 sregs_[defs[0]] = Type::DexType(cu_->dex_file, mir->dalvikInsn.vC).AsNonNull();
H A Dtype_inference_test.cc425 mir->dalvikInsn.vC = dex_file_builder_.GetTypeIdx(type_defs_[def->metadata].descriptor);
/art/compiler/dex/quick/x86/
H A Dtarget_x86.cc1591 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1706 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1707 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1740 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1741 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1775 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1776 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1854 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1855 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1883 DCHECK_EQ(mir->dalvikInsn.vC
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H A Dquick_assemble_x86_test.cc208 mir->dalvikInsn.vC = (vector_type << 16) | vector_size; // Type size.
H A Dutility_x86.cc1001 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
H A Dint_x86.cc288 int false_val = mir->dalvikInsn.vC;
/art/compiler/dex/quick/
H A Dmir_to_lir.cc483 const uint32_t vC = mir->dalvikInsn.vC; local
620 GenInstanceof(vC, rl_dest, rl_src[0]);
666 GenNewArray(vC, rl_dest, rl_src[0]);
1126 GenArithOpIntLit(opcode, rl_dest, rl_src[0], vC);
H A Ddex_file_method_inliner.cc124 return invoke->dalvikInsn.vC + arg; // Range invoke.
692 // For invokes, the object register is in vC. For null check mir, it is in vA.
693 invoke->dalvikInsn.vA = invoke->dalvikInsn.vC;
H A Dralloc_util.cc1149 (opcode == Instruction::CHECK_CAST) ? mir->dalvikInsn.vB : mir->dalvikInsn.vC;
/art/runtime/verifier/
H A Dmethod_verifier.h450 // - vA holds word count, vC holds index of first reg.
451 bool CheckVarArgRangeRegs(uint32_t vA, uint32_t vC);
H A Dmethod_verifier.cc1209 bool MethodVerifier::CheckVarArgRangeRegs(uint32_t vA, uint32_t vC) { argument
1211 // vA/vC are unsigned 8-bit/16-bit quantities for /range instructions, so there's no risk of
1213 if (vA + vC > registers_size) {
1214 Fail(VERIFY_ERROR_BAD_CLASS_HARD) << "invalid reg index " << vA << "+" << vC
/art/compiler/dex/quick/arm/
H A Dint_arm.cc255 int false_val = mir->dalvikInsn.vC;
/art/compiler/dex/quick/arm64/
H A Dint_arm64.cc203 GenSelect(mir->dalvikInsn.vB, mir->dalvikInsn.vC, mir->meta.ccode, rl_result.reg,

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