Searched refs:RC (Results 1 - 25 of 205) sorted by relevance

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/external/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument
30 if (RC == &NVPTX::Float32RegsRegClass) {
33 if (RC == &NVPTX::Float64RegsRegClass) {
35 } else if (RC == &NVPTX::Int64RegsRegClass) {
37 } else if (RC == &NVPTX::Int32RegsRegClass) {
39 } else if (RC == &NVPTX::Int16RegsRegClass) {
41 } else if (RC == &NVPTX::Int1RegsRegClass) {
43 } else if (RC == &NVPTX::SpecialRegsRegClass) {
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { argument
52 if (RC
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H A DNVPTXRegisterInfo.h60 std::string getNVPTXRegClassName(const TargetRegisterClass *RC);
61 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
/external/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h66 // Compute all information about RC.
67 void compute(const TargetRegisterClass *RC) const;
69 // Return an up-to-date RCInfo for RC.
70 const RCInfo &get(const TargetRegisterClass *RC) const {
71 const RCInfo &RCI = RegClass[RC->getID()];
73 compute(RC);
85 /// registers in RC in the current function.
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
87 return get(RC).NumRegs;
90 /// getOrder - Returns the preferred allocation order for RC
119 getMinCost(const TargetRegisterClass *RC) argument
127 getLastCostChange(const TargetRegisterClass *RC) argument
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/external/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true);
44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC
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/external/llvm/lib/CodeGen/
H A DLiveStackAnalysis.cpp60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
68 S2RCMap.insert(std::make_pair(Slot, RC));
72 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
84 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
85 if (RC)
86 OS << " [" << TRI->getRegClassName(RC) << "]\n";
H A DRegisterClassInfo.cpp76 /// compute - Compute the preferred allocation order for RC with reserved
79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
80 assert(RC && "no register class given");
81 RCInfo &RCI = RegClass[RC->getID()];
84 unsigned NumRegs = RC->getNumRegs();
97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
133 // Check if RC is a proper sub-class.
135 TRI->getLargestLegalSuperClass(RC, *MF))
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ")
157 const TargetRegisterClass *RC = nullptr; local
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H A DTargetRegisterInfo.cpp88 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
89 if (!RC || RC->isAllocatable())
90 return RC;
92 const unsigned *SubClass = RC->getSubClassMask();
119 const TargetRegisterClass* RC = *I; local
120 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
121 (!BestRC || BestRC->hasSubClass(RC)))
122 BestRC = RC;
131 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument
236 const TargetRegisterClass *RC = local
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/external/llvm/lib/Target/R600/
H A DSIRegisterInfo.h51 bool isSGPRClass(const TargetRegisterClass *RC) const {
52 if (!RC)
55 return !hasVGPRs(RC);
67 bool hasVGPRs(const TargetRegisterClass *RC) const;
73 /// \returns The register class that is used for a sub-register of \p RC for
74 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
76 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
120 const TargetRegisterClass *RC) const;
H A DR600RegisterInfo.h41 getRegClassWeight(const TargetRegisterClass *RC) const override;
H A DSIFixSGPRCopies.cpp140 const TargetRegisterClass *RC local
145 RC = TRI->getSubRegClass(RC, SubReg);
150 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
157 return RC;
166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); local
167 return TRI->getSubRegClass(RC, SubReg);
230 const TargetRegisterClass *RC local
233 MRI.constrainRegClass(Op.getReg(), RC);
236 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, local
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/external/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp77 const TargetRegisterClass *RC = local
87 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
98 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; local
99 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
104 const TargetRegisterClass *RC = local
109 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
110 RC->getAlignment(), false);
137 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { argument
140 RC->getSize(), RC
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H A DMipsInstrInfo.h93 const TargetRegisterClass *RC,
95 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
101 const TargetRegisterClass *RC,
103 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
109 const TargetRegisterClass *RC,
116 const TargetRegisterClass *RC,
H A DMipsSEFrameLowering.cpp155 const TargetRegisterClass *RC = RegInfo.intRegClass(4); local
156 unsigned VR = MRI.createVirtualRegister(RC);
159 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
170 const TargetRegisterClass *RC = RegInfo.intRegClass(4); local
171 unsigned VR = MRI.createVirtualRegister(RC);
176 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); local
189 unsigned VR0 = MRI.createVirtualRegister(RC);
190 unsigned VR1 = MRI.createVirtualRegister(RC);
197 TII.loadRegFromStack(MBB, I, VR0, FI, RC,
213 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); local
245 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); local
294 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
348 const TargetRegisterClass *RC = local
476 const TargetRegisterClass *RC = STI.isABI_N64() ? local
542 const TargetRegisterClass *RC = STI.isABI_N64() ? local
590 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
630 const TargetRegisterClass *RC = STI.hasMips64() ? local
644 const TargetRegisterClass *RC = STI.isABI_N64() ? local
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H A DMips16RegisterInfo.h35 const TargetRegisterClass *RC,
H A DMipsSEInstrInfo.cpp182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
190 if (Mips::GPR32RegClass.hasSubClassEq(RC))
192 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
194 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
196 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
198 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
200 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
202 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
204 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
206 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
180 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
223 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
390 const TargetRegisterClass *RC = STI.isABI_N64() ? local
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/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h127 bool hasSubClass(const TargetRegisterClass *RC) const {
128 return RC != this && hasSubClassEq(RC);
131 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
133 bool hasSubClassEq(const TargetRegisterClass *RC) const {
134 unsigned ID = RC->getID();
140 bool hasSuperClass(const TargetRegisterClass *RC) const {
141 return RC->hasSubClass(this);
144 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
146 bool hasSuperClassEq(const TargetRegisterClass *RC) cons
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/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp116 for (const auto &RC : RegisterClasses)
117 OS << " " << RC.getName() << "RegClassID"
118 << " = " << RC.EnumValue << ",\n";
180 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
182 for (const auto &RC : RegBank.getRegClasses()) {
183 const CodeGenRegister::Vec &Regs = RC.getMembers();
188 RC.buildRegUnitSet(RegUnits);
192 OS << "}, \t// " << RC.getName() << "\n";
195 << " return RCWeightTable[RC->getID()];\n"
291 << "getRegClassPressureSets(const TargetRegisterClass *RC) cons
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/external/llvm/utils/release/
H A Dtest-release.sh28 RC=""
75 -rc | --rc | -RC | --RC )
77 RC="rc$1"
80 RC=final
152 if [ -z "$RC" ]; then
176 BuildDir=$BuildDir/$RC
186 if [ $RC != "final" ]; then
187 Package=$Package-$RC
232 if ! svn ls $Base_url/$proj/tags/RELEASE_$Release_no_dot/$RC > /de
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/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.h48 const TargetRegisterClass *RC,
54 const TargetRegisterClass *RC,
H A DThumb1InstrInfo.cpp73 const TargetRegisterClass *RC,
75 assert((RC == &ARM::tGPRRegClass ||
79 if (RC == &ARM::tGPRRegClass ||
101 const TargetRegisterClass *RC,
103 assert((RC == &ARM::tGPRRegClass ||
107 if (RC == &ARM::tGPRRegClass ||
71 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
99 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb2InstrInfo.h50 const TargetRegisterClass *RC,
56 const TargetRegisterClass *RC,
H A DThumbRegisterInfo.h31 getLargestLegalSuperClass(const TargetRegisterClass *RC,
57 const TargetRegisterClass *RC,
/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.h69 getSubClassWithSubReg(const TargetRegisterClass *RC,
73 getLargestLegalSuperClass(const TargetRegisterClass *RC,
86 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
88 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
/external/llvm/include/llvm/IR/
H A DInlineAsm.h281 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { argument
282 // Store RC + 1, reserve the value 0 to mean 'no register class'.
283 ++RC;
284 assert(RC <= 0x7fff && "Too large register class ID");
286 return InputFlag | (RC << 16);
338 /// class constraint. Sets RC to the register class ID.
339 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { argument
344 // stores RC + 1.
347 RC = High - 1;
/external/clang/lib/AST/
H A DRawCommentList.cpp213 void RawCommentList::addComment(const RawComment &RC, argument
215 if (RC.isInvalid())
221 RC.getLocStart())) {
228 if (RC.isOrdinary())
234 Comments.push_back(new (Allocator) RawComment(RC));
239 const RawComment &C2 = RC;
249 RC.isParseAllComments());
251 Comments.push_back(new (Allocator) RawComment(RC));

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