Searched refs:Binop (Results 1 - 21 of 21) sorted by relevance

/external/valgrind/VEX/priv/
H A Dir_match.c74 if (p->Iex.Binop.op != e->Iex.Binop.op) return False;
75 if (!matchWrk(mi, p->Iex.Binop.arg1, e->Iex.Binop.arg1))
77 if (!matchWrk(mi, p->Iex.Binop.arg2, e->Iex.Binop.arg2))
H A Dhost_arm_isel.c774 && (e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Sub32)
775 && e->Iex.Binop.arg2->tag == Iex_Const
776 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32) {
777 Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32;
780 if (e->Iex.Binop.op == Iop_Sub32)
782 reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
840 && (e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Sub32)
841 && e->Iex.Binop
[all...]
H A Dhost_tilegx_isel.c407 && e->Iex.Binop.op == Iop_Add64
408 && e->Iex.Binop.arg2->tag == Iex_Const
409 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64
410 && uInt_fits_in_16_bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)) {
412 return TILEGXAMode_IR((Long) e->Iex.Binop.arg2->Iex.Const.con->Ico.U64,
413 iselWordExpr_R(env, e->Iex.Binop.arg1));
481 switch (e->Iex.Binop.op) {
527 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
534 e->Iex.Binop.arg2);
540 e->Iex.Binop
[all...]
H A Dir_opt.c274 return toBool( isIRAtom(e->Iex.Binop.arg1)
275 && isIRAtom(e->Iex.Binop.arg2) );
334 IRExpr_Binop(ex->Iex.Binop.op,
335 flatten_Expr(bb, ex->Iex.Binop.arg1),
336 flatten_Expr(bb, ex->Iex.Binop.arg2))));
1082 return toBool( e1->Iex.Binop.op == e2->Iex.Binop.op
1083 && sameIRExprs_aux( env, e1->Iex.Binop.arg1,
1084 e2->Iex.Binop.arg1 )
1085 && sameIRExprs_aux( env, e1->Iex.Binop
[all...]
H A Dhost_x86_isel.c904 e->Iex.Binop.op==Iop_PRemC3210F64
925 if (e->Iex.Binop.op == Iop_Sub32 && isZeroU32(e->Iex.Binop.arg1)) {
927 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg2);
934 switch (e->Iex.Binop.op) {
954 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
955 X86RMI* rmi = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
979 switch (e->Iex.Binop.op) {
993 HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1);
997 switch (e->Iex.Binop
[all...]
H A Dhost_ppc_isel.c1435 switch (e->Iex.Binop.op) {
1453 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1459 e->Iex.Binop.arg2, IEndianess);
1463 e->Iex.Binop.arg2, IEndianess);
1473 switch (e->Iex.Binop.op) {
1486 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1492 ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2, IEndianess);
1494 ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2, IEndianess);
1529 if (e->Iex.Binop.op == Iop_DivS32 ||
1530 e->Iex.Binop
[all...]
H A Dhost_mips_isel.c722 if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_Add64
723 && e->Iex.Binop.arg2->tag == Iex_Const
724 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64
726 uLong_is_4_aligned(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64) : True)
727 && uLong_fits_in_16_bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)) {
728 return MIPSAMode_IR((Int) e->Iex.Binop.arg2->Iex.Const.con->Ico.U64,
729 iselWordExpr_R(env, e->Iex.Binop.arg1));
733 if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_Add64) {
734 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1);
735 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop
[all...]
H A Dhost_amd64_isel.c972 if ((e->Iex.Binop.op == Iop_Sub64 && isZeroU64(e->Iex.Binop.arg1))
973 || (e->Iex.Binop.op == Iop_Sub32 && isZeroU32(e->Iex.Binop.arg1))) {
975 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg2);
982 switch (e->Iex.Binop.op) {
1002 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
1003 AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
1010 switch (e->Iex.Binop.op) {
1024 HReg regL = iselIntExpr_R(env, e->Iex.Binop
[all...]
H A Dhost_arm64_isel.c870 && (e->Iex.Binop.op == Iop_Add64 || e->Iex.Binop.op == Iop_Sub64)
871 && e->Iex.Binop.arg2->tag == Iex_Const
872 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64) {
873 Long simm = (Long)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64;
880 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
881 if (e->Iex.Binop.op == Iop_Sub64) simm = -simm;
888 && e->Iex.Binop.op == Iop_Add64
889 && e->Iex.Binop.arg2->tag == Iex_Const
890 && e->Iex.Binop
[all...]
H A Dhost_s390_isel.c301 if (expr->tag == Iex_Binop && expr->Iex.Binop.op == Iop_Add64) {
302 IRExpr *arg1 = expr->Iex.Binop.arg1;
303 IRExpr *arg2 = expr->Iex.Binop.arg2;
924 IRExpr *arg1 = expr->Iex.Binop.arg1;
925 IRExpr *arg2 = expr->Iex.Binop.arg2;
928 switch (expr->Iex.Binop.op) {
1115 IRExpr *arg1 = expr->Iex.Binop.arg1;
1116 IRExpr *arg2 = expr->Iex.Binop.arg2;
1125 switch (expr->Iex.Binop.op) {
1343 size = (expr->Iex.Binop
[all...]
H A Dir_defs.c1314 ppIROp(e->Iex.Binop.op);
1316 ppIRExpr(e->Iex.Binop.arg1);
1318 ppIRExpr(e->Iex.Binop.arg2);
1839 e->Iex.Binop.op = op;
1840 e->Iex.Binop.arg1 = arg1;
1841 e->Iex.Binop.arg2 = arg2;
2301 return IRExpr_Binop(e->Iex.Binop.op,
2302 deepCopyIRExpr(e->Iex.Binop.arg1),
2303 deepCopyIRExpr(e->Iex.Binop.arg2));
3563 typeOfPrimop(e->Iex.Binop
[all...]
H A Dguest_arm_helpers.c802 && st->Ist.WrTmp.data->Iex.Binop.op == Iop_Or32
803 && isU32(st->Ist.WrTmp.data->Iex.Binop.arg2, (ARMCondAL << 4)))
/external/v8/test/cctest/compiler/
H A Dtest-js-typed-lowering.cc108 return reduce(Binop(op, Parameter(left_type, 0), Parameter(right_type, 1)));
111 Node* Binop(const Operator* op, Node* left, Node* right) { function in class:JSTypedLoweringTester
205 Node* add = R.Binop(R.javascript.Add(), p0, p1);
222 Node* add = R.Binop(R.javascript.Add(), p0, p1);
249 Node* add = R.Binop(ops[k], p0, p1);
319 Node* add = R.Binop(R.ops[k], p0, p1);
379 Node* add = R.Binop(R.ops[k], p0, p1);
651 Node* cmp = R.Binop(ops[k], p0, p1);
706 Node* cmp = R.Binop(ops[k], p0, p1);
737 Node* cmp = R.Binop(
[all...]
/external/valgrind/coregrind/
H A Dm_translate.c422 if (e->Iex.Binop.arg1->tag != Iex_RdTmp) goto case3;
423 if (!get_SP_delta(e->Iex.Binop.arg1->Iex.RdTmp.tmp, &delta)) goto case3;
424 if (e->Iex.Binop.arg2->tag != Iex_Const) goto case3;
425 if (!IS_ADD_OR_SUB(e->Iex.Binop.op)) goto case3;
426 con = GET_CONST(e->Iex.Binop.arg2->Iex.Const.con);
428 if (IS_ADD(e->Iex.Binop.op)) {
/external/valgrind/coregrind/m_debuginfo/
H A Dstorage.c859 e.Cex.Binop.op = op;
860 e.Cex.Binop.ixL = ixL;
861 e.Cex.Binop.ixR = ixR;
961 ML_(ppCfiExpr)(src, e->Cex.Binop.ixL);
963 ppCfiBinop(e->Cex.Binop.op);
965 ML_(ppCfiExpr)(src, e->Cex.Binop.ixR);
H A Dpriv_storage.h442 } Binop; member in union:__anon15895::__anon15896
H A Ddebuginfo.c2447 wL = evalCfiExpr( exprs, e->Cex.Binop.ixL, eec, ok );
2449 wR = evalCfiExpr( exprs, e->Cex.Binop.ixR, eec, ok );
2451 switch (e->Cex.Binop.op) {
H A Dreaddwarf.c2487 cpL = copy_convert_CfiExpr_tree( dstxa, srcuc, src->Cex.Binop.ixL );
2488 cpR = copy_convert_CfiExpr_tree( dstxa, srcuc, src->Cex.Binop.ixR );
2492 return ML_(CfiExpr_Binop)( dstxa, src->Cex.Binop.op, cpL, cpR );
/external/valgrind/memcheck/
H A Dmc_translate.c4921 e->Iex.Binop.op,
4922 e->Iex.Binop.arg1, e->Iex.Binop.arg2
6160 return isBogusAtom(e->Iex.Binop.arg1)
6161 || isBogusAtom(e->Iex.Binop.arg2);
6592 return e1->Iex.Binop.op == e2->Iex.Binop.op
6593 && sameIRValue(e1->Iex.Binop.arg1, e2->Iex.Binop.arg1)
6594 && sameIRValue(e1->Iex.Binop
[all...]
/external/valgrind/VEX/useful/
H A Dtest_main.c2180 e->Iex.Binop.op,
2181 e->Iex.Binop.arg1, e->Iex.Binop.arg2
2583 return isBogusAtom(e->Iex.Binop.arg1)
2584 || isBogusAtom(e->Iex.Binop.arg2);
/external/valgrind/VEX/pub/
H A Dlibvex_ir.h405 /* Primitive operations that are used in Unop, Binop, Triop and Qop
2018 } Binop; member in union:_IRExpr::__anon15748

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