Searched refs:CTX_RB3D_CNTL (Results 1 - 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c334 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
336 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
339 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
342 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
345 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
387 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
703 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
708 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
711 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
721 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |
[all...]
H A Dradeon_state.c142 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
144 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
1528 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ALPHA_BLEND_ENABLE;
1530 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ALPHA_BLEND_ENABLE;
1534 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
1536 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
1585 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_Z_ENABLE;
1587 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_Z_ENABLE;
1594 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
1595 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL]
[all...]
H A Dradeon_context.h99 #define CTX_RB3D_CNTL 10 macro
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_state.c205 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &
218 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
223 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
226 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
682 GLuint flag = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & ~R200_PLANE_MASK_ENABLE;
697 if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) {
699 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag;
1777 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_Z_ENABLE;
1779 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_Z_ENABLE;
1786 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |
[all...]
H A Dr200_state_init.c451 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
453 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
456 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
459 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
462 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
505 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
963 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
966 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
976 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
978 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |
[all...]
H A Dr200_context.h108 #define CTX_RB3D_CNTL 10 macro

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