Searched refs:Inst (Results 1 - 25 of 249) sorted by relevance

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/external/llvm/lib/MC/
H A DMCInstrAnalysis.cpp13 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument
15 if (Inst.getNumOperands() == 0 ||
16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
19 int64_t Imm = Inst.getOperand(0).getImm();
/external/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h34 virtual bool isBranch(const MCInst &Inst) const {
35 return Info->get(Inst.getOpcode()).isBranch();
38 virtual bool isConditionalBranch(const MCInst &Inst) const {
39 return Info->get(Inst.getOpcode()).isConditionalBranch();
42 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
46 virtual bool isIndirectBranch(const MCInst &Inst) const {
47 return Info->get(Inst.getOpcode()).isIndirectBranch();
50 virtual bool isCall(const MCInst &Inst) const {
51 return Info->get(Inst
[all...]
H A DMCInstBuilder.h23 MCInst Inst; member in class:llvm::MCInstBuilder
28 Inst.setOpcode(Opcode);
33 Inst.addOperand(MCOperand::CreateReg(Reg));
39 Inst.addOperand(MCOperand::CreateImm(Val));
45 Inst.addOperand(MCOperand::CreateFPImm(Val));
51 Inst.addOperand(MCOperand::CreateExpr(Val));
57 Inst.addOperand(MCOperand::CreateInst(Val));
62 return Inst;
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
92 static DecodeStatus Decode2RInstruction(MCInst &Inst,
97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
199 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
211 DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
223 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
234 DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
275 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
345 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
358 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
371 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
384 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
398 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
411 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
424 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
438 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
509 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
523 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
537 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
550 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
563 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
576 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
589 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
603 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
618 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
632 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
646 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
666 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
680 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
700 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
719 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64AddressTypePromotion.cpp107 /// - Inst is used only once (no need to insert truncate).
108 /// - Inst has only one operand that will require a sext operation (we do
110 bool shouldGetThrough(const Instruction *Inst);
118 bool canGetThrough(const Instruction *Inst);
155 bool AArch64AddressTypePromotion::canGetThrough(const Instruction *Inst) { argument
156 if (isa<SExtInst>(Inst))
159 const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst);
165 if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) {
166 const Instruction *Opnd = cast<Instruction>(Inst
178 shouldGetThrough(const Instruction *Inst) argument
207 shouldSExtOperand(const Instruction *Inst, int OpIdx) argument
391 << *Inst << '\\n'); local
440 const Instruction *Inst = dyn_cast<GetElementPtrInst>(U); local
451 Instruction *Inst = SExt; local
[all...]
/external/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp49 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument
55 Inst.addOperand(MCOperand::CreateReg(RegNo));
59 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
62 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs);
65 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
68 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs);
71 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
74 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs);
77 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
80 return decodeRegisterClass(Inst, RegN
[all...]
/external/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp53 Instruction *Inst; member in struct:__anon11014::SimpleValue
55 SimpleValue(Instruction *I) : Inst(I) {
56 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!");
60 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() ||
61 Inst == DenseMapInfo<Instruction *>::getTombstoneKey();
64 static bool canHandle(Instruction *Inst) { argument
66 if (CallInst *CI = dyn_cast<CallInst>(Inst))
68 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) ||
69 isa<GetElementPtrInst>(Inst) || is
91 Instruction *Inst = Val.Inst; local
200 Instruction *Inst; member in struct:__anon11015::CallValue
211 canHandle(Instruction *Inst) argument
238 Instruction *Inst = Val.Inst; local
384 ParseMemoryInst(Instruction *Inst, const TargetTransformInfo &TTI) argument
415 isMatchingMemLoc(const ParseMemoryInst &Inst) argument
440 getOrCreateResult(Value *Inst, Type *ExpectedType) const argument
476 Instruction *Inst = I++; local
605 << " due to: " << *Inst << '\\n'); local
[all...]
H A DSink.cpp60 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
61 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const;
76 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument
82 for (Use &U : Inst->uses()) {
137 Instruction *Inst = I; // The instruction to sink. local
145 if (isa<DbgInfoIntrinsic>(Inst))
148 if (SinkInstruction(Inst, Stores))
157 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument
160 if (Inst->mayWriteToMemory()) {
161 Stores.insert(Inst);
180 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const argument
219 SinkInstruction(Instruction *Inst, SmallPtrSetImpl<Instruction *> &Stores) argument
[all...]
H A DConstantHoisting.cpp66 Instruction *Inst; member in struct:__anon11007::ConstantUser
69 ConstantUser(Instruction *Inst, unsigned Idx) : Inst(Inst), OpndIdx(Idx) { } argument
82 void addUser(Instruction *Inst, unsigned Idx, unsigned Cost) { argument
84 Uses.push_back(ConstantUser(Inst, Idx));
157 Instruction *findMatInsertPt(Instruction *Inst, unsigned Idx = ~0U) const;
160 Instruction *Inst, unsigned Idx,
163 Instruction *Inst);
214 Instruction *ConstantHoisting::findMatInsertPt(Instruction *Inst, argument
275 collectConstantCandidates(ConstCandMapType &ConstCandMap, Instruction *Inst, unsigned Idx, ConstantInt *ConstInt) argument
312 collectConstantCandidates(ConstCandMapType &ConstCandMap, Instruction *Inst) argument
445 updateOperand(Instruction *Inst, unsigned Idx, Instruction *Mat) argument
[all...]
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp65 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
70 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
75 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
80 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
85 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
90 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
95 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
100 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
105 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
110 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
907 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
916 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
929 DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
940 DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
951 DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
962 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
973 DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
983 DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
990 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1002 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1014 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1025 DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1036 DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1047 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1070 DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1087 DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1104 DecodeCacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1121 DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1136 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1182 DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1234 DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1250 DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1266 DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1282 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1317 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1335 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1353 DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1371 DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1389 DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1406 DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1428 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1439 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1452 DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1464 DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1476 DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1488 DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1500 DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1512 DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1524 DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1536 DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1548 DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1560 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1569 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1579 DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1589 DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1599 DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1608 DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1617 DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1626 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1635 DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1648 DecodeUImm6Lsl2(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1656 DecodeLiSimm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1667 DecodeSimm4(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1675 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1683 DecodeLSAImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1692 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1703 DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1712 DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1718 DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1724 DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1738 DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/Analysis/
H A DCFLAliasAnalysis.cpp62 // Returns possible functions called by the Inst* into the given
67 template <typename Inst>
68 static bool getPossibleTargets(Inst *, SmallVectorImpl<Function *> &);
273 void visitPtrToIntInst(PtrToIntInst &Inst) { argument
274 auto *Ptr = Inst.getOperand(0);
278 void visitIntToPtrInst(IntToPtrInst &Inst) { argument
279 auto *Ptr = &Inst;
283 void visitCastInst(CastInst &Inst) { argument
285 Edge(&Inst, Inst
288 visitBinaryOperator(BinaryOperator &Inst) argument
295 visitAtomicCmpXchgInst(AtomicCmpXchgInst &Inst) argument
301 visitAtomicRMWInst(AtomicRMWInst &Inst) argument
307 visitPHINode(PHINode &Inst) argument
314 visitGetElementPtrInst(GetElementPtrInst &Inst) argument
321 visitSelectInst(SelectInst &Inst) argument
335 visitLoadInst(LoadInst &Inst) argument
341 visitStoreInst(StoreInst &Inst) argument
347 visitVAArgInst(VAArgInst &Inst) argument
483 visitCallLikeInst(InstT &Inst) argument
496 visitCallInst(CallInst &Inst) argument
498 visitInvokeInst(InvokeInst &Inst) argument
505 visitExtractElementInst(ExtractElementInst &Inst) argument
511 visitInsertElementInst(InsertElementInst &Inst) argument
518 visitLandingPadInst(LandingPadInst &Inst) argument
525 visitInsertValueInst(InsertValueInst &Inst) argument
532 visitExtractValueInst(ExtractValueInst &Inst) argument
537 visitShuffleVectorInst(ShuffleVectorInst &Inst) argument
558 visitInstruction(Instruction &Inst) argument
560 visitStoreInst(StoreInst &Inst) argument
562 visitAtomicCmpXchgInst(AtomicCmpXchgInst &Inst) argument
566 visitAtomicRMWInst(AtomicRMWInst &Inst) argument
570 visitInsertElementInst(InsertElementInst &Inst) argument
574 visitInsertValueInst(InsertValueInst &Inst) argument
800 getTargetValue(Instruction *Inst) argument
805 hasUsefulEdges(Instruction *Inst) argument
842 argsToEdges(CFLAliasAnalysis &Analysis, Instruction *Inst, SmallVectorImpl<Edge> &Output) argument
894 addInstructionToGraph(CFLAliasAnalysis &Analysis, Instruction &Inst, SmallVectorImpl<Value *> &ReturnedValues, NodeMapT &Map, GraphT &Graph) argument
[all...]
H A DPHITransAddr.cpp25 static bool CanPHITrans(Instruction *Inst) { argument
26 if (isa<PHINode>(Inst) ||
27 isa<GetElementPtrInst>(Inst))
30 if (isa<CastInst>(Inst) &&
31 isSafeToSpeculativelyExecute(Inst))
34 if (Inst->getOpcode() == Instruction::Add &&
35 isa<ConstantInt>(Inst->getOperand(1)))
118 Instruction *Inst = dyn_cast<Instruction>(Addr); local
119 return !Inst || CanPHITrans(Inst);
149 Instruction *Inst = dyn_cast<Instruction>(V); local
[all...]
H A DMemDepPrinter.cpp100 Instruction *Inst = &I; local
102 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory())
105 MemDepResult Res = MDA.getDependency(Inst);
107 Deps[Inst].insert(std::make_pair(getInstTypePair(Res),
109 } else if (auto CS = CallSite(Inst)) {
113 DepSet &InstDeps = Deps[Inst];
121 assert( (isa<LoadInst>(Inst) || isa<StoreInst>(Inst) ||
122 isa<VAArgInst>(Inst))
139 const Instruction *Inst = &I; local
[all...]
H A DDelinearization.cpp73 static Value *getPointerOperand(Instruction &Inst) { argument
74 if (LoadInst *Load = dyn_cast<LoadInst>(&Inst))
76 else if (StoreInst *Store = dyn_cast<StoreInst>(&Inst))
78 else if (GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(&Inst))
86 Instruction *Inst = &(*I); local
89 if (!isa<StoreInst>(Inst) && !isa<LoadInst>(Inst) &&
90 !isa<GetElementPtrInst>(Inst))
93 const BasicBlock *BB = Inst->getParent();
97 const SCEV *AccessFn = SE->getSCEVAtScope(getPointerOperand(*Inst),
113 O << "Inst:" << *Inst << "\\n"; local
[all...]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigne
891 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
902 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
915 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
929 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
941 DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
956 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
986 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1006 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1027 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1041 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1049 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1064 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1084 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1105 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1117 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1131 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1140 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1177 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1212 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1249 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1273 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1298 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1325 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1475 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1580 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1624 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1815 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1844 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1867 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1958 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2005 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2047 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2071 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2098 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2126 DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2147 DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2174 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2194 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2213 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2219 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2246 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2272 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2289 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2563 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2576 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2591 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2604 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2614 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2885 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2932 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2980 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3015 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3068 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3113 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3132 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3138 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3144 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3150 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3156 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3192 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3216 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3224 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3232 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3240 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3255 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3269 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3279 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3287 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3315 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3396 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3479 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3558 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3597 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3649 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3663 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3678 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument
3693 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3706 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3752 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3813 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3839 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3850 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3875 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3886 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3899 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3923 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3938 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3954 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3996 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4028 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4036 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4059 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4068 DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4077 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4139 DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4162 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4183 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4208 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4233 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4261 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4286 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4311 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4378 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4444 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4511 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4575 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4645 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4709 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4790 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4862 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4888 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4914 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4934 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4971 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5005 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument
5020 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument
5031 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5058 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5088 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5118 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
5145 DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
[all...]
/external/llvm/lib/Transforms/ObjCARC/
H A DDependencyAnalysis.h61 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg,
66 bool CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA,
71 bool CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
74 /// Returns true if we can not conservatively prove that Inst can not decrement
76 bool CanDecrementRefCount(const Instruction *Inst, const Value *Ptr,
79 static inline bool CanDecrementRefCount(const Instruction *Inst, argument
82 return CanDecrementRefCount(Inst, Ptr, PA, GetARCInstKind(Inst));
H A DDependencyAnalysis.cpp35 bool llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, argument
48 ImmutableCallSite CS(Inst);
56 const DataLayout &DL = Inst->getModule()->getDataLayout();
71 bool llvm::objcarc::CanDecrementRefCount(const Instruction *Inst, argument
80 return CanAlterRefCount(Inst, Ptr, PA, Class);
85 bool llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, argument
92 const DataLayout &DL = Inst->getModule()->getDataLayout();
96 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) {
102 } else if (auto CS = ImmutableCallSite(Inst)) {
112 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
135 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg, ProvenanceAnalysis &PA) argument
255 Instruction *Inst = --LocalStartPos; local
[all...]
H A DObjCARCExpand.cpp98 Instruction *Inst = &*I; local
100 DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n");
102 switch (GetBasicARCInstKind(Inst)) {
114 Value *Value = cast<CallInst>(Inst)->getArgOperand(0);
115 DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst << "\n"
117 Inst->replaceAllUsesWith(Value);
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp192 bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands,
329 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
330 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
332 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
333 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
373 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1750 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument
1753 Inst.addOperand(MCOperand::CreateImm(0));
1755 Inst
1760 addCondCodeOperands(MCInst &Inst, unsigned N) const argument
1767 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument
1772 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument
1777 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument
1782 addITMaskOperands(MCInst &Inst, unsigned N) const argument
1787 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument
1792 addCCOutOperands(MCInst &Inst, unsigned N) const argument
1797 addRegOperands(MCInst &Inst, unsigned N) const argument
1802 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument
1812 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument
1823 addShifterImmOperands(MCInst &Inst, unsigned N) const argument
1829 addRegListOperands(MCInst &Inst, unsigned N) const argument
1837 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument
1841 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument
1845 addRotImmOperands(MCInst &Inst, unsigned N) const argument
1851 addModImmOperands(MCInst &Inst, unsigned N) const argument
1861 addModImmNotOperands(MCInst &Inst, unsigned N) const argument
1868 addModImmNegOperands(MCInst &Inst, unsigned N) const argument
1875 addBitfieldOperands(MCInst &Inst, unsigned N) const argument
1886 addImmOperands(MCInst &Inst, unsigned N) const argument
1891 addFBits16Operands(MCInst &Inst, unsigned N) const argument
1897 addFBits32Operands(MCInst &Inst, unsigned N) const argument
1903 addFPImmOperands(MCInst &Inst, unsigned N) const argument
1910 addImm8s4Operands(MCInst &Inst, unsigned N) const argument
1918 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument
1926 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument
1934 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument
1942 addImm1_16Operands(MCInst &Inst, unsigned N) const argument
1950 addImm1_32Operands(MCInst &Inst, unsigned N) const argument
1958 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument
1967 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument
1976 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument
1984 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument
1992 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument
2000 addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const argument
2011 addThumbMemPCOperands(MCInst &Inst, unsigned N) const argument
2031 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument
2036 addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const argument
2041 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument
2046 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument
2052 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument
2068 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument
2074 addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const argument
2078 addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const argument
2082 addAlignedMemory16Operands(MCInst &Inst, unsigned N) const argument
2086 addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const argument
2090 addAlignedMemory32Operands(MCInst &Inst, unsigned N) const argument
2094 addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const argument
2098 addAlignedMemory64Operands(MCInst &Inst, unsigned N) const argument
2102 addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const argument
2106 addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const argument
2110 addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const argument
2114 addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const argument
2118 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument
2336 addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const argument
2343 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument
2350 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument
2357 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument
2368 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument
2380 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument
2386 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument
2397 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument
2402 addBankedRegOperands(MCInst &Inst, unsigned N) const argument
2407 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument
2412 addVecListOperands(MCInst &Inst, unsigned N) const argument
2417 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument
2423 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument
2428 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument
2433 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument
2438 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument
2446 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument
2455 addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const argument
2464 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument
2473 addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const argument
2482 addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const argument
2495 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument
2509 addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const argument
2522 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument
2536 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument
4695 cvtThumbMultiply(MCInst &Inst, const OperandVector &Operands) argument
4711 cvtThumbBranches(MCInst &Inst, const OperandVector &Operands) argument
5629 RequiresVFPRegListValidation(StringRef Inst, bool &AcceptSinglePrecisionOnly, bool &AcceptDoublePrecisionOnly) argument
5988 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
6004 listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) argument
6015 instIsBreakpoint(const MCInst &Inst) argument
6023 validatetLDMRegList(MCInst Inst, const OperandVector &Operands, unsigned ListNo, bool IsARPop) argument
6046 validatetSTMRegList(MCInst Inst, const OperandVector &Operands, unsigned ListNo) argument
6068 validateInstruction(MCInst &Inst, const OperandVector &Operands) argument
6694 processInstruction(MCInst &Inst, const OperandVector &Operands, MCStreamer &Out) argument
8528 checkTargetMatchPredicate(MCInst &Inst) argument
8581 MCInst Inst; local
[all...]
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp33 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
36 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
40 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
46 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
49 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
55 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
58 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
61 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
257 DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
268 DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
286 DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
307 DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
328 DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
349 DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
370 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
381 DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
403 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
414 DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
437 DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
459 DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
482 DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
505 DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
526 DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
549 DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
572 DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
582 DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
591 DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
598 DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
614 DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
621 DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
631 DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
639 DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
662 DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument
668 DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument
674 DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
679 DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
685 DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
690 DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
696 DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
701 DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
707 DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
712 DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
717 DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
722 DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
727 DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
732 DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
794 DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
827 DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
888 DecodeSignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1073 DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1156 DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1285 DecodeAddSubERegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1342 DecodeLogicalImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1373 DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1412 DecodeModImmTiedInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1430 DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1449 DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1485 DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1502 DecodeSystemPStateInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1523 DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
[all...]
/external/llvm/utils/TableGen/
H A DInstrInfoEmitter.cpp55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument
91 for (auto &Op : Inst.Operands) {
180 for (const CodeGenInstruction *Inst : Target.instructions()) {
181 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
208 for (const CodeGenInstruction *Inst : NumberedInstructions) {
209 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
212 for (const auto &Info : Inst->Operands) {
221 OperandMap[OpList].push_back(Namespace + "::" + Inst
363 Record *Inst = II->TheDef; local
464 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.h19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate
21 Inst(unsigned Opc, unsigned ImmOpnd);
23 typedef SmallVector<Inst, 7 > InstSeq;
33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp179 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument
182 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
186 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
189 return decodeRegisterClass(Inst, RegNo, CRRegs);
192 static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo,
195 return decodeRegisterClass(Inst, RegNo, CRRegs);
198 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
201 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
204 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
207 return decodeRegisterClass(Inst, RegN
[all...]
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_init.h80 lp_set_load_alignment(LLVMValueRef Inst,
84 lp_set_store_alignment(LLVMValueRef Inst,
/external/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp262 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
517 void addRegOperands(MCInst &Inst, unsigned N) const { argument
521 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { argument
523 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
526 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { argument
528 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
531 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { argument
533 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
536 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { argument
538 Inst
541 addRegGxRCOperands(MCInst &Inst, unsigned N) const argument
548 addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const argument
555 addRegF4RCOperands(MCInst &Inst, unsigned N) const argument
560 addRegF8RCOperands(MCInst &Inst, unsigned N) const argument
565 addRegVRRCOperands(MCInst &Inst, unsigned N) const argument
570 addRegVSRCOperands(MCInst &Inst, unsigned N) const argument
575 addRegVSFRCOperands(MCInst &Inst, unsigned N) const argument
580 addRegQFRCOperands(MCInst &Inst, unsigned N) const argument
585 addRegQSRCOperands(MCInst &Inst, unsigned N) const argument
590 addRegQBRCOperands(MCInst &Inst, unsigned N) const argument
595 addRegCRBITRCOperands(MCInst &Inst, unsigned N) const argument
600 addRegCRRCOperands(MCInst &Inst, unsigned N) const argument
605 addCRBitMaskOperands(MCInst &Inst, unsigned N) const argument
610 addImmOperands(MCInst &Inst, unsigned N) const argument
618 addS16ImmOperands(MCInst &Inst, unsigned N) const argument
633 addU16ImmOperands(MCInst &Inst, unsigned N) const argument
648 addBranchTargetOperands(MCInst &Inst, unsigned N) const argument
656 addTLSRegOperands(MCInst &Inst, unsigned N) const argument
778 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) argument
800 ProcessInstruction(MCInst &Inst, const OperandVector &Operands) argument
1133 MCInst Inst; local
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