Searched refs:R600 (Results 1 - 19 of 19) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/TargetInfo/
H A DAMDGPUTargetInfo.cpp25 R600(TheAMDGPUTarget, "r600", "AMD GPUs HD2XXX-HD6XXX");
/external/llvm/lib/Target/R600/TargetInfo/
H A DAMDGPUTargetInfo.cpp20 /// be deprecated and there will be a R600 target and a GCN target.
28 R600(TheAMDGPUTarget, "r600", "AMD GPUs HD2XXX-HD6XXX");
/external/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.h38 R600, enumerator in enum:radeon_generation
H A Dradeon_drm_winsys.c234 ws->gen = R600;
273 else if (ws->gen >= R600) {
307 if (ws->gen == R600 && !debug_get_bool_option("RADEON_VA", FALSE))
329 if (ws->gen >= R600) {
391 ws->gen < R600) {
421 if (ws->gen >= R600) {
/external/llvm/lib/Target/R600/
H A DAMDGPUSubtarget.cpp68 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
H A DAMDGPUSubtarget.h38 R600 = 0, enumerator in enum:llvm::AMDGPUSubtarget::Generation
/external/mesa3d/include/pci_ids/
H A Dr600_pci_ids.h1 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
/external/clang/include/clang/Basic/
H A DTargetBuiltins.h75 /// \brief R600 builtins
76 namespace R600 { namespace in namespace:clang
/external/libdrm/radeon/
H A Dr600_pci_ids.h1 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600.h69 R600, enumerator in enum:chip_class
H A Dr600_pipe.c249 case R600:
305 if (rctx->chip_class == R600)
335 case CHIP_R600: return "AMD R600";
418 /* Supported except the original R600. */
421 /* R600 doesn't support per-MRT blends */
930 rscreen->chip_class = R600;
935 case R600:
H A Dr600_asm.c42 case R600:
259 if ((chip_class == R600) &&
345 case R600:
426 case R600:
447 case R600:
462 case R600:
496 case R600:
536 * R600:
552 case R600:
593 case R600
[all...]
H A Dr600_state.c591 if (rscreen->chip_class == R600 &&
710 /* R600 does not support per-MRT blends */
772 /* R600 does not support per-MRT blends */
1201 if (rctx->chip_class == R600) {
1358 if (rctx->chip_class == R600) {
1593 bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
1763 if (rctx->chip_class == R600) {
2162 if (rctx->chip_class == R600) {
2553 /* HW bug in original R600 */
H A Dr600_hw_context.c198 /* ignore regs not on R600 on R600 */
240 /* R600/R700 configuration */
911 if (ctx->chip_class == R600) {
1241 if (ctx->chip_class == R600) {
H A Dr600_blit.c153 if (rctx->chip_class == R600 && max_sample > 0) {
H A Dr600_state_common.c353 if (rctx->chip_class == R600) {
H A Dr600_shader.c1245 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1265 fprintf(stderr, "R600 LLVM backend failed to compile "
1991 if (ctx->bc->chip_class == R600) {
/external/clang/lib/CodeGen/
H A DCGBuiltin.cpp6415 case R600::BI__builtin_amdgpu_div_scale:
6416 case R600::BI__builtin_amdgpu_div_scalef: {
6443 case R600::BI__builtin_amdgpu_div_fmas:
6444 case R600::BI__builtin_amdgpu_div_fmasf: {
6455 case R600::BI__builtin_amdgpu_div_fixup:
6456 case R600::BI__builtin_amdgpu_div_fixupf:
6458 case R600::BI__builtin_amdgpu_trig_preop:
6459 case R600::BI__builtin_amdgpu_trig_preopf:
6461 case R600::BI__builtin_amdgpu_rcp:
6462 case R600
[all...]
/external/clang/lib/Basic/
H A DTargets.cpp1683 /// \brief The GPU profiles supported by the R600 target.
1748 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;

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