Searched refs:Reg (Results 1 - 25 of 326) sorted by relevance

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/external/llvm/lib/Target/X86/
H A DX86MachineFunctionInfo.cpp25 unsigned Reg = *CSR;
28 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
/external/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/external/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp41 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
43 VRegInfo[Reg].first = RC;
47 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
50 const TargetRegisterClass *OldRC = getRegClass(Reg);
59 setRegClass(Reg, NewRC);
64 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { argument
66 const TargetRegisterClass *OldRC = getRegClass(Reg);
75 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
84 setRegClass(Reg, NewRC);
98 unsigned Reg local
111 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DLivePhysRegs.cpp43 unsigned Reg = O->getReg(); local
44 if (Reg == 0)
46 removeReg(Reg);
55 unsigned Reg = O->getReg(); local
56 if (Reg == 0)
58 addReg(Reg);
71 unsigned Reg = O->getReg(); local
72 if (Reg == 0)
76 Defs.push_back(Reg);
81 removeReg(Reg);
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H A DMachineInstrBundle.cpp134 unsigned Reg = MO.getReg(); local
135 if (!Reg)
137 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
138 if (LocalDefSet.count(Reg)) {
142 KilledDefSet.insert(Reg);
144 if (ExternUseSet.insert(Reg).second) {
145 ExternUses.push_back(Reg);
147 UndefUseSet.insert(Reg);
151 KilledUseSet.insert(Reg);
157 unsigned Reg local
188 unsigned Reg = LocalDefs[i]; local
198 unsigned Reg = ExternUses[i]; local
253 analyzeVirtReg(unsigned Reg, SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) argument
282 analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) argument
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H A DAggressiveAntiDepBreaker.cpp60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument
106 IsLive(unsigned Reg) argument
155 unsigned Reg = *AI; local
168 unsigned Reg = *I; local
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H A DCriticalAntiDepBreaker.cpp63 unsigned Reg = *AI; local
64 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
65 KillIndices[Reg] = BBSize;
66 DefIndices[Reg] = ~0u;
78 unsigned Reg = *AI; local
79 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
80 KillIndices[Reg] = BBSize;
81 DefIndices[Reg] = ~0u;
104 for (unsigned Reg = 0; Reg !
176 unsigned Reg = MO.getReg(); local
262 unsigned Reg = MO.getReg(); local
290 unsigned Reg = MO.getReg(); local
601 unsigned Reg = MO.getReg(); local
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H A DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { argument
183 VarInfo &VRInfo = getVarInfo(Reg);
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
219 if (TRI->isSubRegister(Reg, DefReg)) {
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { argument
232 MachineInstr *LastDef = PhysRegDef[Reg];
234 if (!LastDef && !PhysRegUse[Reg]) {
242 // All of the sub-registers must have been defined before the use of Reg!
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg
281 FindLastRefOrPartRef(unsigned Reg) argument
311 HandlePhysRegKill(unsigned Reg, MachineInstr *MI) argument
443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVectorImpl<unsigned> &Defs) argument
489 unsigned Reg = Defs.back(); local
656 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
681 replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI) argument
694 unsigned Reg = MO.getReg(); local
720 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument
738 isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) argument
819 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DAllocationOrder.h54 unsigned Reg = Order[Pos++]; local
55 if (!isHint(Reg))
56 return Reg;
H A DDeadMachineInstructionElim.cpp75 unsigned Reg = MO.getReg(); local
76 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
78 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
81 if (!MRI->use_nodbg_empty(Reg))
145 unsigned Reg = MO.getReg(); local
146 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
150 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
164 unsigned Reg = MO.getReg(); local
165 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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/external/llvm/include/llvm/MC/
H A DMCWin64EH.h28 static WinEH::Instruction PushNonVol(MCSymbol *L, unsigned Reg) { argument
29 return WinEH::Instruction(Win64EH::UOP_PushNonVol, L, Reg, -1);
38 static WinEH::Instruction SaveNonVol(MCSymbol *L, unsigned Reg, argument
42 L, Reg, Offset);
44 static WinEH::Instruction SaveXMM(MCSymbol *L, unsigned Reg, argument
48 L, Reg, Offset);
50 static WinEH::Instruction SetFPReg(MCSymbol *L, unsigned Reg, unsigned Off) { argument
51 return WinEH::Instruction(UOP_SetFPReg, L, Reg, Off);
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.h55 unsigned getFirstReg(unsigned Reg);
58 inline unsigned getRegAsGR64(unsigned Reg) { argument
59 return GR64Regs[getFirstReg(Reg)];
63 inline unsigned getRegAsGR32(unsigned Reg) { argument
64 return GR32Regs[getFirstReg(Reg)];
68 inline unsigned getRegAsGRH32(unsigned Reg) { argument
69 return GRH32Regs[getFirstReg(Reg)];
/external/llvm/include/llvm/CodeGen/
H A DLiveVariables.h106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
110 unsigned Reg,
150 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
285 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
303 isPHIJoin(unsigned Reg) argument
306 setPHIJoin(unsigned Reg) argument
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H A DLiveIntervalAnalysis.h110 LiveInterval &getInterval(unsigned Reg) { argument
111 if (hasInterval(Reg))
112 return *VirtRegIntervals[Reg];
114 return createAndComputeVirtRegInterval(Reg);
117 const LiveInterval &getInterval(unsigned Reg) const {
118 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
121 bool hasInterval(unsigned Reg) const {
122 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
126 LiveInterval &createEmptyInterval(unsigned Reg) { argument
133 createAndComputeVirtRegInterval(unsigned Reg) argument
140 removeInterval(unsigned Reg) argument
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H A DMachineRegisterInfo.h37 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
95 return MO->Contents.Reg.Next;
215 /// Verify the sanity of the use list for Reg.
216 void verifyUseList(unsigned Reg) const;
248 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
249 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
264 reg_instructions(unsigned Reg) const {
265 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
280 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
281 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
679 setPhysRegUsed(unsigned Reg) argument
693 setPhysRegUnused(unsigned Reg) argument
766 addLiveIn(unsigned Reg, unsigned vreg = 0) argument
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H A DStackMaps.h138 unsigned Reg; member in struct:llvm::StackMaps::Location
140 Location() : LocType(Unprocessed), Size(0), Reg(0), Offset(0) {}
141 Location(LocationType LocType, unsigned Size, unsigned Reg, int64_t Offset) argument
142 : LocType(LocType), Size(Size), Reg(Reg), Offset(Offset) {}
146 unsigned short Reg; member in struct:llvm::StackMaps::LiveOutReg
150 LiveOutReg() : Reg(0), RegNo(0), Size(0) {}
151 LiveOutReg(unsigned short Reg, unsigned short RegNo, unsigned short Size) argument
152 : Reg(Reg), RegN
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H A DLivePhysRegs.h74 void addReg(unsigned Reg) { argument
76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
84 void removeReg(unsigned Reg) { argument
86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
90 for (MCSuperRegIterator SuperRegs(Reg, TRI, /*IncludeSelf=*/false);
98 /// \brief Returns true if register @p Reg is contained in the set. This also
99 /// works if only the super register of @p Reg has been defined, because we
101 bool contains(unsigned Reg) cons
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H A DFunctionLoweringInfo.h164 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { argument
165 if (!LiveOutRegInfo.inBounds(Reg))
168 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
180 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
183 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, argument
189 LiveOutRegInfo.grow(Reg);
190 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
208 unsigned Reg = It->second; local
209 if (Reg == 0)
212 LiveOutRegInfo.grow(Reg);
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/external/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h37 void setLowSavedGPR(unsigned Reg) { LowSavedGPR = Reg; } argument
42 void setHighSavedGPR(unsigned Reg) { HighSavedGPR = Reg; } argument
H A DSystemZShortenInst.cpp78 unsigned Reg = MI.getOperand(0).getReg(); local
79 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
80 unsigned GPRs = GPRMap[Reg];
88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
110 unsigned Reg = *LI;
111 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
112 LiveLow |= LowGPRs[Reg];
113 LiveHigh |= HighGPRs[Reg];
133 if (unsigned Reg
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/external/llvm/lib/Target/R600/
H A DR600RegisterInfo.h34 unsigned getHWRegIndex(unsigned Reg) const override;
43 // \returns true if \p Reg can be defined in one ALU caluse and used in another.
44 bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
H A DSIFixSGPRCopies.cpp90 unsigned Reg,
94 unsigned Reg,
131 /// This functions walks the use list of Reg until it finds an Instruction
137 unsigned Reg,
141 = TargetRegisterInfo::isVirtualRegister(Reg) ?
142 MRI.getRegClass(Reg) :
143 TRI->getRegClass(Reg);
147 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
163 unsigned Reg,
165 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
134 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
160 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument
229 unsigned Reg = Op.getReg(); local
235 unsigned Reg = MI.getOperand(0).getReg(); local
284 unsigned Reg = MI.getOperand(i).getReg(); local
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/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
/external/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
90 unsigned Reg = MI->getOperand(1).getReg(); local
91 if (TargetRegisterInfo::isPhysicalRegister(Reg))
95 MachineInstr *DefMI = MRI->getVRegDef(Reg);
100 Reg = DefMI->getOperand(1).getReg();
101 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
102 DefMI = MRI->getVRegDef(Reg);
106 Reg = DefMI->getOperand(2).getReg();
107 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
108 DefMI = MRI->getVRegDef(Reg);
118 unsigned Reg = MI->getOperand(0).getReg(); local
144 unsigned Reg = MI->getOperand(1).getReg(); local
185 hasRAWHazard(unsigned Reg, MachineInstr *MI) const argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h27 unsigned Reg = 0; local
30 Reg = PPC::CR0;
33 Reg = PPC::CR1;
36 Reg = PPC::CR2;
39 Reg = PPC::CR3;
42 Reg = PPC::CR4;
45 Reg = PPC::CR5;
48 Reg = PPC::CR6;
51 Reg = PPC::CR7;
53 assert(Reg !
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