| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPURegisterInfo.cpp | 46 static const unsigned SubRegs[] = { local
53 assert(Channel < array_lengthof(SubRegs));
54 return SubRegs[Channel];
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | LivePhysRegs.h | 77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
78 SubRegs.isValid(); ++SubRegs)
79 LiveRegs.insert(*SubRegs);
87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
88 SubRegs.isValid(); ++SubRegs)
89 LiveRegs.erase(*SubRegs);
|
| /external/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
198 unsigned SubReg = *SubRegs;
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
221 SubRegs.isValid(); ++SubRegs)
222 PartDefRegs.insert(*SubRegs);
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs
[all...] |
| H A D | MachineVerifier.cpp | 94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95 RV.push_back(*SubRegs);
453 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
455 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
456 regsReserved.set(*SubRegs);
679 for (MCSubRegIterator SubRegs(*
[all...] |
| H A D | CriticalAntiDepBreaker.cpp | 218 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
219 SubRegs.isValid(); ++SubRegs) {
220 KeepRegs.set(*SubRegs);
230 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
231 SubRegs.isValid(); ++SubRegs)
232 KeepRegs.set(*SubRegs);
|
| H A D | MachineInstrBundle.cpp | 175 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
176 unsigned SubReg = *SubRegs;
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| H A D | ScheduleDAGInstrs.cpp | 1084 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1085 SubRegs.isValid(); ++SubRegs)
1086 LiveRegs.set(*SubRegs);
1110 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1111 if (LiveRegs.test(*SubRegs)) {
1112 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1154 for (MCSubRegIterator SubRegs(Re
[all...] |
| H A D | RegisterScavenging.cpp | 218 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
219 if (isRegUsed(*SubRegs)) {
|
| H A D | AggressiveAntiDepBreaker.cpp | 245 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
246 SubRegs.isValid(); ++SubRegs)
247 PassthruRegs.insert(*SubRegs);
319 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
320 unsigned SubregReg = *SubRegs;
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| H A D | BranchFolding.cpp | 153 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
154 SubRegs.isValid(); ++SubRegs)
155 ImpDefRegs.insert(*SubRegs);
1700 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
1701 Uses.erase(*SubRegs); // Use sub-registers to be conservative
|
| H A D | IfConversion.cpp | 1440 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1441 SubRegs.isValid(); ++SubRegs)
1442 ExtUses.insert(*SubRegs);
1449 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1450 SubRegs.isValid(); ++SubRegs)
1451 RedefsByFalse.insert(*SubRegs);
|
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
123 "SubRegs and SubRegIndices must have the same size");
204 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
218 return SubRegs;
227 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
247 if (!SubRegs.insert(*SI).second)
260 CodeGenRegister *SR = SubRegs[Idx];
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
275 SubRegs
545 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); variable
1771 const SubRegMap &SubRegs = Register.getSubRegs(); local
[all...] |
| H A D | CodeGenRegisters.h | 159 return SubRegs;
252 SubRegMap SubRegs; member in struct:llvm::CodeGenRegister
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 401 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
402 LastDef[*SubRegs] = MI;
|
| /external/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 99 /// register. The SubRegs field is a zero terminated array of registers that
107 uint32_t SubRegs; // Sub-register set, described above member in struct:llvm::MCRegisterDesc
111 // sub-register in SubRegs.
458 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 776 unsigned SubRegs = 0; local
783 SubRegs = 2;
787 SubRegs = 4;
792 SubRegs = 2;
796 SubRegs = 3;
800 SubRegs = 4;
804 SubRegs = 2;
808 SubRegs = 2;
813 SubRegs = 3;
818 SubRegs
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 136 const unsigned SubRegs[]);
900 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, local
903 return createTuple(Regs, RegClassIDs, SubRegs);
909 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, local
912 return createTuple(Regs, RegClassIDs, SubRegs);
917 const unsigned SubRegs[]) {
936 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
915 createTuple(ArrayRef<SDValue> Regs, const unsigned RegClassIDs[], const unsigned SubRegs[]) argument
|