Searched refs:TCL_UCP_VERT_BLEND_CTL (Results 1 - 7 of 7) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_state.c326 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
329 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
332 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
335 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
404 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
431 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
433 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
446 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_CULL_FRONT_IS_CCW;
454 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_CULL_FRONT_IS_CCW;
1058 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |
[all...]
H A Dradeon_context.h174 #define TCL_UCP_VERT_BLEND_CTL 5 macro
H A Dradeon_state_init.c855 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_state.c391 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
394 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR;
405 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP;
410 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2;
496 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
523 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
525 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
538 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_CULL_FRONT_IS_CCW;
546 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_CULL_FRONT_IS_CCW;
1757 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |
[all...]
H A Dr200_context.h260 #define TCL_UCP_VERT_BLEND_CTL 8 macro
H A Dr200_vertprog.c1149 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (ctx->Transform.ClipPlanesEnabled << 2);
1152 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(0xfc);
H A Dr200_state_init.c1192 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =

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