/external/pcre/dist/sljit/ |
H A D | sljitNativeSPARC_32.c | 48 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 55 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 68 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 78 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 82 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 85 FAIL_IF(push_inst(compiler, OR | D(TMP_REG1) | S1(0) | S2(src2), DR(TMP_REG1))); 91 FAIL_IF(push_inst(compiler, SUB | SET_FLAGS | D(0) | S1(TMP_REG1) | S2(0), SET_FLAGS)); 92 FAIL_IF(push_inst(compiler, SLL | D(TMP_REG1) | S1(TMP_REG1) | IM [all...] |
H A D | sljitNativeX86_common.c | 67 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) macro 83 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) macro 660 inst = emit_x86_instruction(compiler, 1, TMP_REG1, 0, src, srcw); 707 inst = emit_x86_instruction(compiler, 1, TMP_REG1, 0, src, srcw); 710 inst = emit_x86_instruction(compiler, 1, TMP_REG1, 0, dst, dstw); 752 && reg_map[TMP_REG1] > 7, 758 && reg_map[TMP_REG1] == 2, 767 EMIT_MOV(compiler, TMP_REG1, 0, SLJIT_R1, 0); 770 inst = emit_x86_instruction(compiler, 1, TMP_REG1, 0, TMP_REG1, [all...] |
H A D | sljitNativeARM_64.c | 37 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) macro 518 /* dst must be register, TMP_REG1 519 arg1 must be register, TMP_REG1, imm 533 FAIL_IF(load_immediate(compiler, TMP_REG1, arg1)); 534 arg1 = TMP_REG1; 552 SLJIT_ASSERT(!(flags & SET_FLAGS) && (flags & ARG2_IMM) && arg1 == TMP_REG1); 655 FAIL_IF(load_immediate(compiler, TMP_REG1, arg1)); 656 arg1 = TMP_REG1; 667 SLJIT_ASSERT(!(flags & SET_FLAGS) && arg1 == TMP_REG1); 673 SLJIT_ASSERT(!(flags & SET_FLAGS) && arg1 == TMP_REG1); [all...] |
H A D | sljitNativeSPARC_common.c | 86 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) macro 444 FAIL_IF(load_immediate(compiler, TMP_REG1, -local_size)); 445 FAIL_IF(push_inst(compiler, SAVE | D(SLJIT_SP) | S1(SLJIT_SP) | S2(TMP_REG1), UNMOVABLE_INS)); 595 arg2 = TMP_REG1; 616 arg2 = TMP_REG1; 652 /* arg1 goes to TMP_REG1 or src reg 655 result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. */ 676 else if ((dst & SLJIT_MEM) && !getput_arg_fast(compiler, flags | ARG_TEST, TMP_REG1, dst, dstw)) 705 FAIL_IF(load_immediate(compiler, TMP_REG1, src1w)); 706 src1_r = TMP_REG1; [all...] |
H A D | sljitNativeMIPS_64.c | 168 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 175 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 189 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 207 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 211 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 219 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 231 FAIL_IF(push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src2) | TA(0) | D(TMP_REG1), DR(TMP_REG1))); 233 FAIL_IF(push_inst(compiler, BEQ | S(TMP_REG1) | TA(0) | IMM(5), UNMOVABLE_INS)); 238 FAIL_IF(push_inst(compiler, BGEZ | S(TMP_REG1) | IM [all...] |
H A D | sljitNativeARM_T2_32.c | 36 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) macro 513 /* dst must be register, TMP_REG1 514 arg1 must be register, TMP_REG1, imm 522 FAIL_IF(load_immediate(compiler, TMP_REG1, arg1)); 523 arg1 = TMP_REG1; 536 SLJIT_ASSERT(!(flags & SET_FLAGS) && (flags & ARG2_IMM) && arg1 == TMP_REG1); 672 FAIL_IF(load_immediate(compiler, TMP_REG1, arg1)); 673 arg1 = TMP_REG1; 687 SLJIT_ASSERT(!(flags & SET_FLAGS) && arg1 == TMP_REG1); 693 SLJIT_ASSERT(!(flags & SET_FLAGS) && arg1 == TMP_REG1); [all...] |
H A D | sljitNativeMIPS_32.c | 77 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 84 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 102 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 119 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 127 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 139 FAIL_IF(push_inst(compiler, ADDU | S(src2) | TA(0) | D(TMP_REG1), DR(TMP_REG1))); 141 FAIL_IF(push_inst(compiler, BEQ | S(TMP_REG1) | TA(0) | IMM(5), UNMOVABLE_INS)); 146 FAIL_IF(push_inst(compiler, BGEZ | S(TMP_REG1) | IMM(-2), UNMOVABLE_INS)); 147 FAIL_IF(push_inst(compiler, SLL | T(TMP_REG1) | [all...] |
H A D | sljitNativeMIPS_common.c | 47 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) macro 574 FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size)); 576 FAIL_IF(push_inst(compiler, SUBU_W | S(SLJIT_SP) | T(TMP_REG1) | D(SLJIT_SP), DR(SLJIT_SP))); 643 FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size)); 644 FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | T(TMP_REG1) | D(TMP_REG1), DR(TMP_REG1))); 645 base = S(TMP_REG1); 670 return push_inst(compiler, ADDU_W | S(TMP_REG1) | TA(0) | D(SLJIT_SP), UNMOVABLE_INS); 771 tmp_ar = DR(TMP_REG1); [all...] |
H A D | sljitNativePPC_common.c | 90 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) macro 969 tmp_r = ((inp_flags & LOAD_DATA) && ((inp_flags) & MEM_MASK) <= GPR_REG) ? reg : TMP_REG1; 972 tmp_r = TMP_REG1; 1137 /* arg1 goes to TMP_REG1 or src reg 1140 result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. */ 1182 FAIL_IF(load_immediate(compiler, TMP_REG1, src1w)); 1183 src1_r = TMP_REG1; 1185 else if (getput_arg_fast(compiler, input_flags | LOAD_DATA, TMP_REG1, src1, src1w)) { 1187 src1_r = TMP_REG1; 1215 FAIL_IF(getput_arg(compiler, input_flags | LOAD_DATA, TMP_REG1, src [all...] |
H A D | sljitNativeARM_32.c | 39 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2) macro 263 return push_inst(compiler, BLX | RM(TMP_REG1)); 484 inst[1] = BLX | RM(TMP_REG1); 991 SLJIT_ASSERT(src1 == TMP_REG1); \ 1006 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & ARGS_SWAPPED)); 1019 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & ARGS_SWAPPED)); 1040 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & ARGS_SWAPPED)); 1107 SLJIT_ASSERT(dst != TMP_REG1); 1108 FAIL_IF(push_inst(compiler, EMIT_DATA_PROCESS_INS(MOV_DP, 0, TMP_REG1, SLJIT_UNUSED, reg_map[src2]))); 1109 FAIL_IF(push_inst(compiler, mul_inst | (reg_map[src2] << 8) | reg_map[TMP_REG1])); [all...] |
H A D | sljitNativePPC_32.c | 52 SLJIT_ASSERT(src1 == TMP_REG1); 59 SLJIT_ASSERT(src1 == TMP_REG1); 74 SLJIT_ASSERT(src1 == TMP_REG1); 86 SLJIT_ASSERT(src1 == TMP_REG1); 90 SLJIT_ASSERT(src1 == TMP_REG1); 94 SLJIT_ASSERT(src1 == TMP_REG1);
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H A D | sljitNativePPC_64.c | 133 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \ 134 src1 = TMP_REG1; \ 144 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \ 145 src1 = TMP_REG1; \ 154 SLJIT_ASSERT(src1 == TMP_REG1); 161 SLJIT_ASSERT(src1 == TMP_REG1); 174 SLJIT_ASSERT(src1 == TMP_REG1); 189 SLJIT_ASSERT(src1 == TMP_REG1); 201 SLJIT_ASSERT(src1 == TMP_REG1); 206 SLJIT_ASSERT(src1 == TMP_REG1); [all...] |
H A D | sljitNativeX86_32.c | 97 PUSH_REG(reg_map[TMP_REG1]); 101 *inst++ = MOD_REG | (reg_map[TMP_REG1] << 3) | 0x4 /* esp */; 129 *inst++ = MOD_DISP8 | (reg_map[SLJIT_S0] << 3) | reg_map[TMP_REG1]; 134 *inst++ = MOD_DISP8 | (reg_map[SLJIT_S1] << 3) | reg_map[TMP_REG1]; 139 *inst++ = MOD_DISP8 | (reg_map[SLJIT_S2] << 3) | reg_map[TMP_REG1]; 235 POP_REG(reg_map[TMP_REG1]); 470 dst = TMP_REG1;
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H A D | sljitNativeTILEGX_64.c | 46 #define TMP_REG1 (SLJIT_NO_REGISTERS + 1) macro 1412 SLJIT_ASSERT(!(flags & LOAD_DATA) && reg_map[TMP_REG1] != reg_ar); 1643 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 1650 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 1663 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 1676 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 1688 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 1697 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 1996 /* arg1 goes to TMP_REG1 or src reg. 1999 result goes to TMP_REG2, so put result can use TMP_REG1 an [all...] |
H A D | sljitNativeX86_64.c | 615 dst = TMP_REG1; 651 FAIL_IF(emit_load_imm64(compiler, TMP_REG1, srcw)); 652 src = TMP_REG1; 735 dst_r = FAST_IS_REG(dst) ? dst : TMP_REG1;
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