/external/llvm/include/llvm/CodeGen/ |
H A D | LivePhysRegs.h | 44 const TargetRegisterInfo *TRI; member in class:llvm::LivePhysRegs 51 LivePhysRegs() : TRI(nullptr), LiveRegs() {} 54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) { argument 55 assert(TRI && "Invalid TargetRegisterInfo pointer."); 56 LiveRegs.setUniverse(TRI->getNumRegs()); 60 void init(const TargetRegisterInfo *TRI) { argument 61 assert(TRI && "Invalid TargetRegisterInfo pointer."); 62 this->TRI [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsOptionRecord.h | 45 const MCRegisterInfo *TRI = Context.getRegisterInfo(); local 46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); 47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); 48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); 49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); 50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); 51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); 52 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); 53 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
|
H A D | Mips16FrameLowering.h | 32 const TargetRegisterInfo *TRI) const override; 37 const TargetRegisterInfo *TRI) const override;
|
/external/llvm/lib/Target/R600/ |
H A D | SIFixSGPRCopies.cpp | 88 const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI, 92 const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI, 96 bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI, 118 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { argument 125 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 135 const SIRegisterInfo *TRI, 143 TRI->getRegClass(Reg); 145 RC = TRI->getSubRegClass(RC, SubReg); 150 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MR 134 inferRegClassFromUses( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument 160 inferRegClassFromDef( const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI, unsigned Reg, unsigned SubReg) const argument 178 isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI, const MachineRegisterInfo &MRI) const argument 204 const SIRegisterInfo *TRI = local [all...] |
H A D | R600ExpandSpecialInstrs.cpp | 71 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 179 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); 200 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 203 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; 206 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); 230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && 231 (TRI.getEncodingValue(Src1) & 0xff) < 127) 232 assert(TRI [all...] |
/external/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 33 : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {} 40 if (MF->getSubtarget().getRegisterInfo() != TRI) { 41 TRI = MF->getSubtarget().getRegisterInfo(); 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 43 unsigned NumPSets = TRI->getNumRegPressureSets(); 50 assert(TRI && "no register info set"); 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); 56 CSRNum.resize(TRI->getNumRegs(), 0); 58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 103 unsigned Cost = TRI [all...] |
H A D | AllocationOrder.cpp | 35 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); local 37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); 44 dbgs() << ' ' << PrintReg(Hints[I], TRI);
|
H A D | TargetRegisterInfo.cpp | 44 else if (TRI && Reg < TRI->getNumRegs()) 45 OS << '%' << TRI->getName(Reg); 49 if (TRI) 50 OS << ':' << TRI->getSubRegIndexName(SubIdx); 57 // Generic printout when TRI is missing. 58 if (!TRI) { 64 if (Unit >= TRI->getNumRegUnits()) { 70 MCRegUnitRootIterator Roots(Unit, TRI); 72 OS << TRI 162 firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI) argument 300 dumpReg(unsigned Reg, unsigned SubRegIndex, const TargetRegisterInfo *TRI) argument [all...] |
H A D | LiveRegMatrix.cpp | 51 TRI = MF.getSubtarget().getRegisterInfo(); 56 unsigned NumRegUnits = TRI->getNumRegUnits(); 76 bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, argument 79 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 100 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 101 << " to " << PrintReg(PhysReg, TRI) << ':'); 106 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, 108 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); 119 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) [all...] |
H A D | RegisterScavenging.cpp | 35 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) 66 TRI = MF.getSubtarget().getRegisterInfo(); 69 assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) && 79 NumRegUnits = TRI->getNumRegUnits(); 93 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) 116 for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) { 117 for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) { 218 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 224 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { 243 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MR [all...] |
H A D | AggressiveAntiDepBreaker.cpp | 118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), 123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); 133 dbgs() << " " << TRI->getName(r)); 143 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); 154 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 167 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 170 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 198 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 207 dbgs() << " " << TRI->getName(Reg) << "=g" << 245 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSel [all...] |
H A D | LiveStackAnalysis.cpp | 53 TRI = MF.getSubtarget().getRegisterInfo(); 72 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 86 OS << " [" << TRI->getRegClassName(RC) << "]\n";
|
H A D | RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI; member in class:llvm::CoalescerPair 61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
|
H A D | MachineCopyPropagation.cpp | 37 const TargetRegisterInfo *TRI; member in class:__anon10437::MachineCopyPropagation 70 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 79 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR) 115 const TargetRegisterInfo *TRI) { 119 if (TRI->isSubRegister(SrcSrc, Def)) { 121 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); 124 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); 164 isNopCopy(CopyMI, Def, Src, TRI)) { 184 I->clearRegisterKills(Def, TRI); 194 for (MCRegAliasIterator AI(Src, TRI, tru 114 isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, const TargetRegisterInfo *TRI) argument [all...] |
H A D | StackMapLivenessAnalysis.cpp | 53 const TargetRegisterInfo *TRI; member in class:__anon10504::StackMapLiveness 110 TRI = MF.getSubtarget().getRegisterInfo(); 128 LiveRegs.init(TRI); 162 uint32_t *Mask = MF->allocateRegisterMask(TRI->getNumRegs()); 167 TRI->adjustStackMapLiveOutMask(Mask);
|
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ExpandSpecialInstrs.cpp | 53 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); 106 Src0 = TRI.getSubReg(Src0, SubRegIndex); 107 Src1 = TRI.getSubReg(Src1, SubRegIndex); 110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]); 111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]); 112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); 119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); 120 DstReg = TRI [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DwarfExpression.h | 34 const TargetRegisterInfo &TRI; member in class:llvm::DwarfExpression 38 DwarfExpression(const TargetRegisterInfo &TRI, argument 40 : TRI(TRI), DwarfVersion(DwarfVersion) {} 110 DebugLocDwarfExpression(const TargetRegisterInfo &TRI, argument 112 : DwarfExpression(TRI, DwarfVersion), BS(BS) {}
|
H A D | DwarfExpression.cpp | 76 int DwarfReg = TRI.getDwarfRegNum(MachineReg, false); 87 if (!TRI.isPhysicalRegister(MachineReg)) 90 int Reg = TRI.getDwarfRegNum(MachineReg, false); 102 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { 103 Reg = TRI.getDwarfRegNum(*SR, false); 105 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); 106 unsigned Size = TRI.getSubRegIdxSize(Idx); 107 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); 131 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; 135 for (MCSubRegIterator SR(MachineReg, &TRI); S [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64PBQPRegAlloc.h | 26 const TargetRegisterInfo *TRI; member in class:llvm::A57ChainingConstraint
|
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.h | 36 const TargetRegisterInfo *TRI) const override; 40 const TargetRegisterInfo *TRI) const override;
|
H A D | Thumb1InstrInfo.h | 49 const TargetRegisterInfo *TRI) const override; 55 const TargetRegisterInfo *TRI) const override;
|
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.h | 32 const TargetRegisterInfo *TRI) const override; 43 const TargetRegisterInfo *TRI) const override;
|
H A D | HexagonFrameLowering.cpp | 212 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument 213 MCSuperRegIterator SRI(Reg, TRI); 226 const TargetRegisterInfo *TRI) const { 247 unsigned SuperReg = uniqueSuperReg(Reg, TRI); 252 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); 253 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); 260 CSI[i+1].getFrameIdx(), SuperRegClass, TRI); 266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 268 TRI); 280 const TargetRegisterInfo *TRI) cons [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.h | 40 const TargetRegisterInfo *TRI) const override; 44 const TargetRegisterInfo *TRI) const override;
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.h | 37 const TargetRegisterInfo *TRI) const override; 41 const TargetRegisterInfo *TRI) const override;
|