Searched refs:X86 (Results 1 - 25 of 64) sorted by relevance

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/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
54 " fuse, but the X86 backend currently can't"),
105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
110 { X86::ADC32ri, X86
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H A DX86RegisterInfo.cpp1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
12 // on X86.
58 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
61 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
77 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
78 FramePtr = Use64BitReg ? X86
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H A DX86FloatingPoint.cpp26 #include "X86.h"
79 const char *getPassName() const override { return "X86 FP Stackifier"; }
126 if (Reg < X86::FP0 || Reg > X86::FP6)
128 Mask |= 1 << (Reg - X86::FP0);
184 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
191 /// getSTReg - Return the X86::ST(i) register which contains the specified
194 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
223 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
232 BuildMI(*MBB, I, dl, TII->get(X86
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H A DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
322 if (Op0 == X86::AX && Op1 == X86::AL)
323 NewOpcode = X86
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H A DX86FixupLEAs.cpp15 #include "X86.h"
42 const char *getPassName() const override { return "X86 LEA Fixup"; }
102 case X86::MOV32rr:
103 case X86::MOV64rr: {
107 TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r
108 : X86::LEA64r))
118 case X86::ADD64ri32:
119 case X86::ADD64ri8:
120 case X86
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H A DX86FastISel.cpp1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
166 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
172 static std::pair<X86::CondCode, bool>
174 X86::CondCode CC = X86::COND_INVALID;
179 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
181 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
183 case CmpInst::FCMP_OGE: CC = X86
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H A DX86FrameLowering.cpp1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
91 return X86::SUB64ri8;
92 return X86::SUB64ri32;
95 return X86::SUB32ri8;
96 return X86::SUB32ri;
103 return X86::ADD64ri8;
104 return X86::ADD64ri32;
107 return X86::ADD32ri8;
108 return X86
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H A DX86MachineFunctionInfo.cpp1 //===-- X86MachineFuctionInfo.cpp - X86 machine function info -------------===//
28 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
H A DX86ISelDAGToDAG.cpp1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
15 #include "X86.h"
96 return RegNode->getReg() == X86::RIP;
145 /// ISel - X86 specific code to select X86 machine instructions for
162 return "X86 DAG->DAG Instruction Selection";
500 // late" legalization of these inline with the X86 isel pass.
605 if (!X86
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H A DX86CallFrameOptimization.cpp22 #include "X86.h"
93 const char *getPassName() const override { return "X86 Optimize Call Frame"; }
268 while (I->getOpcode() == X86::LEA32r)
289 if (Opcode != X86::MOV32mi && Opcode != X86::MOV32mr)
300 if (!I->getOperand(X86::AddrBaseReg).isReg() ||
301 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
302 !I->getOperand(X86::AddrScaleAmt).isImm() ||
303 (I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
304 (I->getOperand(X86
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H A DX86SelectionDAGInfo.cpp1 //===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
65 const unsigned ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
66 X86::ECX, X86::EAX, X86::EDI};
124 ValReg = X86::AX;
129 ValReg = X86::EAX;
134 ValReg = X86
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H A DMakefile1 ##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===##
12 TARGET = X86
/external/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp10 // This file is part of the X86 Disassembler.
59 namespace X86 { namespace in namespace:llvm
84 (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
85 case X86::Mode16Bit:
88 case X86::Mode32Bit:
91 case X86::Mode64Bit:
175 #define ENTRY(x) X86::x,
228 X86
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/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
35 cl::desc("Disable relaxation of arithmetic instruction for X86"));
50 case X86::reloc_riprel_4byte:
51 case X86::reloc_riprel_4byte_movq_load:
52 case X86::reloc_signed_4byte:
53 case X86::reloc_global_offset_table:
60 case X86::reloc_global_offset_table8:
89 return X86::NumTargetFixupKinds;
93 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
143 case X86
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H A DX86BaseInfo.h1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
11 // the X86 target useful for the compiler back-end and the MC libraries.
27 namespace X86 { namespace in namespace:llvm
44 } // end namespace X86;
53 // X86 Specific MachineOperand flags.
70 /// See the X86-64 ELF ABI supplement for more details.
77 /// See the X86-64 ELF ABI supplement for more details.
85 /// See the X86-64 ELF ABI supplement for more details.
92 /// See the X86-64 ELF ABI supplement for more details.
221 // Instruction encodings. These are the standard/most common forms for X86
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H A DX86FixupKinds.h1 //===-- X86FixupKinds.h - X86 Specific Fixup Entries ------------*- C++ -*-===//
16 namespace X86 { namespace in namespace:llvm
H A DX86WinCOFFObjectWriter.cpp1 //===-- X86WinCOFFObjectWriter.cpp - X86 Win COFF Writer ------------------===//
54 case X86::reloc_riprel_4byte:
55 case X86::reloc_riprel_4byte_movq_load:
58 case X86::reloc_signed_4byte:
74 case X86::reloc_riprel_4byte:
75 case X86::reloc_riprel_4byte_movq_load:
78 case X86::reloc_signed_4byte:
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp10 // This defines functionality used to emit comments about X86 instructions to
33 case X86::PMOVZXBWrm:
34 case X86::PMOVZXBWrr:
35 case X86::VPMOVZXBWrm:
36 case X86::VPMOVZXBWrr:
40 case X86::VPMOVZXBWYrm:
41 case X86::VPMOVZXBWYrr:
45 case X86::PMOVZXBDrm:
46 case X86::PMOVZXBDrr:
47 case X86
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H A DX86ATTInstPrinter.cpp59 if (MI->getOpcode() == X86::CALLpcrel32 &&
60 (STI.getFeatureBits() & X86::Mode64Bit) != 0) {
168 // Print X86 immediates as signed values.
187 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
188 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
189 const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
190 const MCOperand &SegReg = MI->getOperand(Op + X86::AddrSegmentReg);
196 printOperand(MI, Op + X86::AddrSegmentReg, O);
212 printOperand(MI, Op + X86::AddrBaseReg, O);
216 printOperand(MI, Op + X86
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/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.equinox.launcher.gtk.linux.x86_1.1.2.R36x_v20101019_1345/
H A Dlauncher.gtk.linux.x86.properties11 pluginName = Equinox Launcher Linux X86 Fragment
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.equinox.launcher.win32.win32.x86_1.1.2.R36x_v20101019_1345/
H A Dlauncher.win32.win32.x86.properties11 pluginName = Equinox Launcher Win32 X86 Fragment
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmInstrumentation.cpp1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
118 bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; }
158 if (Reg != X86::NoRegister)
168 static const MCPhysReg Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
169 X86::RCX, X86::RDX, X86
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H A DX86Operand.h1 //===-- X86Operand.h - Parsed X86 machine instruction --------------------===//
20 /// X86Operand - Instances of this class represent a parsed X86 machine
236 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
240 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
244 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
248 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86
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H A DX86AsmParser.cpp1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
732 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
736 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
740 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
744 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
748 (X86::Mode64Bit | X86::Mode32Bit | X86
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/external/llvm/host/include/llvm/Config/
H A DTargets.def28 LLVM_TARGET(X86)

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