| /external/llvm/test/MC/Sparc/ |
| H A D | sparc-vis.s | 3 ! CHECK: fzeros %f31 ! encoding: [0xbf,0xb0,0x0c,0x20]
4 fzeros %f31
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| /external/compiler-rt/lib/builtins/ppc/ |
| H A D | restFP.S | 17 // If the compiler wants to restore f27..f31, it does a "b restFP+52"
40 lfd f31,-8(r1)
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| H A D | saveFP.S | 15 // If the compiler wants to save f27..f31, it does a "bl saveFP+52"
38 stfd f31,-8(r1)
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| /external/llvm/test/MC/Mips/ |
| H A D | mips-reginfo-fp32.s | 33 # abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
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| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips32r2.s | 9 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips2-wrong-error.s | 14 sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| H A D | invalid-mips5-wrong-error.s | 22 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
34 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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| H A D | invalid-mips3-wrong-error.s | 20 sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| H A D | invalid-mips4-wrong-error.s | 22 sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/compiler-rt/test/cfi/ |
| H A D | utils.h | 46 virtual void f31() {} function in class:Deriver
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips5-wrong-error.s | 22 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
34 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| H A D | invalid-mips32r2.s | 26 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
49 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | invalid-mips5-wrong-error.s | 22 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
34 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips5-wrong-error.s | 22 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
34 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips5-wrong-error.s | 25 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/clang/test/CodeGen/ |
| H A D | arm-arguments.c | 160 void f31(struct s31 s) { } function
161 // AAPCS: @f31([1 x i32] %s.coerce)
165 // APCS-GNU: @f31([1 x i32] %s.coerce)
|
| H A D | x86_32-arguments-darwin.c | 132 // CHECK-LABEL: define float @f31()
133 struct s31 { char : 0; float b; char : 0; } f31(void) { while (1) {} } function
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| H A D | x86_64-arguments.c | 238 float f31(struct f31foo X) { function
239 // CHECK-LABEL: define float @f31(<2 x float> %X.coerce0, float %X.coerce1)
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| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 18 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/test/mjsunit/harmony/ |
| H A D | block-let-crankshaft.js | 35 f27, f28, f29, f30, f31, f32, f33];
258 function f31() { function
|
| /external/llvm/test/MC/ELF/ |
| H A D | cfi.s | 185 f31: label
|
| /external/llvm/test/MC/PowerPC/ |
| H A D | ppc64-regs.s | 71 #CHECK: .cfi_offset f31, 556
188 .cfi_offset f31,556
|
| /external/libunwind/tests/ |
| H A D | ia64-test-nat-asm.S | 385 .spillreg.p p6, r5, f31
386 (p6) setf.sig f31 = r5 // save r5 in f31 if it's a NaT
420 (p6) getf.sig r5 = f31
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| /external/libunwind/src/ia64/ |
| H A D | getcontext.S | 80 stf.spill [r9] = f31 // M2
|
| /external/mesa3d/src/mesa/sparc/ |
| H A D | sparc_matrix.h | 50 #define M15 %f31
|