Searched refs:r3 (Results 1 - 25 of 420) sorted by relevance

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/external/llvm/test/MC/ARM/
H A Darm-ldrd.s6 ldrd r1, r2, [r3, #4]
7 ldrd r1, r2, [r3], #4
8 ldrd r1, r2, [r3, #4]!
9 ldrd r1, r2, [r3, -r4]!
10 ldrd r1, r2, [r3, r4]
11 ldrd r1, r2, [r3], r4
20 ldrd r0, r3, [pc, #0]
21 ldrd r0, r3, [r4, #4]
22 ldrd r0, r3, [r4], #4
23 ldrd r0, r3, [r
[all...]
H A Darm-aliases.s5 add r1, r2, r3, lsl #0
6 sub r1, r2, r3, ror #0
7 eor r1, r2, r3, lsr #0
8 orr r1, r2, r3, asr #0
9 and r1, r2, r3, ror #0
10 bic r1, r2, r3, lsl #0
12 @ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
13 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
14 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
15 @ CHECK: orr r1, r2, r3
[all...]
H A Dmul-v4.s14 @ ARMV4: mla r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0xe0]
15 @ ARMV4: mlas r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0xe0]
16 @ ARMV4: mlane r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0x10]
17 @ ARMV4: mlaseq r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0x00]
18 mla r0, r1, r2, r3
19 mlas r0, r1, r2, r3
20 mlane r0, r1, r2, r3
21 mlaseq r0, r1, r2, r3
23 @ ARMV4: smlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xe3,0xe0]
24 @ ARMV4: smlals r2, r3, r
[all...]
H A Darm-arithmetic-aliases.s8 sub r2, r2, r3
9 sub r2, r3
13 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
14 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
18 add r2, r2, r3
19 add r2, r3
23 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
24 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
28 and r2, r2, r3
29 and r2, r3
[all...]
H A Darm_instructions.s22 @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
23 and r1,r2,r3
25 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
26 ands r1,r2,r3
28 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
29 eor r1,r2,r3
31 @ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
32 eors r1,r2,r3
34 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
35 sub r1,r2,r3
[all...]
H A Dthumb.s18 rev r2, r3
19 rev16 r3, r4
21 @ CHECK: rev r2, r3 @ encoding: [0x1a,0xba]
22 @ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba]
25 sxtb r2, r3
26 sxth r2, r3
27 @ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]
28 @ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]
33 uxtb r3, r6
34 uxth r3, r
[all...]
H A Didiv.s13 sdiv r1, r2, r3
14 udiv r3, r4, r5
15 @ A15-ARM: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
16 @ A15-ARM: udiv r3, r4, r5 @ encoding: [0x14,0xf5,0x33,0xe7]
17 @ A15-THUMB: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
18 @ A15-THUMB: udiv r3, r4, r5 @ encoding: [0xb4,0xfb,0xf5,0xf3]
20 @ A15-ARM-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
21 @ A15-ARM-NOTHUMBHWDIV: udiv r3, r4, r5 @ encoding: [0x14,0xf5,0x33,0xe7]
22 @ A15-THUMB-NOARMHWDIV: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
23 @ A15-THUMB-NOARMHWDIV: udiv r3, r
[all...]
/external/v8/test/mjsunit/regress/
H A Dregress-crbug-178790.js47 var r3 = "a"; variable
49 r3 = "(" + r3 + ")a";
51 "test".match(RegExp(r3));
/external/valgrind/none/tests/arm/
H A Dv6intThumb.c711 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
712 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
713 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
714 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
715 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c
[all...]
H A Dv6intThumb.stdout.exp2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
11 cmp r3, r
[all...]
H A Dv6intARM.c425 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
426 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
427 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
428 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
429 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3,
[all...]
/external/compiler-rt/lib/builtins/arm/
H A Dudivmodsi4.S38 mov r3, r0
39 udiv r0, r3, r1
40 mls r1, r0, r1, r3
62 * that (r0 << shift) < 2 * r1. The quotient is stored in r3.
67 clz r3, r1
68 /* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
69 sub r3, r3, ip
72 sub ip, ip, r3, lsl #1
76 sub ip, ip, r3, ls
[all...]
H A Dudivsi3.S62 * that (r0 << shift) < 2 * r1. The quotient is stored in r3.
67 clz r3, r1
68 /* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
69 sub r3, r3, ip
72 sub ip, ip, r3, lsl #1
76 sub ip, ip, r3, lsl #2
77 sub ip, ip, r3, lsl #3
78 mov r3, #0
87 lsr r3, r
[all...]
H A Dcomparesf2.S48 mov r3, r1, lsl #1
52 // flag if both a and b are zero (of either sign). The shift of r3 doesn't
55 orrs r12, r2, r3, lsr #1
67 subspl r0, r2, r3
100 cmpls r3, #0xff000000
115 mov r3, r1, lsl #1
116 orrs r12, r2, r3, lsr #1
120 subspl r0, r2, r3
129 cmpls r3, #0xff000000
139 mov r3, r
[all...]
H A Dumodsi3.S60 * that (r0 << shift) < 2 * r1. The quotient is stored in r3.
65 clz r3, r1
66 /* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
67 sub r3, r3, ip
70 sub ip, ip, r3, lsl #1
74 sub ip, ip, r3, lsl #3
83 lsr r3, r2, #16
84 cmp r3, r1
85 movhs r2, r3
[all...]
/external/boringssl/src/crypto/chacha/
H A Dchacha_vec_arm.S65 mov r8, r3
81 ldmia r4, {r0, r1, r2, r3}
90 stmia r4, {r0, r1, r2, r3}
95 ldr r3, [r7, #84]
102 vldr d24, [r3, #64]
103 vldr d25, [r3, #72]
104 ldr r3, [lr, #12] @ unaligned
106 stmia r5!, {r0, r1, r2, r3}
114 ldr r3, [lr, #12] @ unaligned
116 stmia r6!, {r0, r1, r2, r3}
[all...]
/external/libhevc/common/arm/
H A Dihevc_intra_pred_chroma_horz.s85 @r3 => dst_strd
127 vst1.16 {q1},[r2],r3 @store in 1st row 0-16 columns
128 vst1.16 {q1},[r9],r3 @store in 1st row 16-32 columns
131 vst1.16 {q2},[r2],r3
132 vst1.16 {q2},[r9],r3
135 vst1.16 {q3},[r2],r3
136 vst1.16 {q3},[r9],r3
139 vst1.16 {q4},[r2],r3
140 vst1.16 {q4},[r9],r3
143 vst1.16 {q1},[r2],r3
[all...]
H A Dihevc_intra_pred_luma_horz.s85 @r3 => dst_strd
125 vst1.8 {q1},[r2],r3 @store in 1st row 0-16 columns
126 vst1.8 {q1},[r9],r3 @store in 1st row 16-32 columns
129 vst1.8 {q2},[r2],r3
130 vst1.8 {q2},[r9],r3
133 vst1.8 {q3},[r2],r3
134 vst1.8 {q3},[r9],r3
137 vst1.8 {q4},[r2],r3
138 vst1.8 {q4},[r9],r3
141 vst1.8 {q1},[r2],r3
[all...]
H A Dihevc_deblk_chroma_vert.s62 add r2,r2,r3
72 adds r3,r7,r2,asr #1
80 cmp r3,#0x39
81 ldrle r3,[r7,r3,lsl #2]
82 subgt r3,r3,#6
93 add r3,r3,r5,lsl #1
95 add r6,r3,#
[all...]
H A Dihevc_intra_pred_luma_mode_18_34.s88 @r3 => dst_strd
157 vst1.8 {d0},[r10],r3
158 vst1.8 {d1},[r10],r3
160 vst1.8 {d2},[r10],r3
162 vst1.8 {d3},[r10],r3
165 vst1.8 {d4},[r10],r3
167 vst1.8 {d5},[r10],r3
169 vst1.8 {d6},[r10],r3
171 vst1.8 {d7},[r10],r3
195 vst1.8 {d0},[r10],r3
[all...]
/external/libcxxabi/src/Unwind/
H A DUnwindRegistersRestore.S103 ; thread_state pointer is in r3
109 lwz r2, 16(r3)
110 ; skip r3 for now
113 lwz r6, 32(r3)
114 lwz r7, 36(r3)
115 lwz r8, 40(r3)
116 lwz r9, 44(r3)
117 lwz r10, 48(r3)
118 lwz r11, 52(r3)
119 lwz r12, 56(r3)
[all...]
H A DUnwindRegistersSave.S96 ; thread_state pointer is in r3
99 stw r0, 8(r3)
101 stw r0, 0(r3) ; store lr as ssr0
102 stw r1, 12(r3)
103 stw r2, 16(r3)
104 stw r3, 20(r3)
105 stw r4, 24(r3)
106 stw r5, 28(r3)
107 stw r6, 32(r3)
[all...]
/external/valgrind/none/tests/ppc32/
H A Dtest_tm.c3 int __attribute__ ((noinline)) htm_begin (int r3, int r4) argument
8 ret = r3;
/external/valgrind/none/tests/ppc64/
H A Dtest_tm.c3 int __attribute__ ((noinline)) htm_begin (int r3, int r4) argument
8 ret = r3;
/external/libmpeg2/common/arm/
H A Dimpeg2_format_conv.s144 vst1.8 {q0}, [r3]!
157 sub r3, r3, r6
160 vst1.8 {q0}, [r3]!
164 add r3, r3, r8
170 ldr r3, [sp, #24] @// Load pu1_dest_uv from stack
187 ldr r3, [sp, #24] @// Load pu1_dest_uv from stack
197 vst2.8 {d0, d1}, [r3]!
211 sub r3, r
[all...]

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