Searched refs:v1i64 (Results 1 - 12 of 12) sorted by relevance
/external/clang/test/CodeGen/ |
H A D | const-init.c | 137 typedef long long v1i64 __attribute((vector_size(8))); typedef 143 static v1i64 a = (v1i64)10LL;
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H A D | systemz-abi-vector.c | 18 typedef __attribute__((vector_size(8))) long long v1i64; typedef 72 v1i64 pass_v1i64(v1i64 arg) { return arg; }
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H A D | x86_64-arguments.c | 257 typedef unsigned long long v1i64 __attribute__((__vector_size__(8))); typedef 261 v1i64 f34(v1i64 arg) { return arg; }
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineValueType.h | 84 v1i64 = 37, // 1 x i64 enumerator in enum:llvm::MVT::SimpleValueType 218 SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 || 308 case v1i64: 370 case v1i64: 418 case v1i64: 559 if (NumElements == 1) return MVT::v1i64;
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 2270 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2288 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2306 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2324 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2342 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2360 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2378 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2396 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2414 else if (VT == MVT::v1i64 || VT == MVT::v1f64) 2428 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || V [all...] |
H A D | AArch64ISelLowering.cpp | 108 addDRTypeForNEON(MVT::v1i64); 546 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); 547 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand); 548 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); 549 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); 552 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 6063 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16) 6097 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16) 7367 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
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/external/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 155 case MVT::v1i64: return "v1i64"; 223 case MVT::v1i64: return VectorType::get(Type::getInt64Ty(Context), 1);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 407 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, 408 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, 409 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, 410 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
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H A D | ARMISelLowering.cpp | 434 addDRTypeForNEON(MVT::v1i64); 515 // Neon does not support some operations on v1i64 and v2i64 types. 516 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 526 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 981 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 3884 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 3898 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, 3899 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 4606 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
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H A D | ARMISelDAGToDAG.cpp | 1797 case MVT::v1i64: OpcodeIndex = 3; break; 1841 // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so 1934 case MVT::v1i64: OpcodeIndex = 3; break; 1992 // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
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/external/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 97 case MVT::v1i64: return "MVT::v1i64";
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 766 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) { 775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 1938 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 10737 if (OpVT == MVT::v1i64 && 10739 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 20515 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))). 20520 MMXSrcOp.getValueType() == MVT::v1i64 &&
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