Searched refs:v2i64 (Results 1 - 25 of 48) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
H A Dvpx_convolve_copy_msa.c25 out0 = __msa_copy_u_d((v2i64)src0, 0);
26 out1 = __msa_copy_u_d((v2i64)src1, 0);
27 out2 = __msa_copy_u_d((v2i64)src2, 0);
28 out3 = __msa_copy_u_d((v2i64)src3, 0);
29 out4 = __msa_copy_u_d((v2i64)src4, 0);
30 out5 = __msa_copy_u_d((v2i64)src5, 0);
31 out6 = __msa_copy_u_d((v2i64)src6, 0);
32 out7 = __msa_copy_u_d((v2i64)src7, 0);
42 out0 = __msa_copy_u_d((v2i64)src0, 0);
43 out1 = __msa_copy_u_d((v2i64)src
[all...]
H A Dloopfilter_4_msa.c35 p1_d = __msa_copy_u_d((v2i64)p1_out, 0);
36 p0_d = __msa_copy_u_d((v2i64)p0_out, 0);
37 q0_d = __msa_copy_u_d((v2i64)q0_out, 0);
38 q1_d = __msa_copy_u_d((v2i64)q1_out, 0);
57 thresh0 = (v16u8)__msa_ilvr_d((v2i64)thresh1, (v2i64)thresh0);
61 b_limit0 = (v16u8)__msa_ilvr_d((v2i64)b_limit1, (v2i64)b_limit0);
65 limit0 = (v16u8)__msa_ilvr_d((v2i64)limit1, (v2i64)limit
[all...]
H A Dloopfilter_8_msa.c40 flat = (v16u8)__msa_ilvr_d((v2i64)zero, (v2i64)flat);
43 p1_d = __msa_copy_u_d((v2i64)p1_out, 0);
44 p0_d = __msa_copy_u_d((v2i64)p0_out, 0);
45 q0_d = __msa_copy_u_d((v2i64)q0_out, 0);
46 q1_d = __msa_copy_u_d((v2i64)q1_out, 0);
69 p2_d = __msa_copy_u_d((v2i64)p2_out, 0);
70 p1_d = __msa_copy_u_d((v2i64)p1_out, 0);
71 p0_d = __msa_copy_u_d((v2i64)p0_out, 0);
72 q0_d = __msa_copy_u_d((v2i64)q0_ou
[all...]
H A Dmacros_msa.h381 out1 = (v8i16)__msa_ilvl_d((v2i64)out0, (v2i64)out0); \
382 out3 = (v8i16)__msa_ilvl_d((v2i64)out2, (v2i64)out2); \
533 out0_m = __msa_copy_u_d((v2i64)in, 0); \
548 out0_m = __msa_copy_u_d((v2i64)in, 0); \
549 out1_m = __msa_copy_u_d((v2i64)in, 1); \
571 out0_m = __msa_copy_u_d((v2i64)in0, 0); \
572 out1_m = __msa_copy_u_d((v2i64)in0, 1); \
573 out2_m = __msa_copy_u_d((v2i64)in
[all...]
H A Dloopfilter_16_msa.c458 flat = (v16u8)__msa_ilvr_d((v2i64)zero, (v2i64)flat);
461 p1_d = __msa_copy_u_d((v2i64)p1_out, 0);
462 p0_d = __msa_copy_u_d((v2i64)p0_out, 0);
463 q0_d = __msa_copy_u_d((v2i64)q0_out, 0);
464 q1_d = __msa_copy_u_d((v2i64)q1_out, 0);
495 p2_d = __msa_copy_u_d((v2i64)p2_out, 0);
496 p1_d = __msa_copy_u_d((v2i64)p1_out, 0);
497 p0_d = __msa_copy_u_d((v2i64)p0_out, 0);
498 q0_d = __msa_copy_u_d((v2i64)q0_ou
[all...]
H A Dvpx_convolve_avg_msa.c71 out0 = __msa_copy_u_d((v2i64)dst0, 0);
72 out1 = __msa_copy_u_d((v2i64)dst1, 0);
73 out2 = __msa_copy_u_d((v2i64)dst2, 0);
74 out3 = __msa_copy_u_d((v2i64)dst3, 0);
H A Dintrapred_msa.c221 val0 = __msa_copy_u_d((v2i64)store, 0);
238 data = (v16u8)__msa_insert_d((v2i64)data, 0, val0);
244 val0 = __msa_copy_u_d((v2i64)store, 0);
255 out = __msa_copy_u_d((v2i64)store, 0);
422 src_top = (v16i8)__msa_insert_d((v2i64)src_top, 0, val);
/external/libvpx/libvpx/vp8/common/mips/msa/
H A Dpostproc_msa.c88 out9 = (v16u8)__msa_ilvl_d((v2i64)out8, (v2i64)out8); \
89 out11 = (v16u8)__msa_ilvl_d((v2i64)out10, (v2i64)out10); \
90 out13 = (v16u8)__msa_ilvl_d((v2i64)out12, (v2i64)out12); \
91 out15 = (v16u8)__msa_ilvl_d((v2i64)out14, (v2i64)out14); \
92 out1 = (v16u8)__msa_ilvl_d((v2i64)out0, (v2i64)out
[all...]
H A Dvp8_macros_msa.h476 out0_m = __msa_copy_u_d((v2i64)in, 0); \
492 out0_m = __msa_copy_u_d((v2i64)in, 0); \
493 out1_m = __msa_copy_u_d((v2i64)in, 1); \
516 out0_m = __msa_copy_u_d((v2i64)in0, 0); \
517 out1_m = __msa_copy_u_d((v2i64)in0, 1); \
518 out2_m = __msa_copy_u_d((v2i64)in1, 0); \
519 out3_m = __msa_copy_u_d((v2i64)in1, 1); \
690 #define DOTP_SW2_SD(...) DOTP_SW2(v2i64, __VA_ARGS__)
754 out0 = (RTYPE)__msa_dpadd_s_d((v2i64)out0, (v4i32)mult0, (v4i32)mult0); \
755 out1 = (RTYPE)__msa_dpadd_s_d((v2i64)out
[all...]
H A Dloopfilter_filters_msa.c289 thresh0 = (v16u8)__msa_ilvr_d((v2i64)thresh1, (v2i64)thresh0);
293 b_limit0 = (v16u8)__msa_ilvr_d((v2i64)b_limit1, (v2i64)b_limit0);
297 limit0 = (v16u8)__msa_ilvr_d((v2i64)limit1, (v2i64)limit0);
330 thresh0 = (v16u8)__msa_ilvr_d((v2i64)thresh1, (v2i64)thresh0);
334 b_limit0 = (v16u8)__msa_ilvr_d((v2i64)b_limit1, (v2i64)b_limit
[all...]
H A Dreconintra_msa.c128 sum = (v2u64)__msa_srari_d((v2i64)sum, 3);
136 out = __msa_copy_u_d((v2i64)store, 0);
193 sum = (v2u64)__msa_srari_d((v2i64)sum, 4);
H A Didct_msa.c24 out1 = (v8i16)__msa_ilvl_d((v2i64)s6_m, (v2i64)s4_m); \
25 out3 = (v8i16)__msa_ilvl_d((v2i64)s7_m, (v2i64)s5_m); \
188 v2i64 zero = { 0 };
296 vec = (v8i16)__msa_pckev_d((v2i64)input_dc1, (v2i64)input_dc0);
/external/clang/test/CodeGen/
H A Dsystemz-abi-vector.c25 typedef __attribute__((vector_size(16))) long long v2i64; typedef
75 v2i64 pass_v2i64(v2i64 arg) { return arg; }
H A Dbuiltins-mips-msa.c8 typedef signed long long v2i64 __attribute__ ((vector_size(16))); typedef
27 v2i64 v2i64_a = (v2i64) {0, 1};
28 v2i64 v2i64_b = (v2i64) {1, 2};
29 v2i64 v2i64_r;
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp145 { ISD::SHL, MVT::v2i64, 1 },
146 { ISD::SRL, MVT::v2i64, 1 },
198 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
203 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
253 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
259 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
264 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
275 { ISD::SDIV, MVT::v2i64, 2*20 },
279 { ISD::UDIV, MVT::v2i64, 2*20 },
298 // A v4i64 multiply is custom lowered as two split v2i64 vector
[all...]
/external/libvpx/libvpx/vp8/encoder/mips/msa/
H A Dencodeopt_msa.c21 v2i64 err0 = { 0 };
22 v2i64 err1 = { 0 };
53 v2i64 err0, err1;
122 v2i64 err0, err1, err_dup0, err_dup1;
H A Ddenoising_msa.c45 v2i64 temp0_d, temp1_d;
62 adj_val = (v8i16)__msa_ilvev_d((v2i64)temp0_h, (v2i64)adj_val);
308 temp0_d += (v2i64)temp1_d;
364 v2i64 temp0_d, temp1_d;
418 adj_val = (v8i16)__msa_ilvev_d((v2i64)temp0_h, (v2i64)adj_val);
461 dst0 = __msa_copy_s_d((v2i64)running_avg_y, 0);
495 dst1 = __msa_copy_s_d((v2i64)running_avg_y, 0);
564 dst0 = __msa_copy_s_d((v2i64)running_avg_
[all...]
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h85 v2i64 = 38, // 2 x i64 enumerator in enum:llvm::MVT::SimpleValueType
226 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
309 case v2i64:
363 case v2i64:
429 case v2i64:
560 if (NumElements == 2) return MVT::v2i64;
/external/libvpx/libvpx/vp9/encoder/mips/msa/
H A Dvp9_error_msa.c22 v2i64 sq_coeff_r, sq_coeff_l; \
23 v2i64 err0, err_dup0, err1, err_dup1; \
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
197 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
202 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
205 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
225 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
228 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
230 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
231 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
234 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
388 // unaligned v2i64 store
[all...]
H A DAArch64ISelDAGToDAG.cpp502 case MVT::v2i64:
513 case MVT::v2i64:
2272 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2290 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2308 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2326 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2344 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2362 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2380 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2398 else if (VT == MVT::v2i64 || V
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp66 (int)MVT::v2i64
94 (int)MVT::v2i64
122 if (VT != MVT::i64 && VT != MVT::v2i64) {
175 setOperationAction(ISD::MULHU, MVT::v2i64, Expand);
177 setOperationAction(ISD::MULHS, MVT::v2i64, Expand);
178 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
182 setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand);
183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expan
[all...]
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp83 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
84 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
348 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
370 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
424 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
425 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
426 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
427 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
457 // the vectorized code. Because we have support for v2i64 but not i64 those
459 // To work around this we increase the cost of v2i64 operation
[all...]
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp62 DstVT = MVT::v2i64;
87 DstVT = MVT::v2i64;
100 DstVT = MVT::v2i64;
512 DecodeUNPCKHMask(MVT::v2i64, ShuffleMask);
601 DecodeUNPCKLMask(MVT::v2i64, ShuffleMask);
873 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
/external/llvm/lib/IR/
H A DValueTypes.cpp156 case MVT::v2i64: return "v2i64";
224 case MVT::v2i64: return VectorType::get(Type::getInt64Ty(Context), 2);

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