Searched refs:vex (Results 1 - 25 of 52) sorted by relevance

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/external/valgrind/coregrind/
H A Dm_debugger.c49 static Int ptrace_setregs(Int pid, const VexGuestArchState* vex) argument
54 regs.cs = vex->guest_CS;
55 regs.ss = vex->guest_SS;
56 regs.ds = vex->guest_DS;
57 regs.es = vex->guest_ES;
58 regs.fs = vex->guest_FS;
59 regs.gs = vex->guest_GS;
60 regs.eax = vex->guest_EAX;
61 regs.ebx = vex->guest_EBX;
62 regs.ecx = vex
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H A Dm_machine.c44 #define INSTR_PTR(regs) ((regs).vex.VG_INSTR_PTR)
45 #define STACK_PTR(regs) ((regs).vex.VG_STACK_PTR)
46 #define FRAME_PTR(regs) ((regs).vex.VG_FRAME_PTR)
69 regs->r_pc = (ULong)VG_(threads)[tid].arch.vex.guest_EIP;
70 regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_ESP;
72 = VG_(threads)[tid].arch.vex.guest_EBP;
74 regs->r_pc = VG_(threads)[tid].arch.vex.guest_RIP;
75 regs->r_sp = VG_(threads)[tid].arch.vex.guest_RSP;
77 = VG_(threads)[tid].arch.vex.guest_RBP;
79 regs->r_pc = (ULong)VG_(threads)[tid].arch.vex
193 VexGuestArchState* vex = &(VG_(get_ThreadState)(tid)->arch.vex); local
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/external/valgrind/coregrind/m_sigframe/
H A Dsigframe-tilegx-linux.c79 sc->gregs[0] = tst->arch.vex.guest_r0;
80 sc->gregs[1] = tst->arch.vex.guest_r1;
81 sc->gregs[2] = tst->arch.vex.guest_r2;
82 sc->gregs[3] = tst->arch.vex.guest_r3;
83 sc->gregs[4] = tst->arch.vex.guest_r4;
84 sc->gregs[5] = tst->arch.vex.guest_r5;
85 sc->gregs[6] = tst->arch.vex.guest_r6;
86 sc->gregs[7] = tst->arch.vex.guest_r7;
87 sc->gregs[8] = tst->arch.vex.guest_r8;
88 sc->gregs[9] = tst->arch.vex
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H A Dsigframe-mips32-linux.c86 sc->sc_regs[1] = tst->arch.vex.guest_r1;
87 sc->sc_regs[2] = tst->arch.vex.guest_r2;
88 sc->sc_regs[3] = tst->arch.vex.guest_r3;
89 sc->sc_regs[4] = tst->arch.vex.guest_r4;
90 sc->sc_regs[5] = tst->arch.vex.guest_r5;
91 sc->sc_regs[6] = tst->arch.vex.guest_r6;
92 sc->sc_regs[7] = tst->arch.vex.guest_r7;
93 sc->sc_regs[8] = tst->arch.vex.guest_r8;
94 sc->sc_regs[9] = tst->arch.vex.guest_r9;
95 sc->sc_regs[10] = tst->arch.vex
[all...]
H A Dsigframe-mips64-linux.c81 sc->sc_regs[1] = tst->arch.vex.guest_r1;
82 sc->sc_regs[2] = tst->arch.vex.guest_r2;
83 sc->sc_regs[3] = tst->arch.vex.guest_r3;
84 sc->sc_regs[4] = tst->arch.vex.guest_r4;
85 sc->sc_regs[5] = tst->arch.vex.guest_r5;
86 sc->sc_regs[6] = tst->arch.vex.guest_r6;
87 sc->sc_regs[7] = tst->arch.vex.guest_r7;
88 sc->sc_regs[8] = tst->arch.vex.guest_r8;
89 sc->sc_regs[9] = tst->arch.vex.guest_r9;
90 sc->sc_regs[10] = tst->arch.vex
[all...]
H A Dsigframe-s390x-linux.c65 do { zztst->arch.vex.guest_r##zzn = (unsigned long)(zzval); \
106 VexGuestS390XState vex; member in struct:vg_sigframe
147 sigregs->regs.gprs[0] = tst->arch.vex.guest_r0;
148 sigregs->regs.gprs[1] = tst->arch.vex.guest_r1;
149 sigregs->regs.gprs[2] = tst->arch.vex.guest_r2;
150 sigregs->regs.gprs[3] = tst->arch.vex.guest_r3;
151 sigregs->regs.gprs[4] = tst->arch.vex.guest_r4;
152 sigregs->regs.gprs[5] = tst->arch.vex.guest_r5;
153 sigregs->regs.gprs[6] = tst->arch.vex.guest_r6;
154 sigregs->regs.gprs[7] = tst->arch.vex
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H A Dsigframe-amd64-linux.c103 VexGuestAMD64State vex; member in struct:vg_sigframe
344 # define SC2(reg,REG) sc->reg = tst->arch.vex.guest_##REG
363 sc->eflags = LibVEX_GuestAMD64_get_rflags(&tst->arch.vex);
388 frame->vex = tst->arch.vex;
439 = (void*)tst->arch.vex.guest_RIP;
476 tst->arch.vex.guest_RIP = (Addr) handler;
477 tst->arch.vex.guest_RDI = (ULong) siginfo->si_signo;
478 tst->arch.vex.guest_RSI = (Addr) &frame->sigInfo;
479 tst->arch.vex
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H A Dsigframe-arm64-linux.c50 /* This uses the hack of dumping the vex guest state along with both
64 VexGuestARM64State vex; member in struct:vg_sig_private
96 # define SC2(reg) sc->regs[reg] = tst->arch.vex.guest_X##reg
106 sc->sp = tst->arch.vex.guest_XSP;
107 sc->pc = tst->arch.vex.guest_PC;
147 priv->vex = tst->arch.vex;
189 = (Addr*)(tst)->arch.vex.guest_PC;
196 tst->arch.vex.guest_X1 = (Addr)&rsf->info;
197 tst->arch.vex
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H A Dsigframe-ppc64-linux.c120 do { tst->arch.vex.guest_LR = (zzval); \
127 do { tst->arch.vex.guest_GPR##zzn = (zzval); \
181 *(Addr *)sp = tst->arch.vex.guest_GPR1;
188 faultaddr = tst->arch.vex.guest_CIA;
203 = tst->arch.vex.guest_GPR##gpr
210 frame->uc.uc_mcontext.gp_regs[VKI_PT_NIP] = tst->arch.vex.guest_CIA;
216 frame->uc.uc_mcontext.gp_regs[VKI_PT_ORIG_R3] = tst->arch.vex.guest_GPR3;
217 frame->uc.uc_mcontext.gp_regs[VKI_PT_CTR] = tst->arch.vex.guest_CTR;
218 frame->uc.uc_mcontext.gp_regs[VKI_PT_LNK] = tst->arch.vex.guest_LR;
220 &tst->arch.vex);
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H A Dsigframe-x86-linux.c108 VexGuestX86State vex; member in struct:vg_sigframe
367 # define SC2(reg,REG) sc->reg = tst->arch.vex.guest_##REG
384 sc->eflags = LibVEX_GuestX86_get_eflags(&tst->arch.vex);
407 frame->vex = tst->arch.vex;
522 = (void*)tst->arch.vex.guest_EIP;
562 tst->arch.vex.guest_EIP = (Addr) handler;
569 esp, tst->arch.vex.guest_EIP, tst->status);
598 tst->arch.vex = frame->vex;
[all...]
H A Dsigframe-arm-linux.c55 /* This uses the hack of dumping the vex guest state along with both
67 VexGuestARMState vex; member in struct:vg_sig_private
98 # define SC2(reg,REG) sc->arm_##reg = tst->arch.vex.guest_##REG
154 priv->vex = tst->arch.vex;
202 rsf->info._sifields._sigfault._addr = (Addr *) (tst)->arch.vex.guest_R12; /* IP */
209 tst->arch.vex.guest_R1 = (Addr)&rsf->info;
210 tst->arch.vex.guest_R2 = (Addr)&rsf->sig.uc;
220 tst->arch.vex.guest_R0 = sigNo;
223 tst->arch.vex
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H A Dsigframe-ppc32-linux.c122 do { tst->arch.vex.guest_LR = (zzval); \
129 do { tst->arch.vex.guest_GPR##zzn = (zzval); \
145 # define DO(gpr) mc->mc_gregs[VKI_PT_R0+gpr] = tst->arch.vex.guest_GPR##gpr
152 mc->mc_gregs[VKI_PT_NIP] = tst->arch.vex.guest_CIA;
154 mc->mc_gregs[VKI_PT_ORIG_R3] = tst->arch.vex.guest_GPR3;
155 mc->mc_gregs[VKI_PT_CTR] = tst->arch.vex.guest_CTR;
156 mc->mc_gregs[VKI_PT_LNK] = tst->arch.vex.guest_LR;
157 mc->mc_gregs[VKI_PT_XER] = LibVEX_GuestPPC32_get_XER(&tst->arch.vex);
158 mc->mc_gregs[VKI_PT_CCR] = LibVEX_GuestPPC32_get_CR(&tst->arch.vex);
212 //:: VexGuestPPC32State vex;
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H A Dsigframe-amd64-darwin.c56 and return. However .. for now .. just stick the vex guest state
127 frame->gst = tst->arch.vex;
154 tst->arch.vex.guest_RDI = (ULong) sigNo;
155 tst->arch.vex.guest_RSI = (Addr) &frame->fake_siginfo;/* oh well */
156 tst->arch.vex.guest_RDX = (Addr) &frame->fake_ucontext; /* oh well */
201 tst->arch.vex = frame->gst;
212 tid, tst->arch.vex.guest_RIP);
H A Dsigframe-x86-darwin.c56 and return. However .. for now .. just stick the vex guest state
130 frame->gst = tst->arch.vex;
201 tst->arch.vex = frame->gst;
212 tid, tst->arch.vex.guest_EIP);
/external/valgrind/coregrind/m_syswrap/
H A Dsyswrap-amd64-darwin.c67 VexGuestAMD64State *vex)
69 mach->__rax = vex->guest_RAX;
70 mach->__rbx = vex->guest_RBX;
71 mach->__rcx = vex->guest_RCX;
72 mach->__rdx = vex->guest_RDX;
73 mach->__rdi = vex->guest_RDI;
74 mach->__rsi = vex->guest_RSI;
75 mach->__rbp = vex->guest_RBP;
76 mach->__rsp = vex->guest_RSP;
77 mach->__rflags = LibVEX_GuestAMD64_get_rflags(vex);
66 x86_thread_state64_from_vex(x86_thread_state64_t *mach, VexGuestAMD64State *vex) argument
95 x86_float_state64_from_vex(x86_float_state64_t *mach, VexGuestAMD64State *vex) argument
124 VexGuestAMD64State *vex = (VexGuestAMD64State *)vex_generic; local
160 x86_thread_state64_to_vex(const x86_thread_state64_t *mach, VexGuestAMD64State *vex) argument
189 x86_float_state64_to_vex(const x86_float_state64_t *mach, VexGuestAMD64State *vex) argument
218 VexGuestAMD64State *vex = (VexGuestAMD64State *)vex_generic; local
341 VexGuestAMD64State *vex = &tst->arch.vex; local
436 VexGuestAMD64State *vex; local
[all...]
H A Dsyswrap-x86-darwin.c65 VexGuestX86State *vex)
67 mach->__eax = vex->guest_EAX;
68 mach->__ebx = vex->guest_EBX;
69 mach->__ecx = vex->guest_ECX;
70 mach->__edx = vex->guest_EDX;
71 mach->__edi = vex->guest_EDI;
72 mach->__esi = vex->guest_ESI;
73 mach->__ebp = vex->guest_EBP;
74 mach->__esp = vex->guest_ESP;
75 mach->__ss = vex
64 x86_thread_state32_from_vex(i386_thread_state_t *mach, VexGuestX86State *vex) argument
86 x86_float_state32_from_vex(i386_float_state_t *mach, VexGuestX86State *vex) argument
100 VexGuestX86State *vex = (VexGuestX86State *)vex_generic; local
119 x86_thread_state32_to_vex(const i386_thread_state_t *mach, VexGuestX86State *vex) argument
141 x86_float_state32_to_vex(const i386_float_state_t *mach, VexGuestX86State *vex) argument
155 VexGuestX86State *vex = (VexGuestX86State *)vex_generic; local
281 VexGuestX86State *vex = &tst->arch.vex; local
384 VexGuestX86State *vex; local
[all...]
H A Dsyswrap-x86-linux.c253 ctst->arch.vex.guest_EAX = 0;
256 ctst->arch.vex.guest_ESP = esp;
293 ptst->arch.vex.guest_ESP,
294 ctst->arch.vex.guest_FS, ctst->arch.vex.guest_GS);
481 static void deallocate_LGDTs_for_thread ( VexGuestX86State* vex )
488 vex->guest_LDT, vex->guest_GDT );
490 if (vex->guest_LDT != (HWord)NULL) {
491 free_LDT_or_GDT( (VexGuestX86SegDescr*)vex
[all...]
H A Dsyswrap-main.c314 syscallno, &tst->arch.vex,
321 VG_DARWIN_SYSNO_FOR_KERNEL(syscallno), &tst->arch.vex,
327 VG_DARWIN_SYSNO_FOR_KERNEL(syscallno), &tst->arch.vex,
333 VG_DARWIN_SYSNO_FOR_KERNEL(syscallno), &tst->arch.vex,
1565 getSyscallArgsFromGuestState( &sci->orig_args, &tst->arch.vex, trc );
1593 tst->arch.vex.guest_SC_CLASS = VG_DARWIN_SYSNO_CLASS(sysno);
1732 putSyscallArgsIntoGuestState( &sci->args, &tst->arch.vex );
1765 getSyscallStatusFromGuestState( &sci->status, &tst->arch.vex );
1804 putSyscallStatusIntoGuestState( tid, &sci->status, &tst->arch.vex );
1861 getSyscallStatusFromGuestState( &test_status, &tst->arch.vex );
[all...]
H A Dsyswrap-ppc64-linux.c433 { UInt old_cr = LibVEX_GuestPPC64_get_CR( &ctst->arch.vex );
435 ctst->arch.vex.guest_GPR3 = 0;
437 LibVEX_GuestPPC64_put_CR( old_cr & ~(1<<28), &ctst->arch.vex );
441 ctst->arch.vex.guest_GPR1 = sp;
472 ctst->arch.vex.guest_GPR13 = child_tls;
523 child->vex = parent->vex;
740 //tst->arch.vex.guest_ESP -= sizeof(Addr);
/external/valgrind/coregrind/m_coredump/
H A Dcoredump-elf.c253 regs->eflags = LibVEX_GuestX86_get_eflags( &arch->vex );
254 regs->esp = arch->vex.guest_ESP;
255 regs->eip = arch->vex.guest_EIP;
257 regs->ebx = arch->vex.guest_EBX;
258 regs->ecx = arch->vex.guest_ECX;
259 regs->edx = arch->vex.guest_EDX;
260 regs->esi = arch->vex.guest_ESI;
261 regs->edi = arch->vex.guest_EDI;
262 regs->ebp = arch->vex.guest_EBP;
263 regs->eax = arch->vex
[all...]
/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h52 #define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7)
53 #define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6)
54 #define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5)
55 #define mmmmmFromVEX2of3(vex) ((vex) & 0x1f)
56 #define wFromVEX3of3(vex) (((vex)
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/external/valgrind/coregrind/m_initimg/
H A Dinitimg-linux.c1028 LibVEX_GuestX86_initialise(&arch->vex);
1035 arch->vex.guest_ESP = iifii.initial_client_SP;
1036 arch->vex.guest_EIP = iifii.initial_client_IP;
1040 asm volatile("movw %%cs, %0" : : "m" (arch->vex.guest_CS));
1041 asm volatile("movw %%ds, %0" : : "m" (arch->vex.guest_DS));
1042 asm volatile("movw %%ss, %0" : : "m" (arch->vex.guest_SS));
1043 asm volatile("movw %%es, %0" : : "m" (arch->vex.guest_ES));
1050 LibVEX_GuestAMD64_initialise(&arch->vex);
1057 arch->vex.guest_RSP = iifii.initial_client_SP;
1058 arch->vex
[all...]
H A Dinitimg-darwin.c594 LibVEX_GuestX86_initialise(&arch->vex);
601 arch->vex.guest_ESP = iifii.initial_client_SP;
602 arch->vex.guest_EIP = iifii.initial_client_IP;
609 LibVEX_GuestAMD64_initialise(&arch->vex);
616 arch->vex.guest_RSP = iifii.initial_client_SP;
617 arch->vex.guest_RIP = iifii.initial_client_IP;
/external/valgrind/coregrind/m_scheduler/
H A Dscheduler.c697 Addr a_vex = (Addr) & tst->arch.vex;
701 UInt sz_vex = (UInt) sizeof tst->arch.vex;
771 vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VSR0));
775 vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VSR1));
783 vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_D0));
787 vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex.guest_D1));
793 vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex.guest_X0));
796 vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_Q0));
874 UInt cno = (UInt)VG_TT_FAST_HASH((Addr)tst->arch.vex.VG_INSTR_PTR);
875 if (LIKELY(VG_(tt_fast)[cno].guest == (Addr)tst->arch.vex
[all...]
/external/valgrind/none/tests/s390x/
H A Dop_exception.stderr.exp2 vex s390->IR: unknown insn: 0000
15 vex s390->IR: unknown insn: 0000
28 vex s390->IR: unknown insn: FFFF FFFF FFFF
41 vex s390->IR: unknown insn: 0000

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