Searched refs:st3 (Results 1 - 25 of 30) sorted by relevance

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/external/clang/test/CodeGen/
H A Dstruct-x86-darwin.c15 struct STest3 {char a; short b; int c; } st3; variable in typeref:struct:STest3
/external/apache-harmony/sql/src/test/java/org/apache/harmony/sql/tests/javax/sql/
H A DStatementEventTest.java92 StatementEvent st3 = new StatementEvent(pc, null, new SQLException(
94 SerializationTest.verifyGolden(this, st3, STATEMENTEVENT_COMPARATOR);
/external/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s172 st3 { v0.16b, v1.16b, v2.16b }, [x0]
173 st3 { v15.8h, v16.8h, v17.8h }, [x15]
174 st3 { v31.4s, v0.4s, v1.4s }, [sp]
175 st3 { v0.2d, v1.2d, v2.2d }, [x0]
176 st3 { v0.8b, v1.8b, v2.8b }, [x0]
177 st3 { v15.4h, v16.4h, v17.4h }, [x15]
178 st3 { v31.2s, v0.2s, v1.2s }, [sp]
179 // CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x00,0x4c]
180 // CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x00,0x4c]
181 // CHECK: st3 { v3
[all...]
H A Dneon-simd-ldst-one-elem.s148 st3 { v0.b, v1.b, v2.b }[9], [x0]
149 st3 { v15.h, v16.h, v17.h }[7], [x15]
150 st3 { v31.s, v0.s, v1.s }[3], [sp]
151 st3 { v0.d, v1.d, v2.d }[1], [x0]
152 // CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x00,0x4d]
153 // CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x00,0x4d]
154 // CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d]
155 // CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d]
309 st3 { v0.b, v1.b, v2.b }[9], [x0], #3
310 st3 { v1
[all...]
H A Darm64-simd-ldst.s239 st3.8b {v4, v5, v6}, [x19]
240 st3.16b {v4, v5, v6}, [x19]
241 st3.4h {v4, v5, v6}, [x19]
242 st3.8h {v4, v5, v6}, [x19]
243 st3.2s {v4, v5, v6}, [x19]
244 st3.4s {v4, v5, v6}, [x19]
245 st3.2d {v4, v5, v6}, [x19]
247 st3.8b {v10, v11, v12}, [x9]
248 st3.16b {v14, v15, v16}, [x19]
249 st3
[all...]
H A Dneon-simd-post-ldst-multi-elem.s343 st3 { v0.16b, v1.16b, v2.16b }, [x0], x1
344 st3 { v15.8h, v16.8h, v17.8h }, [x15], x2
345 st3 { v31.4s, v0.4s, v1.4s }, [sp], #48
346 st3 { v0.2d, v1.2d, v2.2d }, [x0], #48
347 st3 { v0.8b, v1.8b, v2.8b }, [x0], x2
348 st3 { v15.4h, v16.4h, v17.4h }, [x15], x3
349 st3 { v31.2s, v0.2s, v1.2s }, [sp], #24
350 // CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0], x1
352 // CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2
354 // CHECK: st3 { v3
[all...]
H A Dneon-diagnostics.s4091 st3 {v15.8h, v16.8h, v17.4h}, [x15]
4092 st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
4093 st3 {v0.8b, v2.8b, v3.8b}, [x0]
4094 st3 {v15.8h-v17.4h}, [x15]
4095 st3 {v31.4s-v2.4s}, [sp]
4097 // CHECK-ERROR: st3 {v15.8h, v16.8h, v17.4h}, [x15]
4100 // CHECK-ERROR: st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
4103 // CHECK-ERROR: st3 {v0.8b, v2.8b, v3.8b}, [x0]
4106 // CHECK-ERROR: st3 {v15.8h-v17.4h}, [x15]
4109 // CHECK-ERROR: st3 {v3
[all...]
/external/compiler-rt/lib/sanitizer_common/tests/
H A Dsanitizer_libc_test.cc94 struct stat st1, st2, st3; local
97 EXPECT_EQ(0u, internal_fstat(fd, &st3));
98 EXPECT_EQ(fsize, (uptr)st3.st_size);
/external/libvpx/libvpx/vpx_dsp/mips/
H A Dconvolve2_avg_horiz_dspr2.c280 uint32_t st1, st2, st3; local
346 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 3 */
351 "addqh_r.w %[qload3], %[qload3], %[st3] \n\t" /* average even 3 */
375 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 6 */
382 "addqh_r.w %[qload3], %[qload3], %[st3] \n\t" /* average even 6 */
421 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 1 */
426 "addqh_r.w %[st3], %[st3], %[st1] \n\t" /* average odd 1 */
429 "sb %[st3], 1(%[dst]) \n\t" /* store odd 1 to dst */
453 "lbux %[st3],
529 uint32_t st1, st2, st3; local
[all...]
H A Dconvolve2_dspr2.c263 uint32_t st1, st2, st3; local
327 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 3 */
332 "sb %[st3], 0(%[dst]) \n\t" /* even 3 */
356 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 6 */
362 "sb %[st3], 0(%[dst]) \n\t" /* even 6 */
394 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 1 */
400 "sb %[st3], 0(%[odd_dst]) \n\t" /* odd 1 */
423 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 4 */
428 "sb %[st3], 0(%[odd_dst]) \n\t" /* odd 4 */
449 "lbux %[st3],
495 uint32_t st1, st2, st3; local
[all...]
H A Dconvolve2_horiz_dspr2.c242 uint32_t st1, st2, st3; local
301 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 3 */
306 "sb %[st3], 4(%[dst]) \n\t" /* even 3 */
325 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 6 */
331 "sb %[st3], 10(%[dst]) \n\t" /* even 6 */
361 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 1 */
367 "sb %[st3], 1(%[dst]) \n\t" /* odd 1 */
387 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 4 */
392 "sb %[st3], 7(%[dst]) \n\t" /* odd 4 */
409 "lbux %[st3],
449 uint32_t st1, st2, st3; local
[all...]
H A Dconvolve8_avg_horiz_dspr2.c346 uint32_t st1, st2, st3; local
426 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 3 */
431 "addqh_r.w %[qload3], %[qload3], %[st3] \n\t" /* average even 3 */
468 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 6 */
475 "addqh_r.w %[qload3], %[qload3], %[st3] \n\t" /* average even 6 */
523 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 1 */
528 "addqh_r.w %[st3], %[st3], %[st1] \n\t" /* average odd 1 */
534 "sb %[st3], 1(%[dst]) \n\t" /* store odd 1 to dst */
566 "lbux %[st3],
657 uint32_t st1, st2, st3; local
[all...]
H A Dconvolve8_horiz_dspr2.c312 uint32_t st1, st2, st3; local
385 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 3 */
391 "sb %[st3], 4(%[dst]) \n\t" /* even 3 */
422 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 6 */
429 "sb %[st3], 10(%[dst]) \n\t" /* even 6 */
467 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 1 */
473 "sb %[st3], 1(%[dst]) \n\t" /* odd 1 */
504 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 4 */
510 "sb %[st3], 7(%[dst]) \n\t" /* odd 4 */
538 "lbux %[st3],
582 uint32_t st1, st2, st3; local
[all...]
H A Dconvolve8_dspr2.c329 uint32_t st1, st2, st3; local
407 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 3 */
413 "sb %[st3], 0(%[dst]) \n\t" /* even 3 */
447 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* even 6 */
454 "sb %[st3], 0(%[dst]) \n\t" /* even 6 */
494 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 1 */
500 "sb %[st3], 0(%[odd_dst]) \n\t" /* odd 1 */
534 "lbux %[st3], %[Temp3](%[cm]) \n\t" /* odd 4 */
540 "sb %[st3], 0(%[odd_dst]) \n\t" /* odd 4 */
570 "lbux %[st3],
619 uint32_t st1, st2, st3; local
[all...]
/external/icu/icu4j/main/classes/charset/src/com/ibm/icu/charset/
H A DCharsetMBCS.java518 int i, st3;
565 st3 = tableInts[stage2];
566 st3 = (int)(char)(st3 * 16 + (c&0xf));
572 p = st3*3;
578 ints[st3] = (int)value;
582 chars[st3] = (char)value;
610 int st1, st2, st3, i;
617 st3 = mbcsTable.mbcsIndex.get(stageUTF8Index++);
618 if (st3 !
[all...]
/external/icu/icu4c/source/common/
H A Ducnvmbcs.cpp857 uint32_t st3; local
897 if((st3=stage2[st2])!=0) {
899 stage3=results+st3;
943 if((st3=stage2[st2])!=0) {
945 stage3=bytes+st3Multiplier*16*(uint32_t)(uint16_t)st3;
948 st3>>=16;
958 if(st3&1) {
978 st3>>=1;
984 if(((st3&1)!=0 || useFallback) && *((const uint16_t *)stage3)>=0x100) {
987 st3>>
1406 int32_t i, st3; local
1510 int32_t st1, st2, st3, i; local
[all...]
H A Ducnv_ext.cpp1034 int32_t st1, stage1Length, st2, st3, minLength; local
1074 if((st3=(int32_t)ps2[st2]<<UCNV_EXT_STAGE_2_LEFT_SHIFT)!=0) {
1076 ps3=stage3+st3;
/external/valgrind/exp-dhat/
H A Ddh_main.c791 IRStmt* st3 = IRStmt_Store(END, counter_addr, mkexpr(t2)); local
795 addStmtToIRSB( sbOut, st3 );
/external/valgrind/none/tests/amd64/
H A Dgen_insn_test.pl64 st0 => 0, st1 => 1, st2 => 2, st3 => 3,
/external/valgrind/none/tests/x86/
H A Dgen_insn_test.pl59 st0 => 0, st1 => 1, st2 => 2, st3 => 3,
/external/valgrind/massif/
H A Dms_main.c2036 IRStmt* st3 = IRStmt_Store(END, counter_addr, IRExpr_RdTmp(t2)); local
2040 addStmtToIRSB( sbOut, st3 );
/external/valgrind/none/tests/arm64/
H A Dmemory.stdout.exp10349 st3 {v17.2d, v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
10379 st3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+9, x6=9
10409 st3 {v17.2d, v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
10439 st3 {v17.4s, v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
10469 st3 {v17.4s, v18.4s, v19.4s}, [x5], #48 with x5 = middle_of_block+9, x6=9
10499 st3 {v17.4s, v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
10529 st3 {v17.2s, v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
10559 st3 {v17.2s, v18.2s, v19.2s}, [x5], #24 with x5 = middle_of_block+9, x6=9
10589 st3 {v17.2s, v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
10619 st3 {v1
[all...]
/external/elfutils/src/tests/
H A Drun-addrcfi.sh46 x87 reg14 (%st3): undefined
93 x87 reg14 (%st3): undefined
167 x87 reg36 (%st3): undefined
233 x87 reg36 (%st3): undefined
H A Drun-allregs.sh75 14: %st3 (st3), float 80 bits
147 36: %st3 (st3), float 80 bits
/external/vixl/src/vixl/a64/
H A Dsimulator-a64.h1512 void st3(VectorFormat vform,
1517 void st3(VectorFormat vform,

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