/external/llvm/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg, argument 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
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H A D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { argument 40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); 52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { argument 67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); 104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { 106 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg); 130 if (VirtReg->empty() || LiveUnion->empty()) { 135 // In most cases, the union will start before VirtReg [all...] |
H A D | LiveRegMatrix.cpp | 99 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 100 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 102 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); 103 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 106 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, 109 Matrix[Unit].unify(VirtReg, Range); 117 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { argument 118 unsigned PhysReg = VRM->getPhys(VirtReg.reg); 119 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg 134 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 152 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 166 query(LiveInterval &VirtReg, unsigned RegUnit) argument 174 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument [all...] |
H A D | RegAllocBasic.cpp | 102 unsigned selectOrSplit(LiveInterval &VirtReg, 111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 164 // that interfere with VirtReg. The newly spilled or split live intervals are 166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument 174 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); 180 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) 186 " interferences with " << VirtReg << "\n"); 220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, argument 226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); 229 switch (Matrix->checkInterference(VirtReg, PhysRe [all...] |
H A D | RegisterCoalescer.h | 66 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | TargetRegisterInfo.cpp | 265 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument 271 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 283 // Check that Phys is a valid hint in VirtReg's register class. 289 // from VirtReg's register class if they aren't in the allocation order. The
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H A D | VirtRegMap.cpp | 84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { argument 85 unsigned Hint = MRI->getSimpleHint(VirtReg); 90 return getPhys(VirtReg) == Hint; 93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { argument 94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); 244 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); local 245 if (MRI->reg_nodbg_empty(VirtReg)) 247 LiveInterval &LI = LIS->getInterval(VirtReg); 252 unsigned PhysReg = VRM->getPhys(VirtReg); 349 // If we encounter a VirtReg o 360 unsigned VirtReg = MO.getReg(); local [all...] |
H A D | PHIElimination.cpp | 201 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs. 203 static bool isImplicitlyDefined(unsigned VirtReg, argument 205 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
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H A D | RegAllocFast.cpp | 72 unsigned VirtReg; // Virtual register number. member in struct:__anon10466::RAFast::LiveReg 78 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} 81 return TargetRegisterInfo::virtReg2Index(VirtReg); 167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); 172 void killVirtReg(unsigned VirtReg); 174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { argument 181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { 184 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 201 getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) argument 256 killVirtReg(unsigned VirtReg) argument 266 spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) argument 507 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument 518 const unsigned VirtReg = LRI->VirtReg; local 590 defineVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument 623 reloadVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument [all...] |
H A D | InlineSpiller.cpp | 856 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, argument 862 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops); 868 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); 874 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) 890 markValueUsed(&VirtReg, ParentVNI); 895 // If the instruction also writes VirtReg.reg, it had better not require the 898 markValueUsed(&VirtReg, ParentVNI); 925 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
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H A D | LiveDebugVariables.cpp | 309 /// lookupVirtReg - Find the EC leader for VirtReg or null. 310 UserValue *lookupVirtReg(unsigned VirtReg); 348 void mapVirtReg(unsigned VirtReg, UserValue *EC); 478 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument 479 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs"); 480 UserValue *&Leader = virtRegToEqClass[VirtReg]; 484 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument 485 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) 934 unsigned VirtReg = Loc.getReg(); local 935 if (VRM.isAssignedReg(VirtReg) [all...] |
H A D | MachineBasicBlock.cpp | 359 unsigned VirtReg = I->getOperand(0).getReg(); local 360 if (!MRI.constrainRegClass(VirtReg, RC)) 362 return VirtReg; 366 unsigned VirtReg = MRI.createVirtualRegister(RC); local 367 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) 371 return VirtReg;
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H A D | RegAllocGreedy.cpp | 197 LiveRangeStage getStage(const LiveInterval &VirtReg) const { 198 return ExtraRegInfo[VirtReg.reg].Stage; 201 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument 203 ExtraRegInfo[VirtReg.reg].Stage = Stage; 342 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg); 347 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, 358 unsigned calculateRegionSplitCost(LiveInterval &VirtReg, 363 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, 368 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order, 476 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { argument 488 LRE_WillShrinkVirtReg(unsigned VirtReg) argument 593 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 637 canReassign(LiveInterval &VirtReg, unsigned PrevReg) argument 700 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument 782 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &NewVRegs) argument 823 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit) argument 1313 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1343 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR) argument 1424 doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, bool HasCompact, SmallVectorImpl<unsigned> &NewVRegs) argument 1472 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1540 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument 1684 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | LiveIntervalUnion.h | 87 void unify(LiveInterval &VirtReg, const LiveRange &Range); 88 void unify(LiveInterval &VirtReg) { argument 89 unify(VirtReg, VirtReg); 93 void extract(LiveInterval &VirtReg, const LiveRange &Range); 94 void extract(LiveInterval &VirtReg) { argument 95 extract(VirtReg, VirtReg); 113 LiveInterval *VirtReg; member in class:llvm::LiveIntervalUnion::Query 114 LiveInterval::iterator VirtRegI; // current position in VirtReg [all...] |
H A D | ScheduleDAGInstrs.h | 35 unsigned VirtReg; member in struct:llvm::VReg2SUnit 38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} 41 return TargetRegisterInfo::virtReg2Index(VirtReg);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 224 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument 230 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 241 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
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