codegen_x86.h revision 3c12c512faf6837844d5465b23b9410889e5eb11
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23#include <map> 24 25namespace art { 26 27class X86Mir2Lir : public Mir2Lir { 28 protected: 29 class InToRegStorageMapper { 30 public: 31 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide) = 0; 32 virtual ~InToRegStorageMapper() {} 33 }; 34 35 class InToRegStorageX86_64Mapper : public InToRegStorageMapper { 36 public: 37 InToRegStorageX86_64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} 38 virtual ~InToRegStorageX86_64Mapper() {} 39 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide); 40 private: 41 int cur_core_reg_; 42 int cur_fp_reg_; 43 }; 44 45 class InToRegStorageMapping { 46 public: 47 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 48 initialized_(false) {} 49 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 50 int GetMaxMappedIn() { return max_mapped_in_; } 51 bool IsThereStackMapped() { return is_there_stack_mapped_; } 52 RegStorage Get(int in_position); 53 bool IsInitialized() { return initialized_; } 54 private: 55 std::map<int, RegStorage> mapping_; 56 int max_mapped_in_; 57 bool is_there_stack_mapped_; 58 bool initialized_; 59 }; 60 61 public: 62 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena, bool gen64bit); 63 64 // Required for target - codegen helpers. 65 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 66 RegLocation rl_dest, int lit); 67 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 68 LIR* CheckSuspendUsingLoad() OVERRIDE; 69 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 70 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 71 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 72 OpSize size, VolatileKind is_volatile) OVERRIDE; 73 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 74 OpSize size) OVERRIDE; 75 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 76 RegStorage r_dest, OpSize size) OVERRIDE; 77 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 78 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 79 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 80 OpSize size, VolatileKind is_volatile) OVERRIDE; 81 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 82 OpSize size) OVERRIDE; 83 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 84 RegStorage r_src, OpSize size) OVERRIDE; 85 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 86 87 // Required for target - register utilities. 88 RegStorage TargetReg(SpecialTargetRegister reg); 89 RegStorage GetArgMappingToPhysicalReg(int arg_num); 90 RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); 91 RegLocation GetReturnAlt(); 92 RegLocation GetReturnWideAlt(); 93 RegLocation LocCReturn(); 94 RegLocation LocCReturnRef(); 95 RegLocation LocCReturnDouble(); 96 RegLocation LocCReturnFloat(); 97 RegLocation LocCReturnWide(); 98 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 99 void AdjustSpillMask(); 100 void ClobberCallerSave(); 101 void FreeCallTemps(); 102 void LockCallTemps(); 103 void MarkPreservedSingle(int v_reg, RegStorage reg); 104 void MarkPreservedDouble(int v_reg, RegStorage reg); 105 void CompilerInitializeRegAlloc(); 106 107 // Required for target - miscellaneous. 108 void AssembleLIR(); 109 int AssignInsnOffsets(); 110 void AssignOffsets(); 111 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 112 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 113 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 114 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 115 const char* GetTargetInstFmt(int opcode); 116 const char* GetTargetInstName(int opcode); 117 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 118 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 119 uint64_t GetTargetInstFlags(int opcode); 120 size_t GetInsnSize(LIR* lir) OVERRIDE; 121 bool IsUnconditionalBranch(LIR* lir); 122 123 // Check support for volatile load/store of a given size. 124 bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; 125 // Get the register class for load/store of a field. 126 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 127 128 // Required for target - Dalvik-level generators. 129 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 130 RegLocation rl_src2); 131 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 132 RegLocation rl_dest, int scale); 133 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 134 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 135 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 136 RegLocation rl_src1, RegLocation rl_shift); 137 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 138 RegLocation rl_src2); 139 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 140 RegLocation rl_src2); 141 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 142 RegLocation rl_src2); 143 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 144 RegLocation rl_src2); 145 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 146 RegLocation rl_src2); 147 void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); 148 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 149 RegLocation rl_src2); 150 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 151 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 152 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); 153 bool GenInlinedSqrt(CallInfo* info); 154 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 155 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 156 bool GenInlinedPeek(CallInfo* info, OpSize size); 157 bool GenInlinedPoke(CallInfo* info, OpSize size); 158 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 159 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 160 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 161 RegLocation rl_src2); 162 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 163 RegLocation rl_src2); 164 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 165 RegLocation rl_src2); 166 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 167 RegLocation rl_src2, bool is_div); 168 // TODO: collapse reg_lo, reg_hi 169 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 170 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 171 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 172 void GenDivZeroCheckWide(RegStorage reg); 173 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); 174 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); 175 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 176 void GenExitSequence(); 177 void GenSpecialExitSequence(); 178 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 179 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 180 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 181 void GenSelect(BasicBlock* bb, MIR* mir); 182 bool GenMemBarrier(MemBarrierKind barrier_kind); 183 void GenMoveException(RegLocation rl_dest); 184 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 185 int first_bit, int second_bit); 186 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 187 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 188 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 189 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 190 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 191 192 /* 193 * @brief Generate a two address long operation with a constant value 194 * @param rl_dest location of result 195 * @param rl_src constant source operand 196 * @param op Opcode to be generated 197 * @return success or not 198 */ 199 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 200 /* 201 * @brief Generate a three address long operation with a constant value 202 * @param rl_dest location of result 203 * @param rl_src1 source operand 204 * @param rl_src2 constant source operand 205 * @param op Opcode to be generated 206 * @return success or not 207 */ 208 bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 209 Instruction::Code op); 210 211 /** 212 * @brief Generate a long arithmetic operation. 213 * @param rl_dest The destination. 214 * @param rl_src1 First operand. 215 * @param rl_src2 Second operand. 216 * @param op The DEX opcode for the operation. 217 * @param is_commutative The sources can be swapped if needed. 218 */ 219 virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 220 Instruction::Code op, bool is_commutative); 221 222 /** 223 * @brief Generate a two operand long arithmetic operation. 224 * @param rl_dest The destination. 225 * @param rl_src Second operand. 226 * @param op The DEX opcode for the operation. 227 */ 228 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 229 230 /** 231 * @brief Generate a long operation. 232 * @param rl_dest The destination. Must be in a register 233 * @param rl_src The other operand. May be in a register or in memory. 234 * @param op The DEX opcode for the operation. 235 */ 236 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 237 238 /** 239 * @brief Implement instanceof a final class with x86 specific code. 240 * @param use_declaring_class 'true' if we can use the class itself. 241 * @param type_idx Type index to use if use_declaring_class is 'false'. 242 * @param rl_dest Result to be set to 0 or 1. 243 * @param rl_src Object to be tested. 244 */ 245 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 246 RegLocation rl_src); 247 /* 248 * 249 * @brief Implement Set up instanceof a class with x86 specific code. 250 * @param needs_access_check 'true' if we must check the access. 251 * @param type_known_final 'true' if the type is known to be a final class. 252 * @param type_known_abstract 'true' if the type is known to be an abstract class. 253 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 254 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 255 * @param type_idx Type index to use if use_declaring_class is 'false'. 256 * @param rl_dest Result to be set to 0 or 1. 257 * @param rl_src Object to be tested. 258 */ 259 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 260 bool type_known_abstract, bool use_declaring_class, 261 bool can_assume_type_is_in_dex_cache, 262 uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 263 264 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 265 RegLocation rl_src1, RegLocation rl_shift); 266 267 // Single operation generators. 268 LIR* OpUnconditionalBranch(LIR* target); 269 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 270 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 271 LIR* OpCondBranch(ConditionCode cc, LIR* target); 272 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 273 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 274 LIR* OpIT(ConditionCode cond, const char* guide); 275 void OpEndIT(LIR* it); 276 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 277 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 278 LIR* OpReg(OpKind op, RegStorage r_dest_src); 279 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 280 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 281 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 282 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 283 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 284 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 285 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 286 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 287 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 288 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 289 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 290 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 291 LIR* OpTestSuspend(LIR* target); 292 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 293 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 294 LIR* OpVldm(RegStorage r_base, int count); 295 LIR* OpVstm(RegStorage r_base, int count); 296 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 297 void OpRegCopyWide(RegStorage dest, RegStorage src); 298 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 299 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 300 301 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); 302 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); 303 void SpillCoreRegs(); 304 void UnSpillCoreRegs(); 305 static const X86EncodingMap EncodingMap[kX86Last]; 306 bool InexpensiveConstantInt(int32_t value); 307 bool InexpensiveConstantFloat(int32_t value); 308 bool InexpensiveConstantLong(int64_t value); 309 bool InexpensiveConstantDouble(int64_t value); 310 311 /* 312 * @brief Should try to optimize for two address instructions? 313 * @return true if we try to avoid generating three operand instructions. 314 */ 315 virtual bool GenerateTwoOperandInstructions() const { return true; } 316 317 /* 318 * @brief x86 specific codegen for int operations. 319 * @param opcode Operation to perform. 320 * @param rl_dest Destination for the result. 321 * @param rl_lhs Left hand operand. 322 * @param rl_rhs Right hand operand. 323 */ 324 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 325 RegLocation rl_rhs); 326 327 /* 328 * @brief Dump a RegLocation using printf 329 * @param loc Register location to dump 330 */ 331 static void DumpRegLocation(RegLocation loc); 332 333 /* 334 * @brief Load the Method* of a dex method into the register. 335 * @param target_method The MethodReference of the method to be invoked. 336 * @param type How the method will be invoked. 337 * @param register that will contain the code address. 338 * @note register will be passed to TargetReg to get physical register. 339 */ 340 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 341 SpecialTargetRegister symbolic_reg); 342 343 /* 344 * @brief Load the Class* of a Dex Class type into the register. 345 * @param type How the method will be invoked. 346 * @param register that will contain the code address. 347 * @note register will be passed to TargetReg to get physical register. 348 */ 349 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 350 351 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 352 353 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 354 NextCallInsn next_call_insn, 355 const MethodReference& target_method, 356 uint32_t vtable_idx, 357 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 358 bool skip_this); 359 360 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 361 NextCallInsn next_call_insn, 362 const MethodReference& target_method, 363 uint32_t vtable_idx, 364 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 365 bool skip_this); 366 367 /* 368 * @brief Generate a relative call to the method that will be patched at link time. 369 * @param target_method The MethodReference of the method to be invoked. 370 * @param type How the method will be invoked. 371 * @returns Call instruction 372 */ 373 virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 374 375 /* 376 * @brief Handle x86 specific literals 377 */ 378 void InstallLiteralPools(); 379 380 /* 381 * @brief Generate the debug_frame CFI information. 382 * @returns pointer to vector containing CFE information 383 */ 384 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 385 386 /* 387 * @brief Generate the debug_frame FDE information. 388 * @returns pointer to vector containing CFE information 389 */ 390 std::vector<uint8_t>* ReturnCallFrameInformation(); 391 392 protected: 393 size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 394 int32_t raw_base, int32_t displacement); 395 void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); 396 void EmitPrefix(const X86EncodingMap* entry, 397 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); 398 void EmitOpcode(const X86EncodingMap* entry); 399 void EmitPrefixAndOpcode(const X86EncodingMap* entry, 400 int32_t reg_r, int32_t reg_x, int32_t reg_b); 401 void EmitDisp(uint8_t base, int32_t disp); 402 void EmitModrmThread(uint8_t reg_or_opcode); 403 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); 404 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, 405 int32_t disp); 406 void EmitImm(const X86EncodingMap* entry, int64_t imm); 407 void EmitNullary(const X86EncodingMap* entry); 408 void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); 409 void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); 410 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 411 void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 412 int32_t disp); 413 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); 414 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); 415 void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 416 int32_t raw_index, int scale, int32_t disp); 417 void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 418 int32_t disp, int32_t raw_reg); 419 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 420 void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 421 int32_t raw_disp, int32_t imm); 422 void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); 423 void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); 424 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); 425 void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 426 int32_t imm); 427 void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, 428 int32_t imm); 429 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 430 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); 431 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); 432 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 433 void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); 434 void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); 435 void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 436 void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); 437 void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); 438 void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); 439 void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 440 int32_t cc); 441 442 void EmitJmp(const X86EncodingMap* entry, int32_t rel); 443 void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); 444 void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 445 void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); 446 void EmitCallThread(const X86EncodingMap* entry, int32_t disp); 447 void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 448 int32_t raw_index, int scale, int32_t table_or_disp); 449 void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); 450 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 451 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 452 int64_t val, ConditionCode ccode); 453 void GenConstWide(RegLocation rl_dest, int64_t value); 454 455 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 456 457 /* 458 * @brief Ensure that a temporary register is byte addressable. 459 * @returns a temporary guarenteed to be byte addressable. 460 */ 461 virtual RegStorage AllocateByteRegister(); 462 463 /* 464 * @brief Check if a register is byte addressable. 465 * @returns true if a register is byte addressable. 466 */ 467 bool IsByteRegister(RegStorage reg); 468 469 /* 470 * @brief generate inline code for fast case of Strng.indexOf. 471 * @param info Call parameters 472 * @param zero_based 'true' if the index into the string is 0. 473 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 474 * generated. 475 */ 476 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 477 478 /* 479 * @brief Load 128 bit constant into vector register. 480 * @param bb The basic block in which the MIR is from. 481 * @param mir The MIR whose opcode is kMirConstVector 482 * @note vA is the TypeSize for the register. 483 * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. 484 */ 485 void GenConst128(BasicBlock* bb, MIR* mir); 486 487 /* 488 * @brief MIR to move a vectorized register to another. 489 * @param bb The basic block in which the MIR is from. 490 * @param mir The MIR whose opcode is kMirConstVector. 491 * @note vA: TypeSize 492 * @note vB: destination 493 * @note vC: source 494 */ 495 void GenMoveVector(BasicBlock *bb, MIR *mir); 496 497 /* 498 * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know the type of the vector. 499 * @param bb The basic block in which the MIR is from. 500 * @param mir The MIR whose opcode is kMirConstVector. 501 * @note vA: TypeSize 502 * @note vB: destination and source 503 * @note vC: source 504 */ 505 void GenMultiplyVector(BasicBlock *bb, MIR *mir); 506 507 /* 508 * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. 509 * @param bb The basic block in which the MIR is from. 510 * @param mir The MIR whose opcode is kMirConstVector. 511 * @note vA: TypeSize 512 * @note vB: destination and source 513 * @note vC: source 514 */ 515 void GenAddVector(BasicBlock *bb, MIR *mir); 516 517 /* 518 * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. 519 * @param bb The basic block in which the MIR is from. 520 * @param mir The MIR whose opcode is kMirConstVector. 521 * @note vA: TypeSize 522 * @note vB: destination and source 523 * @note vC: source 524 */ 525 void GenSubtractVector(BasicBlock *bb, MIR *mir); 526 527 /* 528 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. 529 * @param bb The basic block in which the MIR is from. 530 * @param mir The MIR whose opcode is kMirConstVector. 531 * @note vA: TypeSize 532 * @note vB: destination and source 533 * @note vC: immediate 534 */ 535 void GenShiftLeftVector(BasicBlock *bb, MIR *mir); 536 537 /* 538 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. 539 * @param bb The basic block in which the MIR is from. 540 * @param mir The MIR whose opcode is kMirConstVector. 541 * @note vA: TypeSize 542 * @note vB: destination and source 543 * @note vC: immediate 544 */ 545 void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); 546 547 /* 548 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. 549 * @param bb The basic block in which the MIR is from.. 550 * @param mir The MIR whose opcode is kMirConstVector. 551 * @note vA: TypeSize 552 * @note vB: destination and source 553 * @note vC: immediate 554 */ 555 void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); 556 557 /* 558 * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. 559 * @note vA: TypeSize 560 * @note vB: destination and source 561 * @note vC: source 562 */ 563 void GenAndVector(BasicBlock *bb, MIR *mir); 564 565 /* 566 * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. 567 * @param bb The basic block in which the MIR is from. 568 * @param mir The MIR whose opcode is kMirConstVector. 569 * @note vA: TypeSize 570 * @note vB: destination and source 571 * @note vC: source 572 */ 573 void GenOrVector(BasicBlock *bb, MIR *mir); 574 575 /* 576 * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. 577 * @param bb The basic block in which the MIR is from. 578 * @param mir The MIR whose opcode is kMirConstVector. 579 * @note vA: TypeSize 580 * @note vB: destination and source 581 * @note vC: source 582 */ 583 void GenXorVector(BasicBlock *bb, MIR *mir); 584 585 /* 586 * @brief Reduce a 128-bit packed element into a single VR by taking lower bits 587 * @param bb The basic block in which the MIR is from. 588 * @param mir The MIR whose opcode is kMirConstVector. 589 * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. 590 * @note vA: TypeSize 591 * @note vB: destination and source VR (not vector register) 592 * @note vC: source (vector register) 593 */ 594 void GenAddReduceVector(BasicBlock *bb, MIR *mir); 595 596 /* 597 * @brief Extract a packed element into a single VR. 598 * @param bb The basic block in which the MIR is from. 599 * @param mir The MIR whose opcode is kMirConstVector. 600 * @note vA: TypeSize 601 * @note vB: destination VR (not vector register) 602 * @note vC: source (vector register) 603 * @note arg[0]: The index to use for extraction from vector register (which packed element). 604 */ 605 void GenReduceVector(BasicBlock *bb, MIR *mir); 606 607 /* 608 * @brief Create a vector value, with all TypeSize values equal to vC 609 * @param bb The basic block in which the MIR is from. 610 * @param mir The MIR whose opcode is kMirConstVector. 611 * @note vA: TypeSize. 612 * @note vB: destination vector register. 613 * @note vC: source VR (not vector register). 614 */ 615 void GenSetVector(BasicBlock *bb, MIR *mir); 616 617 /* 618 * @brief Generate code for a vector opcode. 619 * @param bb The basic block in which the MIR is from. 620 * @param mir The MIR whose opcode is a non-standard opcode. 621 */ 622 void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 623 624 /* 625 * @brief Return the correct x86 opcode for the Dex operation 626 * @param op Dex opcode for the operation 627 * @param loc Register location of the operand 628 * @param is_high_op 'true' if this is an operation on the high word 629 * @param value Immediate value for the operation. Used for byte variants 630 * @returns the correct x86 opcode to perform the operation 631 */ 632 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 633 634 /* 635 * @brief Return the correct x86 opcode for the Dex operation 636 * @param op Dex opcode for the operation 637 * @param dest location of the destination. May be register or memory. 638 * @param rhs Location for the rhs of the operation. May be in register or memory. 639 * @param is_high_op 'true' if this is an operation on the high word 640 * @returns the correct x86 opcode to perform the operation 641 * @note at most one location may refer to memory 642 */ 643 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 644 bool is_high_op); 645 646 /* 647 * @brief Is this operation a no-op for this opcode and value 648 * @param op Dex opcode for the operation 649 * @param value Immediate value for the operation. 650 * @returns 'true' if the operation will have no effect 651 */ 652 bool IsNoOp(Instruction::Code op, int32_t value); 653 654 /** 655 * @brief Calculate magic number and shift for a given divisor 656 * @param divisor divisor number for calculation 657 * @param magic hold calculated magic number 658 * @param shift hold calculated shift 659 */ 660 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 661 662 /* 663 * @brief Generate an integer div or rem operation. 664 * @param rl_dest Destination Location. 665 * @param rl_src1 Numerator Location. 666 * @param rl_src2 Divisor Location. 667 * @param is_div 'true' if this is a division, 'false' for a remainder. 668 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 669 */ 670 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 671 bool is_div, bool check_zero); 672 673 /* 674 * @brief Generate an integer div or rem operation by a literal. 675 * @param rl_dest Destination Location. 676 * @param rl_src Numerator Location. 677 * @param lit Divisor. 678 * @param is_div 'true' if this is a division, 'false' for a remainder. 679 */ 680 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 681 682 /* 683 * Generate code to implement long shift operations. 684 * @param opcode The DEX opcode to specify the shift type. 685 * @param rl_dest The destination. 686 * @param rl_src The value to be shifted. 687 * @param shift_amount How much to shift. 688 * @returns the RegLocation of the result. 689 */ 690 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 691 RegLocation rl_src, int shift_amount); 692 /* 693 * Generate an imul of a register by a constant or a better sequence. 694 * @param dest Destination Register. 695 * @param src Source Register. 696 * @param val Constant multiplier. 697 */ 698 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 699 700 /* 701 * Generate an imul of a memory location by a constant or a better sequence. 702 * @param dest Destination Register. 703 * @param sreg Symbolic register. 704 * @param displacement Displacement on stack of Symbolic Register. 705 * @param val Constant multiplier. 706 */ 707 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 708 709 /* 710 * @brief Compare memory to immediate, and branch if condition true. 711 * @param cond The condition code that when true will branch to the target. 712 * @param temp_reg A temporary register that can be used if compare memory is not 713 * supported by the architecture. 714 * @param base_reg The register holding the base address. 715 * @param offset The offset from the base. 716 * @param check_value The immediate to compare to. 717 */ 718 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 719 int offset, int check_value, LIR* target); 720 721 /* 722 * Can this operation be using core registers without temporaries? 723 * @param rl_lhs Left hand operand. 724 * @param rl_rhs Right hand operand. 725 * @returns 'true' if the operation can proceed without needing temporary regs. 726 */ 727 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 728 729 /** 730 * @brief Generates inline code for conversion of long to FP by using x87/ 731 * @param rl_dest The destination of the FP. 732 * @param rl_src The source of the long. 733 * @param is_double 'true' if dealing with double, 'false' for float. 734 */ 735 virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 736 737 /* 738 * @brief Perform MIR analysis before compiling method. 739 * @note Invokes Mir2LiR::Materialize after analysis. 740 */ 741 void Materialize(); 742 743 /* 744 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register 745 * without regard to data type. In practice, this can result in UpdateLoc returning a 746 * location record for a Dalvik float value in a core register, and vis-versa. For targets 747 * which can inexpensively move data between core and float registers, this can often be a win. 748 * However, for x86 this is generally not a win. These variants of UpdateLoc() 749 * take a register class argument - and will return an in-register location record only if 750 * the value is live in a temp register of the correct class. Additionally, if the value is in 751 * a temp register of the wrong register class, it will be clobbered. 752 */ 753 RegLocation UpdateLocTyped(RegLocation loc, int reg_class); 754 RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); 755 756 /* 757 * @brief Analyze MIR before generating code, to prepare for the code generation. 758 */ 759 void AnalyzeMIR(); 760 761 /* 762 * @brief Analyze one basic block. 763 * @param bb Basic block to analyze. 764 */ 765 void AnalyzeBB(BasicBlock * bb); 766 767 /* 768 * @brief Analyze one extended MIR instruction 769 * @param opcode MIR instruction opcode. 770 * @param bb Basic block containing instruction. 771 * @param mir Extended instruction to analyze. 772 */ 773 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 774 775 /* 776 * @brief Analyze one MIR instruction 777 * @param opcode MIR instruction opcode. 778 * @param bb Basic block containing instruction. 779 * @param mir Instruction to analyze. 780 */ 781 virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 782 783 /* 784 * @brief Analyze one MIR float/double instruction 785 * @param opcode MIR instruction opcode. 786 * @param bb Basic block containing instruction. 787 * @param mir Instruction to analyze. 788 */ 789 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 790 791 /* 792 * @brief Analyze one use of a double operand. 793 * @param rl_use Double RegLocation for the operand. 794 */ 795 void AnalyzeDoubleUse(RegLocation rl_use); 796 797 /* 798 * @brief Analyze one invoke-static MIR instruction 799 * @param opcode MIR instruction opcode. 800 * @param bb Basic block containing instruction. 801 * @param mir Instruction to analyze. 802 */ 803 void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); 804 805 bool Gen64Bit() const { return gen64bit_; } 806 807 // Information derived from analysis of MIR 808 809 // The compiler temporary for the code address of the method. 810 CompilerTemp *base_of_code_; 811 812 // Have we decided to compute a ptr to code and store in temporary VR? 813 bool store_method_addr_; 814 815 // Have we used the stored method address? 816 bool store_method_addr_used_; 817 818 // Instructions to remove if we didn't use the stored method address. 819 LIR* setup_method_address_[2]; 820 821 // Instructions needing patching with Method* values. 822 GrowableArray<LIR*> method_address_insns_; 823 824 // Instructions needing patching with Class Type* values. 825 GrowableArray<LIR*> class_type_address_insns_; 826 827 // Instructions needing patching with PC relative code addresses. 828 GrowableArray<LIR*> call_method_insns_; 829 830 // Prologue decrement of stack pointer. 831 LIR* stack_decrement_; 832 833 // Epilogue increment of stack pointer. 834 LIR* stack_increment_; 835 836 // 64-bit mode 837 bool gen64bit_; 838 839 // The list of const vector literals. 840 LIR *const_vectors_; 841 842 /* 843 * @brief Search for a matching vector literal 844 * @param mir A kMirOpConst128b MIR instruction to match. 845 * @returns pointer to matching LIR constant, or nullptr if not found. 846 */ 847 LIR *ScanVectorLiteral(MIR *mir); 848 849 /* 850 * @brief Add a constant vector literal 851 * @param mir A kMirOpConst128b MIR instruction to match. 852 */ 853 LIR *AddVectorLiteral(MIR *mir); 854 855 InToRegStorageMapping in_to_reg_storage_mapping_; 856}; 857 858} // namespace art 859 860#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 861