codegen_x86.h revision 614c2b4e219631e8c190fd9fd5d4d9cd343434e1 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
19
20#include "dex/compiler_internals.h"
21#include "x86_lir.h"
22
23namespace art {
24
25class X86Mir2Lir : public Mir2Lir {
26  public:
27    X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen helpers.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                                    RegLocation rl_dest, int lit);
32    int LoadHelper(ThreadOffset offset);
33    LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34    LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
35                                  int s_reg);
36    LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37    LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
38                                     int r_dest, int r_dest_hi, OpSize size, int s_reg);
39    LIR* LoadConstantNoClobber(int r_dest, int value);
40    LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
41    LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42    LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43    LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44    LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
45                                      int r_src, int r_src_hi, OpSize size, int s_reg);
46    void MarkGCCard(int val_reg, int tgt_addr_reg);
47
48    // Required for target - register utilities.
49    bool IsFpReg(int reg);
50    bool SameRegType(int reg1, int reg2);
51    int AllocTypedTemp(bool fp_hint, int reg_class);
52    int AllocTypedTempPair(bool fp_hint, int reg_class);
53    int S2d(int low_reg, int high_reg);
54    int TargetReg(SpecialTargetRegister reg);
55    RegLocation GetReturnAlt();
56    RegLocation GetReturnWideAlt();
57    RegLocation LocCReturn();
58    RegLocation LocCReturnDouble();
59    RegLocation LocCReturnFloat();
60    RegLocation LocCReturnWide();
61    uint32_t FpRegMask();
62    uint64_t GetRegMaskCommon(int reg);
63    void AdjustSpillMask();
64    void ClobberCallerSave();
65    void FlushReg(int reg);
66    void FlushRegWide(int reg1, int reg2);
67    void FreeCallTemps();
68    void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
69    void LockCallTemps();
70    void MarkPreservedSingle(int v_reg, int reg);
71    void CompilerInitializeRegAlloc();
72
73    // Required for target - miscellaneous.
74    void AssembleLIR();
75    int AssignInsnOffsets();
76    void AssignOffsets();
77    AssemblerStatus AssembleInstructions(CodeOffset start_addr);
78    void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
79    void SetupTargetResourceMasks(LIR* lir, uint64_t flags);
80    const char* GetTargetInstFmt(int opcode);
81    const char* GetTargetInstName(int opcode);
82    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
83    uint64_t GetPCUseDefEncoding();
84    uint64_t GetTargetInstFlags(int opcode);
85    int GetInsnSize(LIR* lir);
86    bool IsUnconditionalBranch(LIR* lir);
87
88    // Required for target - Dalvik-level generators.
89    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
90                                   RegLocation rl_src1, RegLocation rl_src2);
91    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
92                             RegLocation rl_index, RegLocation rl_dest, int scale);
93    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
94                     RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark);
95    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
96                           RegLocation rl_src1, RegLocation rl_shift);
97    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
98    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
99    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
100    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
101                                  RegLocation rl_src1, RegLocation rl_src2);
102    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
103                                 RegLocation rl_src1, RegLocation rl_src2);
104    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105                          RegLocation rl_src2);
106    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
107    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
108    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
109    bool GenInlinedSqrt(CallInfo* info);
110    bool GenInlinedPeek(CallInfo* info, OpSize size);
111    bool GenInlinedPoke(CallInfo* info, OpSize size);
112    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
113    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
114    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
115    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
116    LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
117                                ThrowKind kind);
118    LIR* GenMemImmedCheck(ConditionCode c_code, int base, int offset, int check_value,
119                          ThrowKind kind);
120    RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
121    RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
122    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
123    void GenDivZeroCheck(int reg_lo, int reg_hi);
124    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
125    void GenExitSequence();
126    void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
127    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
128    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
129    void GenSelect(BasicBlock* bb, MIR* mir);
130    void GenMemBarrier(MemBarrierKind barrier_kind);
131    void GenMoveException(RegLocation rl_dest);
132    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result,
133                                               int lit, int first_bit, int second_bit);
134    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
135    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
136    void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
137    void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
138    void GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special);
139    /*
140     * @brief Generate a two address long operation with a constant value
141     * @param rl_dest location of result
142     * @param rl_src constant source operand
143     * @param op Opcode to be generated
144     */
145    void GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
146    /*
147     * @brief Generate a three address long operation with a constant value
148     * @param rl_dest location of result
149     * @param rl_src1 source operand
150     * @param rl_src2 constant source operand
151     * @param op Opcode to be generated
152     */
153    void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1,
154                        RegLocation rl_src2, Instruction::Code op);
155
156    /**
157      * @brief Generate a long arithmetic operation.
158      * @param rl_dest The destination.
159      * @param rl_src1 First operand.
160      * @param rl_src2 Second operand.
161      * @param op The DEX opcode for the operation.
162      * @param is_commutative The sources can be swapped if needed.
163      */
164    void GenLongArith(RegLocation rl_dest, RegLocation rl_src1,
165                      RegLocation rl_src2, Instruction::Code op, bool is_commutative);
166
167    /**
168      * @brief Generate a two operand long arithmetic operation.
169      * @param rl_dest The destination.
170      * @param rl_src Second operand.
171      * @param op The DEX opcode for the operation.
172      */
173    void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
174
175    /**
176      * @brief Generate a long operation.
177      * @param rl_dest The destination.  Must be in a register
178      * @param rl_src The other operand.  May be in a register or in memory.
179      * @param op The DEX opcode for the operation.
180      */
181    void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
182
183    /**
184     * @brief Implement instanceof a final class with x86 specific code.
185     * @param use_declaring_class 'true' if we can use the class itself.
186     * @param type_idx Type index to use if use_declaring_class is 'false'.
187     * @param rl_dest Result to be set to 0 or 1.
188     * @param rl_src Object to be tested.
189     */
190    void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx,
191                            RegLocation rl_dest, RegLocation rl_src);
192    /*
193     *
194     * @brief Implement Set up instanceof a class with x86 specific code.
195     * @param needs_access_check 'true' if we must check the access.
196     * @param type_known_final 'true' if the type is known to be a final class.
197     * @param type_known_abstract 'true' if the type is known to be an abstract class.
198     * @param use_declaring_class 'true' if the type can be loaded off the current Method*.
199     * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache.
200     * @param type_idx Type index to use if use_declaring_class is 'false'.
201     * @param rl_dest Result to be set to 0 or 1.
202     * @param rl_src Object to be tested.
203     */
204    void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final,
205                                    bool type_known_abstract, bool use_declaring_class,
206                                    bool can_assume_type_is_in_dex_cache,
207                                    uint32_t type_idx, RegLocation rl_dest,
208                                    RegLocation rl_src);
209
210    // Single operation generators.
211    LIR* OpUnconditionalBranch(LIR* target);
212    LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
213    LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
214    LIR* OpCondBranch(ConditionCode cc, LIR* target);
215    LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
216    LIR* OpFpRegCopy(int r_dest, int r_src);
217    LIR* OpIT(ConditionCode cond, const char* guide);
218    LIR* OpMem(OpKind op, int rBase, int disp);
219    LIR* OpPcRelLoad(int reg, LIR* target);
220    LIR* OpReg(OpKind op, int r_dest_src);
221    LIR* OpRegCopy(int r_dest, int r_src);
222    LIR* OpRegCopyNoInsert(int r_dest, int r_src);
223    LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
224    LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
225    LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value);
226    LIR* OpRegMem(OpKind op, int r_dest, RegLocation value);
227    LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
228    LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type);
229    LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type);
230    LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src);
231    LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
232    LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
233    LIR* OpTestSuspend(LIR* target);
234    LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
235    LIR* OpVldm(int rBase, int count);
236    LIR* OpVstm(int rBase, int count);
237    void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
238    void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
239    void OpTlsCmp(ThreadOffset offset, int val);
240
241    void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset);
242    void SpillCoreRegs();
243    void UnSpillCoreRegs();
244    static const X86EncodingMap EncodingMap[kX86Last];
245    bool InexpensiveConstantInt(int32_t value);
246    bool InexpensiveConstantFloat(int32_t value);
247    bool InexpensiveConstantLong(int64_t value);
248    bool InexpensiveConstantDouble(int64_t value);
249
250    RegLocation UpdateLocWide(RegLocation loc);
251    RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update);
252    RegLocation EvalLoc(RegLocation loc, int reg_class, bool update);
253    int AllocTempDouble();
254    void ResetDefLocWide(RegLocation rl);
255
256    /*
257     * @brief x86 specific codegen for int operations.
258     * @param opcode Operation to perform.
259     * @param rl_dest Destination for the result.
260     * @param rl_lhs Left hand operand.
261     * @param rl_rhs Right hand operand.
262     */
263    void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
264                       RegLocation rl_lhs, RegLocation rl_rhs);
265
266    /*
267     * @brief Dump a RegLocation using printf
268     * @param loc Register location to dump
269     */
270    static void DumpRegLocation(RegLocation loc);
271
272    /*
273     * @brief Load the Method* of a dex method into the register.
274     * @param dex_method_index The index of the method to be invoked.
275     * @param type How the method will be invoked.
276     * @param register that will contain the code address.
277     * @note register will be passed to TargetReg to get physical register.
278     */
279    void LoadMethodAddress(int dex_method_index, InvokeType type,
280                           SpecialTargetRegister symbolic_reg);
281
282    /*
283     * @brief Load the Class* of a Dex Class type into the register.
284     * @param type How the method will be invoked.
285     * @param register that will contain the code address.
286     * @note register will be passed to TargetReg to get physical register.
287     */
288    void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg);
289
290    /*
291     * @brief Generate a relative call to the method that will be patched at link time.
292     * @param dex_method_index The index of the method to be invoked.
293     * @param type How the method will be invoked.
294     * @returns Call instruction
295     */
296    LIR * CallWithLinkerFixup(int dex_method_index, InvokeType type);
297
298    /*
299     * @brief Handle x86 specific literals
300     */
301    void InstallLiteralPools();
302
303  private:
304    void EmitPrefix(const X86EncodingMap* entry);
305    void EmitOpcode(const X86EncodingMap* entry);
306    void EmitPrefixAndOpcode(const X86EncodingMap* entry);
307    void EmitDisp(uint8_t base, int disp);
308    void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp);
309    void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int disp);
310    void EmitImm(const X86EncodingMap* entry, int imm);
311    void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg);
312    void EmitOpReg(const X86EncodingMap* entry, uint8_t reg);
313    void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp);
314    void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,
315                     int scale, int disp);
316    void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg);
317    void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm);
318    void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp);
319    void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,
320                      int scale, int disp);
321    void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,
322                      uint8_t reg);
323    void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp);
324    void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2);
325    void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
326    void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
327    void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, int32_t imm);
328    void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
329    void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm);
330    void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
331    void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
332    void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl);
333    void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl);
334    void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition);
335
336    /**
337     * @brief Used for encoding conditional register to register operation.
338     * @param entry The entry in the encoding map for the opcode.
339     * @param reg1 The first physical register.
340     * @param reg2 The second physical register.
341     * @param condition The condition code for operation.
342     */
343    void EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition);
344
345    void EmitJmp(const X86EncodingMap* entry, int rel);
346    void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc);
347    void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp);
348    void EmitCallImmediate(const X86EncodingMap* entry, int disp);
349    void EmitCallThread(const X86EncodingMap* entry, int disp);
350    void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index,
351                   int scale, int table_or_disp);
352    void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset);
353    void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir);
354    void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
355                                  int64_t val, ConditionCode ccode);
356    void OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg);
357    void GenConstWide(RegLocation rl_dest, int64_t value);
358
359    /*
360     * @brief Return the correct x86 opcode for the Dex operation
361     * @param op Dex opcode for the operation
362     * @param loc Register location of the operand
363     * @param is_high_op 'true' if this is an operation on the high word
364     * @param value Immediate value for the operation.  Used for byte variants
365     * @returns the correct x86 opcode to perform the operation
366     */
367    X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value);
368
369    /*
370     * @brief Return the correct x86 opcode for the Dex operation
371     * @param op Dex opcode for the operation
372     * @param dest location of the destination.  May be register or memory.
373     * @param rhs Location for the rhs of the operation.  May be in register or memory.
374     * @param is_high_op 'true' if this is an operation on the high word
375     * @returns the correct x86 opcode to perform the operation
376     * @note at most one location may refer to memory
377     */
378    X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs,
379                        bool is_high_op);
380
381    /*
382     * @brief Is this operation a no-op for this opcode and value
383     * @param op Dex opcode for the operation
384     * @param value Immediate value for the operation.
385     * @returns 'true' if the operation will have no effect
386     */
387    bool IsNoOp(Instruction::Code op, int32_t value);
388
389    /**
390     * @brief Calculate magic number and shift for a given divisor
391     * @param divisor divisor number for calculation
392     * @param magic hold calculated magic number
393     * @param shift hold calculated shift
394     */
395    void CalculateMagicAndShift(int divisor, int& magic, int& shift);
396
397    /*
398     * @brief Generate an integer div or rem operation.
399     * @param rl_dest Destination Location.
400     * @param rl_src1 Numerator Location.
401     * @param rl_src2 Divisor Location.
402     * @param is_div 'true' if this is a division, 'false' for a remainder.
403     * @param check_zero 'true' if an exception should be generated if the divisor is 0.
404     */
405    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
406                                  RegLocation rl_src2, bool is_div, bool check_zero);
407
408    /*
409     * @brief Generate an integer div or rem operation by a literal.
410     * @param rl_dest Destination Location.
411     * @param rl_src Numerator Location.
412     * @param lit Divisor.
413     * @param is_div 'true' if this is a division, 'false' for a remainder.
414     */
415    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div);
416
417    /*
418     * Generate code to implement long shift operations.
419     * @param opcode The DEX opcode to specify the shift type.
420     * @param rl_dest The destination.
421     * @param rl_src The value to be shifted.
422     * @param shift_amount How much to shift.
423     * @returns the RegLocation of the result.
424     */
425    RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
426                                  RegLocation rl_src, int shift_amount);
427    /*
428     * Generate an imul of a register by a constant or a better sequence.
429     * @param dest Destination Register.
430     * @param src Source Register.
431     * @param val Constant multiplier.
432     */
433    void GenImulRegImm(int dest, int src, int val);
434
435    /*
436     * Generate an imul of a memory location by a constant or a better sequence.
437     * @param dest Destination Register.
438     * @param sreg Symbolic register.
439     * @param displacement Displacement on stack of Symbolic Register.
440     * @param val Constant multiplier.
441     */
442    void GenImulMemImm(int dest, int sreg, int displacement, int val);
443
444    /*
445     * @brief Compare memory to immediate, and branch if condition true.
446     * @param cond The condition code that when true will branch to the target.
447     * @param temp_reg A temporary register that can be used if compare memory is not
448     * supported by the architecture.
449     * @param base_reg The register holding the base address.
450     * @param offset The offset from the base.
451     * @param check_value The immediate to compare to.
452     */
453    LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg,
454                           int offset, int check_value, LIR* target);
455
456    /*
457     * Can this operation be using core registers without temporaries?
458     * @param rl_lhs Left hand operand.
459     * @param rl_rhs Right hand operand.
460     * @returns 'true' if the operation can proceed without needing temporary regs.
461     */
462    bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs);
463
464    /**
465     * @brief Generates inline code for conversion of long to FP by using x87/
466     * @param rl_dest The destination of the FP.
467     * @param rl_src The source of the long.
468     * @param is_double 'true' if dealing with double, 'false' for float.
469     */
470    void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double);
471
472    /*
473     * @brief Perform MIR analysis before compiling method.
474     * @note Invokes Mir2LiR::Materialize after analysis.
475     */
476    void Materialize();
477
478    /*
479     * @brief Analyze MIR before generating code, to prepare for the code generation.
480     */
481    void AnalyzeMIR();
482
483    /*
484     * @brief Analyze one basic block.
485     * @param bb Basic block to analyze.
486     */
487    void AnalyzeBB(BasicBlock * bb);
488
489    /*
490     * @brief Analyze one extended MIR instruction
491     * @param opcode MIR instruction opcode.
492     * @param bb Basic block containing instruction.
493     * @param mir Extended instruction to analyze.
494     */
495    void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir);
496
497    /*
498     * @brief Analyze one MIR instruction
499     * @param opcode MIR instruction opcode.
500     * @param bb Basic block containing instruction.
501     * @param mir Instruction to analyze.
502     */
503    void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir);
504
505    /*
506     * @brief Analyze one MIR float/double instruction
507     * @param opcode MIR instruction opcode.
508     * @param bb Basic block containing instruction.
509     * @param mir Instruction to analyze.
510     */
511    void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir);
512
513    /*
514     * @brief Analyze one use of a double operand.
515     * @param rl_use Double RegLocation for the operand.
516     */
517    void AnalyzeDoubleUse(RegLocation rl_use);
518
519    // Information derived from analysis of MIR
520
521    // The compiler temporary for the code address of the method.
522    CompilerTemp *base_of_code_;
523
524    // Have we decided to compute a ptr to code and store in temporary VR?
525    bool store_method_addr_;
526
527    // Have we used the stored method address?
528    bool store_method_addr_used_;
529
530    // Instructions to remove if we didn't use the stored method address.
531    LIR* setup_method_address_[2];
532
533    // Instructions needing patching with Method* values.
534    GrowableArray<LIR*> method_address_insns_;
535
536    // Instructions needing patching with Class Type* values.
537    GrowableArray<LIR*> class_type_address_insns_;
538
539    // Instructions needing patching with PC relative code addresses.
540    GrowableArray<LIR*> call_method_insns_;
541};
542
543}  // namespace art
544
545#endif  // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
546